JPH09331257A - DC offset cancel circuit - Google Patents

Abstract

(57) Abstract: A correction error is eliminated when the input level of a circuit for canceling a DC component included in a baseband analog signal output from a high frequency receiving unit of a radio paging receiver is large. A baseband analog signal is input to one of buffers 1, amplified by an amplifier 2, digitally converted by an A / D converter 3 and used as one input of an adder 5, and the level of the digital value is set as a level. The detector 4 monitors and the moving average value is obtained by the averaging circuit 7. The control unit 8 stores the moving average value of the DC component of the noise in the memory 9 according to the information of the noise or the significant section obtained by the determination unit 6 and the information of the level detector 4, and the detection level of the significant section is small. When the detection level is high, the stored value of the memory 9 is subtracted and input to the adder 5 to cancel the DC offset. When the detected level is high, the stored value of the memory 9 is given to the adder 11 to add the reference value, and the analog value is converted. It is configured to be applied to the other input of the buffer 1 to correct the DC shift amount.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in, for example, a demodulation circuit of a radio paging receiver and the like, and digitally converts a baseband analog signal output from a harmonic wave receiving unit into a demodulating unit or a decoder unit. The present invention relates to a direct current (DC) offset cancel circuit having a function of removing a direct current component superimposed on a signal.

[0002]

2. Description of the Related Art A radio frequency receiver of a radio paging receiver converts a signal intermittently received by battery saving or the like into a baseband analog signal and outputs it. This baseband analog signal is analog / digital (A / D)
It is converted into a digital signal by the converter and input to the demodulation section or the decoder section. In the demodulation section or decoder section, error correction is performed, bit synchronization and frame synchronization are performed, and the number RO
It collates with the calling number of M and demodulates and outputs when it matches.

In such a radio paging receiver, the baseband analog signal output from the high frequency receiving section is an antenna input signal which is intermittently received, and is subjected to frequency selective amplification and frequency conversion in the high frequency receiving section to form a baseband signal. Until then, a direct current component due to an analog element or the like may be superimposed. If a baseband signal on which such a DC component is superimposed is digitally converted as it is and input to the decoder unit, an error occurs in the determination by the threshold value when detecting various signals in the demodulation unit or the decoder unit. There is. Therefore, D that removes the DC component in the circuit portion that digitally converts the baseband analog signal is used.
A C offset cancel circuit is used.

FIG. 1 is a diagram showing a configuration example of a conventionally used DC offset cancel circuit. In the figure, 101 and 103 are inversion buffers, and 102 is an inversion buffer 101.
An offset voltage (DC component canceling voltage) application terminal for canceling the DC component (DC offset) of the signal (IN) input to the input terminal 104 is an A / D converter for converting an analog value into a digital value. The signal (IN) input to the inverting buffer 101 is a baseband analog signal output from the high frequency receiver.

In the inverting buffer 101, the DC component in the analog input signal can be changed by manually adjusting the offset voltage value applied to the offset voltage applying terminal 102. The inverting buffer 103 inverts the signal input from the inverting buffer 101 again and outputs it. The A / D converter 104 converts the signal into a digital signal and inputs it to the decoder section. In this way, by presetting the voltage applied to the terminal 102 of the inverting buffer 101, the DC component included in the analog input signal is canceled.

[0006]

However, in the above circuit, the DC offset value to be canceled is different for each receiver and is a fixed value that is manually set. However, there is a drawback in that automatic correction cannot be performed for changes in the DC offset amount due to changes in temperature and changes over time.

Further, when the DC offset value is automatically canceled, correction by a digital value can be considered. In this case, it is necessary to consider the influence of the change in the received signal level. For example, when the amplitude of the amplified significant signal at the A / D converter input exceeds the maximum voltage value and the minimum voltage value, that is, when a sine wave input is taken as an example of the significant signal, the A / D conversion is apparently performed. If a DC component is corrected for the digital value output from the A / D converter when the input of the converter is a rectangular wave, the significant signal waveform may be erroneously corrected. There is.

2A and 2B are explanatory diagrams of the input signal waveform of the A / D converter. FIG. 2A shows a significant signal (in the case of a sine wave) waveform when the level is low, and FIG. 2B shows an excessive input state. The waveform of the significant signal is shown. In the input waveform of A / D converter,
As the input signal level in (A) increases, the input range (allowable range) is exceeded, and a saturated state results in a waveform like (B), which is directly converted to a digital value.
If a DC offset value detected in advance is added to the digital value by an adder to correct the digital value, the correction cannot be performed by a simple calculation in the saturated portion of the excessive input exceeding the allowable level.

An object of the present invention is to provide a DC offset cancel circuit capable of automatically correcting even in a reception over-input state regardless of the magnitude of the amplitude level of a reception signal.

[0010]

A DC offset cancel circuit according to the present invention converts a baseband analog signal output from a high frequency receiving unit into a digital value and inputs the digital value to the baseband analog signal. A circuit for removing the included DC component, wherein the baseband analog signal is used as one input, and the reference voltage value of the baseband analog signal is corrected by the reference voltage value input from the other and output. , An amplifier for amplifying the output of the buffer, an A / D converter for converting the output of the amplifier into a digital value, and an output of the A / D converter as one input, and canceling a DC component input from the other A first adder that subtracts and outputs a value, an output of the first adder is given to the decoder section, and a noise section of the output of the first adder A determining section for outputting a signal discrimination information indicating whether discrimination was significantly signal or noise by the threshold between,
An averaging circuit for obtaining and outputting a moving average value of the output digital value of the A / D converter when instructed to operate;
A level detector that detects the output level of the D converter, a memory that sequentially overwrites and stores only the moving average value of the noise section calculated by the averaging circuit, and a reference voltage of the baseband analog signal that is input to the buffer. A reference value register in which a value is preset and stored as a digital value, and a second adder which receives the output of the reference value register as one input and adds and outputs the DC component offset value input from the other ,
According to the D / A converter that converts the output of the second adder into an analog value and uses it as the reference voltage value that is input to the other of the buffers, and the signal determination information obtained from the determination unit,
In the noise section, the averaging circuit is operated to sequentially overwrite and store the moving average value of the noise section in the memory, and in the significant section, the operation of the averaging circuit is stopped to store the moving average of the noise section in the memory. When the output of the level detector is smaller than a predetermined level, the value is input to the other of the first adders, and when the output of the level detector is larger than the predetermined level, Is provided with a control unit for controlling so as to input to the other of the second adders.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION According to the present invention, the level detector 4 monitors the level of a baseband analog signal output from a high-frequency receiver, and when the input level is low, the A / D converter 3 is used.
After being converted to a digital value by the adder 5, the adder 5 cancels the DC offset value in the noise section read from the memory 9, and when the input is excessive, the adder 11 adds a reference value to buffer the signal converted to an analog value. 1 to correct the DC offset in the analog signal.

[0012]

EXAMPLES Examples of the present invention will be described. FIG. 3 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 1 is a buffer, and the reference voltage value after the DC offset value correction output from the D / A converter 12 is input from the other and reflected in the received signal. Reference numeral 2 is an amplifier for amplifying the output signal of the buffer 1, 3 is an A / D converter for converting an analog signal of the output of the amplifier 2 into a digital signal, and 4 is an amplitude level of the output of the A / D converter 3. A level detector, 5 is an adder for canceling DC offset with a digital value when the input signal is not over-input, and 6 outputs a signal output from the A / D converter 3, and the signal is a significant signal or noise. A determination unit that determines either of them and outputs signal determination information indicating whether it is a significant signal or noise, and 7 is an averaging circuit that calculates a moving average value of the output of the A / D converter 3. 8 is a determination unit 6
The averaging circuit is operated only when the signal from is indicating noise, and the obtained value is output to the memory 9 as an offset value. When the signal from the judging unit 6 indicates a significant signal, the averaging circuit 7 is a control unit that stops 7 and outputs the offset value stored in the memory 9 to the adder 5. Reference numeral 9 is a memory for storing the offset value obtained by the averaging circuit 7 according to an instruction from the control unit 8.

Reference numeral 10 is a reference value register for presetting and storing the reference voltage value of the input signal as a digital value, and 11
Is an adder for adding and outputting the offset value read from the memory 9 and the value of the reference value setting register 10 according to the instruction of the control unit, and 12 is for converting the digital value of the output of the adder 11 into an analog value, It is a D / A converter that outputs to the buffer 1 as a reference voltage value with the DC component removed.

[Operation] Specific examples of the present invention will be described below. First, the baseband analog signal from the harmonic receiver is amplified by the amplifier 2 and converted from an analog value to a digital value by the A / D converter 3. The determination unit 4 outputs the received signal converted into a digital value to the decoder unit and determines whether the signal is a significant signal such as a message sent from the transmission side.
Alternatively, it is determined whether the signal does not include a meaningful signal, that is, noise, and the determination result is output to the control unit 6 as signal determination information. The control unit 6, which has received the determination result of the significant signal or the noise, first operates the averaging circuit 7 when the signal indicates the noise. Averaging circuit 7 is A
The moving average value of the digital value of the noise output from the / D converter 3 is obtained, the DC offset value is calculated from this value, and the control unit 8 is notified. The control unit 8 sequentially stores the value in the memory 9
To memorize.

Next, when the information from the judging section 6 indicates a significant signal, the control section 8 first stops the operation of the averaging circuit 7,
The DC offset value detected in the noise section and stored in the memory 9 is read. At this time, the control unit 8 simultaneously monitors the output signal of the level detector 4 and outputs it to the adder 5 when it shows a certain level or less, that is, when the significant signal at that time is sufficiently smaller than its allowable maximum amplitude. The adder 5 is A
D detected in the noise interval from the significant signal output of the D / D converter 3
Subtract the C offset value. At this time, D from the control unit 8
Only the adder 5 outputs the C offset value, and the adder 1
No output to 1. Therefore, in the reference value register 10,
The reference voltage value when the DC component is 0, that is, the center value of the signal waveform input to the buffer 1 in the ideal state is set as a digital value, and the reference voltage value is directly set as D.
The / A converter 12 converts it into an analog value and uses it as the other input of the buffer 1.

On the other hand, when the information input from the judgment unit 6 to the control unit 8 indicates a significant signal and the output of the level detector 4 shows a certain level or more, that is, the amplitude of the significant signal at that time is When the output waveform of the A / D converter 3 is sufficiently large and sticks to the upper and lower limit values, the DC offset value detected in the noise section for the significant signal is directly calculated by the adder 5 as a digital value. Then,
There is a possibility that incorrect correction may be made due to inversion of the value in a place where the amplitude is large. Therefore, the control unit 8 switches and outputs the DC offset value from the adder 5 to the adder 11 according to the result of the level detector 4. At this point, it is possible to know how much the DC offset value is superimposed on the output signal of the amplifier 2, so the adder 11 subtracts the detected DC offset value from the reference voltage value in advance to correct the reference value itself. deep. The digital value serving as the reference of the received signal is converted into an analog value by the D / A converter 12 and used as a reference voltage value applied to the other input terminal of the buffer 1. By this series of operations, even when the input signal level is large and the waveform of the output of the amplifier 2 exceeds the permissible level and is shaken off, the correction is performed in the preceding stage of the amplifier 2, so that the DC offset value is accurate. Can be corrected.

[0017]

As described in detail above, according to the present invention, a DC offset value due to an analog element such as an amplifier is detected without being affected by the polarity of a significant signal, and the DC offset is automatically canceled. can do.
Further, according to the present invention, the significant signal level is used to switch between correction of the analog value before input to the amplifier and correction of the digital value after A / D conversion.
The DC offset value can be reliably canceled regardless of the input level of the significant signal.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a conventional circuit configuration example.

FIG. 2 is an explanatory diagram of an input signal of an A / D converter.

FIG. 3 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 101, 103 Inversion buffer 102 Offset voltage application terminal 104 A / D converter 1 Buffer 2 Amplifier 3 A / D converter 4 Level detector 5 Adder 6 Judgment unit 7 Average circuit 8 Control unit 9 Memory 10 Reference value register 11 Addition Device 12 D / A converter

Claims (1)

[Claims] 1. A circuit for removing a DC component contained in a baseband analog signal when the baseband analog signal output from a high frequency receiving unit is converted into a digital value and input to a decoder unit, wherein: A buffer that receives a baseband analog signal as one input and corrects and outputs a reference voltage value of the baseband analog signal with a reference voltage value that is input from the other, an amplifier that amplifies the output of the buffer, and the amplifier An A / D converter for converting the output of the above into a digital value, and a first adder which takes the output of the A / D converter as one input and subtracts the DC component offset value input from the other to output , The output of the first adder is given to the decoder section, and the noise section and the significant section of the output of the first adder are discriminated by a threshold value to indicate whether it is a significant signal or noise. A decision section for outputting signal discrimination information, an averaging circuit for obtaining and outputting a moving average value of output digital values of the A / D converter when instructed to operate, and detecting an output level of the A / D converter A level detector, a memory for sequentially overwriting and storing only a moving average value of the noise section calculated by the averaging circuit, and a reference voltage value of a baseband analog signal input to the buffer, which is preset as a digital value. A stored reference value register, a second adder that receives the output of the reference value register as one input, adds the DC component cancellation values input from the other, and outputs the added value, and the output of the second adder Is converted into an analog value and input to the other of the buffers as the reference voltage value, and the averaging circuit is used in the noise section in accordance with the signal discrimination information obtained from the determination unit. The moving average value of the noise section is sequentially overwritten and stored in the memory, and the moving average value of the noise section stored in the memory is stopped as the DC component offset value in the significant section. , When the output of the level detector is smaller than a predetermined level, it is input to the other of the first adders, and when the output of the level detector is larger than the predetermined level, the second adder A DC offset cancel circuit including a control unit for controlling the other input.