JPH09331321A - Synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the synchronization circuit in which mis-detection or missing of detection of a synchronizing signal is reduced even when serial data are read at a high speed from a high density recording optical disk. SOLUTION: In the synchronization circuit detects a synchronizing signal from serial data whose head is arranged with a synchronization pattern, an output of a serial input shift register 20 shifting the serial data by a high frequency clock is given to an ECL/TTL conversion circuit in which serial data are converted into parallel data, and in the case that the serial data is an NRZI code, an NRZI/NRZ conversion circuit 22 converts the serial data into an NRZ code. The output is given to a parallel input shift register 23 consisting of a plurality of parallel input latch circuits 23a-23e connected in cascade and shifting data by a 1/3 frequency division clock. An output state in matching with the synchronization pattern is detected by a synchronization pattern detection circuit based on output states P1-P15 of the parallel input latch circuits 23a-23e.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit for detecting a synchronizing signal from serial data in which the synchronizing signal is arranged.

[0002]

2. Description of the Related Art A sync signal recorded on an optical disc or the like is an important signal as a signal for knowing the beginning of data when the disc is reproduced, and a missing (detection omission) or a sync signal is detected at an incorrect position in detecting the sync signal. If it does (erroneous detection), it cannot be reproduced as correct data.

Therefore, as a sync signal detecting method for detecting a sync signal from serial data recorded on an optical disk or the like, in a recording modulation method in which a position of the sync signal is predicted and a detection window is provided, or a pattern of the sync signal is adopted. A synchronization signal detection method is adopted in which a pattern that is not generated, that is, a prohibition pattern is selected, or an error detection code is assigned to the synchronization signal itself to minimize a detection error.

[0004]

If the detection window is widened or the matching degree of pattern matching is weakened in order to eliminate the omission of detection of the synchronization signal, a contradiction arises in that the possibility of error detection increases, resulting in the detection window. It is not a fundamental improvement only by manipulating the degree of agreement and the degree of coincidence. Furthermore, when the recording density of the disc is increased to realize an optical disc reproducing device with a high transfer rate and the reading speed becomes high, the synchronizing circuit itself cannot keep up with the reading speed due to a signal delay in the synchronizing circuit and the like. The probability of making a detection error increases and cannot be ignored.

FIG. 7 shows an example of a conventional synchronizing circuit, but the problem that the reading speed cannot be followed at a high transfer rate based on the synchronizing circuit will be described. As shown in FIG. 7, the synchronous circuit is connected in cascade.
The serial input type shift register 13 including two latch circuits 1 to 12, the output Q of the predetermined latch circuit is NO.
The synchronous pattern detection circuit 16 is provided which is composed of an AND gate 15 which is connected through the T circuit 14 and which is directly connected to the output Q of another latch circuit.

A serial data signal is input to the first stage latch circuit 1 of the serial input type shift register 13, and a clock signal is supplied to each of the latch circuits 1 to 12. In the synchronization circuit, for example, a serial data signal (... 00001110000110000 ...)
From the synchronization pattern (00111000)
0110) is detected as the output detection signal AND
A serial signal, which is wholly or partially coincident with the synchronization pattern, is detected as a synchronization signal from the gate 15.

When detecting a pattern that completely matches the synchronization pattern, the output "0" of the latch circuit is NOT.
The output "1" of the latch circuit is directly input to the AND gate 15 via the circuit 14 to obtain the synchronization signal SY. By the way, when reproducing a high density recording optical disc, the data transfer rate is as high as 160 Mbps, and the clock frequency for realizing this may be as high as 85 MHz.

In the case of detecting a synchronization pattern from a signal having such a clock frequency of 85 MHz, if the number of stages of the latch circuits forming the serial input type shift register 13 in the synchronization circuit is large, the influence of the delay of the latch circuits becomes large. In such a case, in the synchronizing circuit, jitter occurs in the phase relationship between the shifted serial data and the clock, resulting in erroneous detection or omission of detection of the synchronizing signal, making it difficult to decode the data.

The present invention provides a synchronizing circuit capable of reducing erroneous detection and omission of detection of a synchronizing signal even when serial data is read out at high speed from a high density recording optical disc or the like.

[0010]

SUMMARY OF THE INVENTION A synchronous circuit of the present invention is a parallel input type shift register having a plurality of parallel input type latch circuits connected in cascade for latching the output of a serial / parallel converting circuit for converting serial data into parallel. A pattern matching the synchronization pattern is detected from the output state of each of the parallel input type latch circuits. The parallel input type shift register can reduce the frequency of data transfer.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION In order to detect a synchronization signal from the serial data, the synchronization circuit of the present invention inputs the serial data to a parallel input type shift register and converts the serial data into parallel signals so that matching of the synchronization patterns can be seen. To do.

As an example, serial data (... 0000111
0000110000 ...) to a 12-bit synchronization pattern (001110
000110) is detected, a synchronous circuit as shown in FIG. 1 is used.

As shown in FIG. 1, the synchronous circuit of the present invention is
Latch circuits 20a and 20b that shift with a high frequency clock
And 20c are cascade-connected, a serial input type shift register 20 composed of an ECL circuit, a 3-bit parallel input ECL / TTL conversion circuit 21 for converting the ECL level of the output Q of each latch circuit into a TTL level, and E
The NRZI code output from the CL / TTL conversion circuit 21 is set to N
An NRZI / NRZ conversion circuit for converting into RZ and a parallel input type shift register 23 to which three-bit parallel input latch circuits 23a to 23e are connected in cascade are provided.
In the following description, serial data will be referred to as NRZ.
The description will be made by omitting the NRZI / NRZ conversion circuit 22 from the synchronization circuit. When the serial data is recorded with the NRZI code such as an optical disk, the NRZI / NRZ conversion circuit 22 may be required.

Each latch circuit of the serial input type shift register 20 shifts the serial data with a high frequency clock, and each latch circuit of the parallel input type shift register 20 divides the high frequency clock by 3 in this case. Data is loaded and shifted by the clock. In this case, since the serial input type shift register 20 is composed of the ECL circuit, it operates at a high speed and can absorb the jitter generated in the phase relationship between the high frequency clock and the serial data.

Then, the parallel input type shift register 23 converts the serial data into 3-bit parallel data regardless of the phase. Since the sync signal converted into 3-bit parallel data appears in any of the three phases, the sync signal can be obtained by preparing three kinds of sync pattern detection circuits.

Therefore, in order to detect the three types of synchronization patterns, the output states from the outputs Q1, Q2, and Q3 of the 3-bit parallel input latch circuits 23a to 23e of the parallel input type shift register 23 are set in the subsequent stage. From the latch circuit, P1, P2, P3 ... P13, P14,
P15, and from these output states P1 to P15,
In order to detect the bit synchronization pattern, the output states P15 to P4 are taken out as the first output, the output states P14 to P3 are taken out as the second output, and the output states P13 to P2 are taken out as the third output.

Hereinafter, the first output state will be referred to as P [15:
4], the second output state is described as P [14: 3], and the third output state is described as P [13: 2]. FIG. 2 shows an example of a sync pattern detection circuit for detecting a sync pattern from the first to third output states.

Since the synchronization pattern to be detected is 12-bit (001 110 000 110), the synchronization pattern detection circuit 26 for detecting the synchronization pattern by a perfect match detects the first output state P [15: 4]. 2A, the output states P4, P5, P9 to P11, and P15 are input to the AND gate 25 through the NOT circuit 24, and the output states P6 to P8 and P13 to P14 remain unchanged. A bus is connected to the outputs Q1 to Q3 of the latch circuits 23a to 23e so as to be input to the AND gate 25.

In the synchronization pattern detection circuit 26 thus constructed, the output state P4 is output to the AND gate 25.
If a pattern matching with the synchronization pattern is input from P15 to P15, a high level signal is output from the AND gate 25 to obtain the synchronization signal SY1.

A synchronous pattern detection circuit 2 having the same structure
6 as shown in FIG. 2 (B) and FIG. 2 (C).
And prepare the output state P of the second output state P [14: 3].
3 to P14 are input and the third output state P [13:
2] output states P2 to P13 are input, and when they are completely coincident with the synchronization pattern, a high level signal is output from the AND gate 25 to output the synchronization signals SY2 and SY.
Get 3 each. It goes without saying that these sync signals all have the same pattern, but only the detected phases are different.

Hereinafter, the input serial data (... 1110001110
An example of detecting the synchronization pattern (001 110 000 110) from (000110011100111111001100001100110) will be described. Although it is not known where to divide the input data to decode the data, the parallel input latch circuit is shifted by converting the input data into 3-bit parallel data regardless of the phase of the serial data. Then, the output states P1 to P
The output state at a certain point of 15 is as follows.

1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 1 1 0 1 1 0 0 0 1 0 0 0 1 The vertical bits in this bit array sequentially represent the output states from Q1 to Q3 of the parallel input type latch circuits from the latter stage.

Each parallel input type latch circuit 23a ...
Looking at the output state from 23e, the output state that matches the synchronization pattern is the bit underlined, and this pattern is SY3, that is, the output state of the third output state [13: 2]. The synchronization pattern is detected in P2 to P13. That is, the detection window of the synchronization signal SY3 is expressed in the output state as follows.

[0024]

Similarly, the detection window of the synchronization signal SY1 is as follows. 0 1 0 1 ・ ・ ・ (P4 P7 P10 P13) 0 1 0 1 ・ ・ ・ (P5 P8 P11 P14) 1 0 0 0 ・ ・ ・ (P6 P9 P12 P15)

Similarly, the detection window of SY2 is as follows.

The sync pattern is recorded as a frame sync signal or a sector sync signal for detecting a frame or a sector at the head of data to be recorded on an optical disk or the like. The output of the sync pattern detection circuit 26 is shown in FIG. Such synchronization signals SY1 to SY3 are detected for each sector.

The respective outputs from the respective synchronization pattern detecting circuits 26 are supplied to the OR gate 2 in the circuit as shown in FIG.
The latch circuit 2 until the synchronization pattern following the synchronization signals SY1, SY2, and SY3 is input.
Hold at 8.

Further, each synchronizing signal held in the latch circuit 28 is, for example, a signal P which determines the phase of each sector.
A signal PH which is output from the latch circuit 28 as H1, PH2 and PH3 and is held during the rising period between the synchronization signals as shown in FIG.
The data bits are re-delimited by 1, PH2 and PH3 to decode the data.

For example, in the case of the serial data, the data bit (1 byte) according to the phase of the succeeding PH3 when taken out from the detection window of SY3 as the synchronization pattern is divided as follows. For convenience, a slash "/" is used to indicate a data bit break, and the right side shows a detection window for the synchronization signal SY3.

1 0/1 0 0 0/1 0 1 1/1 0 1 1/0 1 0 0 /, 1 0 0 0 ・ ・ ・ (P4 P7 P10 P13) 1/0 1 0 1/0 1 1 1/0 1 0 1/1 0 1 1 /, 0 1 0 1 ・ ・ ・ (P2 P5 P8 P11) 1/0 1 0 1/1 0 1 1/0 0 0 1/0 0 0 1 /, 0 1 0 1 ・ ・ ・ (P3 P6 P9 P12)

That is, in the sector in which PH3 is set, the 3-bit unit division of the 12-bit data bit following the synchronization signal SY3 is in the output state (P11, P12, P13) as is clear from the configuration of the detection window of SY3. ) Separated.

Similarly, the data bits in the sector in which PH1 has risen are divided by the output states (P13, P14, P15) as apparent from the detection window, and the data bits in the sector in which PH2 has risen are in the output state. (P12, P1
3, P14).

As described above, since the data bits following the synchronization signals SY1 to SY3 detected in different phases also pass through the parallel input type shift registers 23a to 23e, the outputs PH1, PH2 and PH3 from the latch circuit 28 are output.
It is possible to define which piece of data is 1 byte by the rising edge of. Then, the 12-bit NRZ data is converted into 8-bit digital data and decoded.

As described above, the detection error of the synchronization pattern caused by the high frequency can be suppressed by detecting the serial data after converting the serial data into parallel data. Then, if it is known at which phase the sync pattern can be detected, the phase of the data thereafter may be matched with this.

By the way, the following conditions are necessary as a countermeasure for preventing a detection error even if a few errors are mixed in the reproduction data of the high-density recorded optical disk. (1) A pattern that employs a prohibition pattern as a synchronization pattern and that occurs only when a 1-bit error is mixed into normal data is too weak. Therefore, it is necessary to create a pattern in which the prohibited patterns are overlapped many times (condition 1).

(2) In order to be able to reliably detect even if some errors are mixed in the synchronization pattern, it is only necessary to make the synchronization pattern long to some extent and to detect a part. However, the wider the allowable range of the degree of coincidence, the higher the possibility of erroneous detection. Therefore, detection is performed with a detection window that is as accurate and narrow as possible. Further, if the same pattern is repeated in the synchronization pattern, the synchronization signal may be detected a plurality of times depending on the allowable range of the degree of coincidence, so it is necessary to assign an irregular pattern as much as possible (condition 2).

A synchronization pattern based on a prohibited pattern that satisfies the above condition 1 is obtained. As an example, a (1,7) run-length limited code (RLL code) is used as a recording code used for recording on an optical disc.

This RLL code is described in US Pat.
No. 1 specification (Japanese Examined Patent Publication No. 63-7051) and the like, which have at least one and at most seven "0" s between adjacent "1" s (d, k). ) Code with run length limited code (RL) with a code rate of 2/3
L code). According to the RLL code described in the above document, the (1,7) RLL code has a 2-bit pattern of 3
It is converted into a bit pattern and expressed in NRZ notation as follows.

A = 000, b = 001, c = 010, e
= 100, f = 101

In the 3-bit pattern, in order to suppress 0 run to 7 or less, the pattern "aa" is prevented from appearing, and "aa" is in the middle regardless of how the bits are separated. If the pattern is included,
It is a prohibited pattern.

For example, consider whether the byte of S = (001 000 000 100) is a prohibited pattern. If this is learned in the notation of the 3-bit pattern, it can be expressed as "baae", and "aa" is included.

However, the method of dividing the pattern is (0 01
0 000 001 00), the pattern of S is
For example, (000 010 000 001 000), that is, it can be said that it is a part of "acaba", for example, if it is learned from the notation of the above pattern, and since "aa" is not included in this, it is not a prohibited pattern. Absent.

In such a notation, a pattern including "aa" is always a prohibited pattern, no matter how the pattern is divided, and the shortest pattern satisfying this is 14 bits and 0
The pattern that the run becomes 6,7 or 7,6 with 1 in between,
That is, two patterns of S1 = (000 000 100 000 00) S2 = (000 000 010 000 00) can be prohibited patterns.

In the NRZI notation in which the prohibition pattern S1 is used for recording on the optical disc, (0 000 000 111 111
11), or inverted (1 111 111 000 000 00)
And the pit length is (7,8).

Similarly, the prohibition pattern S2 is (0 00
0 000 011 111 11) or inversion (1 111 11 11
1 100 000 00) and the pit length is (8,7).

When such a prohibition pattern is obtained, next, in order to satisfy the condition 2, the sync pattern is expressed as (010 100 000 001 000 000 000 010 000) in NRZ notation.
001 010 001 010) can be selected.

If this is expressed in NRZI (011 000 00
0 001 111 111 100 000 001 100 001 100) or its reversal (100 111 111 110 000 000 011 111 110 011 110 01
It becomes 1). The NRZI pattern is represented by the pit length recorded on the optical disc as (1,2,8,8,7,2,4,2,2), and the (8,8,7) triple prohibited pattern It depends.
So, if you decompose (8,8,7), (8,8) becomes (8,7),
It can be said that both of (7,8) are taken, and that the triple prohibition pattern is applied together with the latter (8,7). In addition, since it is irregular as a whole, the above conditions 1 and 2 are satisfied.

A synchronization circuit for detecting a synchronization signal from serial data adopting the prohibition pattern is taken as an example in which, for simplicity, 14 bits of the shortest prohibition pattern S1 = (000 000 100 000 00) are used as the synchronization pattern. Explain.
The basic structure is the same as that of the synchronous circuit shown in FIG.

FIG. 5 shows a synchronizing circuit for detecting a synchronizing signal from serial data which employs the prohibiting pattern of S1 as a synchronizing pattern. The same components as those of the synchronous circuit of FIG. 1 are designated by the same reference numerals. FIG.
As shown in, the synchronous circuit includes a serial input type shift register 20 in which serial input type latch circuits 20a, 20b, 20c that are shifted by a high frequency clock are connected in cascade.
An ECL / TTL conversion circuit 21 for inputting the outputs of these latch circuits, an NRZI / NRZ conversion circuit 22, and a parallel input type shift register 24 to which three-bit parallel input type latch circuits 24a to 24f are connected in cascade. There is. Also in this case, if the serial data is NRZ,
The NRZI / NRZ conversion circuit 22 is not required.

Then, each latch circuit of the serial input type shift register 20 loads and shifts data with a high frequency clock, and each latch circuit of the parallel input type shift register 24 divides the high frequency clock by 3 in this case. Data is loaded and shifted with a clock divided by three.

As shown in FIG. 6, the sync pattern detecting circuit of the sync circuit is the same as the sync pattern detecting circuit 29a to which the output states P1 to P14 of the parallel input type latch circuits 24a to 24f are input. Output state P
2 to P15 are input to the synchronization pattern detection circuit 29b,
Similarly, it is composed of a synchronization pattern detection circuit 29c to which output states P3 to P16 are input. One of the inputs of each synchronization pattern detection circuit is connected to the NOR gate 26 through the NOT circuit 25. Further, the outputs of the sync pattern detection circuits 29a to 29c are configured to be input to the OR gate 27 and the 3-bit parallel input type latch circuit 28.

The detection of the synchronization pattern of the synchronization circuit will be described below. Here, as shown in the figure, the output states of the respective 3-bit parallel input type latch circuits 24a to 24f are sequentially set to P1, P2 ... P18 from the subsequent stage.
First, as input serial data, for example, ECL level serial data of the following NRZI code is input to the first stage latch circuit 20a of the serial input type shift register 20. Hereinafter, in order to make the input serial data easy to understand, a slash "/" is added to each 3 bits.
Separated by. Input serial data = ... 0/011/111/110/000/000/011/00
0/0 ...

This serial data is the ECL / TT
It is input to the L conversion circuit 21 and serial / parallel conversion is performed. The serial data converted into parallel data is converted into NRZ by the NRZI / NRZ conversion circuit 22.
Converted to code.

The output states of the bits output from the parallel input type 3-bit latch circuits 24a to 24f will be shown from the following stage. P1 = 0, P4 = 0, P7 =
0, P10 = 0, P13 = 0, P16 = 0, P2 = 1, P5 =
0, P8 = 0, P11 = 0, P14 = 0, P17 = 1, P3 =
0, P6 = 0, P9 = 1, P12 = 0, P15 = 0, P18 =
In the output state of 0, the synchronization pattern is (000 000 100 000 00) as described above, so the output states of P3 to P16 match the synchronization pattern.

Therefore, when this pattern is input to each of the sync pattern detection circuits 29a to 29c, "1" is output only from the sync pattern detection circuit 29c, and "0" is output from the other sync pattern detection circuits 29a and 29b. Is output. Then, N of the synchronization pattern detection circuit 29c
The output of the OR gate 26c is detected by the OR gate 27 as the synchronization signal SY3.

As other output states, P1 = 0, P4 = 0,
P7 = 1, P10 = 0, P13 = 0, P16 = 0, P2 = 0,
P5 = 0, P8 = 0, P11 = 0, P14 = 0, P17 = 1,
P3 = 0, P6 = 0, P9 = 0, P12 = 0, P15 = 0,
In the output state of P18 = 0, the output states of P1 to P14 match the synchronization pattern, and the synchronization pattern detection circuit 29
It is detected as the synchronizing signal SY1 from the NOR gate 26a of a.

As another phase output state, P1 = 0,
P4 = 0, P7 = 0, P10 = 0, P13 = 0, P16 = 0,
P2 = 0, P5 = 0, P8 = 1, P11 = 0, P14 = 0,
P17 = 1, P3 = 0, P6 = 0, P9 = 0, P12 = 0,
In the output state of P15 = 0, P18 = 0, the output states of P2 to P15 match the synchronization pattern, and the NOR gate 26b of the synchronization pattern detection circuit 29b outputs the synchronization signal SY2.
Is detected as

Then, the respective synchronizing signals are taken out from the OR gate 27 as synchronizing signals SY1 and SY2, respectively. As described above, since the sync signals detected from the three different phases can be detected as the sync signals of the predetermined sector, the detected sync signals are respectively detected by the 3-bit parallel input type latch circuit 28 as follows. By holding the synchronization signal until it is detected, the data can be divided for each sector.

In this case, the sector data by the output PH1 held by the synchronizing signal SY1 may be divided into 3-bit divisions by the output states P1, P2 and P3, and the output held by the synchronizing signal SY2. P
It is sufficient to divide the 3-bit sector data by H2 into output states P2, P3, and P4.
It is sufficient to divide the 3-bit sector data by the output PH3 held by Y3 into output states P3, P4, and P5.

As described above, by dividing the data following the detected sync signal in the output state, it becomes possible to reliably detect the data for each sector. Even if it is adopted in a device having a transfer rate, there is no possibility of erroneously detecting data and a sync signal.

In each of the above-described embodiments, a simple example in which the number of bits of the synchronization pattern is small has been described. However, when the number of bits of the synchronization pattern is arbitrarily increased, a parallel input type shift register having the increased number is configured. The synchronous circuit can be easily realized only by increasing the number of stages of the parallel input type latch circuit.

[0063]

According to the synchronizing circuit of the present invention, it is possible to detect the synchronizing pattern arranged in the high transfer serial data without error regardless of the phase of the serial data.

[Brief description of drawings]

FIG. 1 is a circuit used for serial / parallel conversion of a synchronizing circuit of the present invention.

FIG. 2 is a synchronization pattern detection circuit of the synchronization circuit of the present invention.

FIG. 3 is an output circuit of the synchronizing circuit of the present invention.

FIG. 4 is a waveform diagram illustrating the operation of the output circuit of the synchronizing circuit of the present invention.

FIG. 5 is a circuit for another serial / parallel conversion of the synchronizing circuit of the present invention.

FIG. 6 is another synchronization pattern detection circuit of the synchronization circuit of the present invention.

FIG. 7 shows a conventional synchronizing circuit.

[Explanation of symbols]

20 ... Serial input type shift register 23. Parallel input type shift register 26, 29a, 29b, 2
9c ··· Sync pattern detection circuit

Claims (4)

[Claims] 1. A synchronization circuit for detecting a synchronization signal from serial data in which a synchronization pattern is arranged at the head of the data, wherein a serial / parallel conversion circuit for converting the serial data into parallel data, and a serial / parallel conversion circuit A parallel input type shift register having a plurality of parallel input type latch circuits connected in cascade for latching an output, and an output state that matches the synchronization pattern from the output state of each parallel input type latch circuit of the parallel input type shift register And a synchronization pattern detection circuit for detecting the. 2. A serial input type shift register in which a plurality of serial input type latch circuits are connected in cascade is provided on the input side of the serial / parallel conversion circuit.
2. The synchronizing circuit according to claim 1, wherein each output of the plurality of serial input type latch circuits is input to a parallel conversion circuit. 3. The synchronization pattern has a minimum run "
2. The synchronizing circuit according to claim 1, wherein the inhibition pattern is a (d, k) code having a maximum run of "7" and a code rate of 2/3 and a run length limited code. 4. A synchronization circuit according to claim 1, further comprising a latch circuit for latching an output signal of the synchronization pattern detection circuit and generating a signal for determining a phase of serial data subsequent to the output signal. .