JPH0945770A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0945770A JPH0945770A JP7194647A JP19464795A JPH0945770A JP H0945770 A JPH0945770 A JP H0945770A JP 7194647 A JP7194647 A JP 7194647A JP 19464795 A JP19464795 A JP 19464795A JP H0945770 A JPH0945770 A JP H0945770A
- Authority
- JP
- Japan
- Prior art keywords
- film
- titanium nitride
- semiconductor device
- tungsten
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 81
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 36
- 239000010937 tungsten Substances 0.000 claims abstract description 36
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 52
- 239000011229 interlayer Substances 0.000 claims description 18
- 239000003870 refractory metal Substances 0.000 claims description 14
- 150000003658 tungsten compounds Chemical class 0.000 claims description 12
- 150000002736 metal compounds Chemical class 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010410 layer Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims 2
- 238000002844 melting Methods 0.000 claims 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 21
- 229910052719 titanium Inorganic materials 0.000 abstract description 21
- 239000010936 titanium Substances 0.000 abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 16
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 abstract description 7
- 239000010408 film Substances 0.000 description 155
- 239000000758 substrate Substances 0.000 description 14
- 239000007789 gas Substances 0.000 description 13
- 238000004544 sputter deposition Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000000460 chlorine Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 7
- 229910052801 chlorine Inorganic materials 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XJDNKRIXUMDJCW-UHFFFAOYSA-J titanium tetrachloride Chemical compound Cl[Ti](Cl)(Cl)Cl XJDNKRIXUMDJCW-UHFFFAOYSA-J 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置及びその
製造方法に関し、特に層間絶縁膜に設けた接続用開口部
を高融点金属あるいは高融点金属化合物で埋め込んだ半
導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a connection opening provided in an interlayer insulating film is filled with a refractory metal or a refractory metal compound and a manufacturing method thereof.
【0002】[0002]
【従来の技術】半導体装置の高集積化は、デザインルー
ルの微細化や配線の多層化等により進められてきた。デ
ザインルールの微細化に伴い、素子あるいは配線間を接
続するための開口部の径も小さくなるが、それに比較し
て、層間絶縁膜の膜厚はほとんど変化しないため、開口
部の深さを径で割ったアスペクト比は増大する一方であ
り、アスペクト比は5を越えようとしている。2. Description of the Related Art High integration of semiconductor devices has been promoted by miniaturization of design rules and multilayer wiring. With the miniaturization of design rules, the diameter of the opening for connecting elements or wirings also becomes smaller.However, since the thickness of the interlayer insulating film hardly changes, the diameter of the opening can be reduced. The aspect ratio divided by is increasing, and the aspect ratio is about to exceed 5.
【0003】このような高アスペクト比の開口部に対し
て従来から広く使用されてきたスパッタ法により必要な
膜厚の窒化チタニウムを形成することは困難である。窒
化チタニウムは、配線材料となるAl合金とSi基板と
の反応を防いだり、化学気相成長法によりWを成長する
際に原料ガスである六弗化タングステン(WF6)とシ
リコン基板との反応を防ぐ等のバリアメタルとしての役
割があり、これらの役割を果たすためには開口部の底に
10nm以上の窒化チタニウムを形成する必要がある。It is difficult to form titanium nitride having a required film thickness in such an opening having a high aspect ratio by a sputtering method which has been widely used conventionally. Titanium nitride prevents a reaction between an Al alloy, which is a wiring material, and a Si substrate, and a reaction between tungsten hexafluoride (WF 6 ) which is a raw material gas and a silicon substrate when W is grown by a chemical vapor deposition method. There is a role as a barrier metal for preventing the above, and in order to fulfill these roles, it is necessary to form titanium nitride having a thickness of 10 nm or more at the bottom of the opening.
【0004】アスペクト比5を越えるような開口部に窒
化チタニウムをスパッタ法に10nm以上形成するのは
困難であるため、被覆性に優れた化学気相成長法(CV
D法)が使用されつつある。開口部の径が0.3μm以
下と微細な場合には、窒化チタニウム上にタングステン
を成長させて開口部を埋め込む従来の方法では工程数が
多く、コスト高となるため、窒化チタニウムを埋め込む
方法によりコスト低減を図る方法が提案されている(例
えば1993年秋季 第54回 応用物理学会学術講演
会 予稿集 p−707の28p−ZE−2)。上述し
た窒化チタニウムで開口部を埋め込む方法は、一般的に
窒化チタニウムの応力が大きく成長速度が小さいため、
厚く成長させることは困難であり、これまで実用化され
ていない。しかしながら、開口部の径が0.3μm以下
と微細となってくると、0.15μm程度の薄い膜厚で
も埋め込むことが可能となり、実用化が可能となってく
る。Since it is difficult to form titanium nitride having a thickness of 10 nm or more in an opening having an aspect ratio of more than 5 by a sputtering method, a chemical vapor deposition method (CV) having an excellent covering property is used.
Method D) is being used. When the diameter of the opening is as small as 0.3 μm or less, the conventional method of growing tungsten on titanium nitride to fill the opening requires a large number of steps, resulting in high cost. A method for reducing costs has been proposed (for example, Autumn 1993 54th Annual Meeting of the Society of Applied Physics, Proceedings, p-707, 28p-ZE-2). In the method of filling the opening with titanium nitride described above, since the stress of titanium nitride is generally large and the growth rate is small,
It is difficult to grow thick and it has not been practically used so far. However, when the diameter of the opening becomes as small as 0.3 μm or less, it becomes possible to embed even a thin film thickness of about 0.15 μm, and it becomes possible to put it into practical use.
【0005】また従来において窒化チタニウムを形成し
た後にWで開口部を埋め込む方法としては、窒化チタニ
ウムを全面成長後、その上に全面にWを成長させ、Wを
全面にエッチバックして開口部の中にのみWを残す方法
が一般的であるが、この方法では工程数が多くコスト高
であることや、窒化チタニウムの被覆性が悪いこと、W
成長の際のバリア性が不十分となりジャンクションリー
クが発生することがあるため、次のような方法が提案さ
れている。その方法について図面を用いて説明する。As a conventional method of filling the opening with W after forming titanium nitride, titanium nitride is grown on the entire surface, W is grown on the entire surface, and W is etched back on the entire surface to open the opening. A method of leaving W only in the inside is general, but this method involves a large number of steps and is costly, and the covering property of titanium nitride is poor.
Since the barrier property during growth may be insufficient and a junction leak may occur, the following method has been proposed. The method will be described with reference to the drawings.
【0006】図4(a)に示すように、まずシリコン基
板21上にシリコン酸化膜22からなる層間絶縁膜を形
成し、シリコン基板21に達する開口部を形成し、次に
開口部の肩部で成長速度とエッチング速度が同じくなる
条件で化学気相成長法により窒化チタニウム23を形成
する。As shown in FIG. 4A, an interlayer insulating film made of a silicon oxide film 22 is first formed on a silicon substrate 21, an opening reaching the silicon substrate 21 is formed, and then a shoulder of the opening is formed. Then, the titanium nitride 23 is formed by the chemical vapor deposition method under the condition that the growth rate and the etching rate are the same.
【0007】その後、図4(b)に示すように窒化チタ
ニウム23を全面エッチバックした後、図4(c)に示
すように開口部の周囲にのみフォトレジスト膜24を形
成し、図4(d)に示すように層間絶縁膜上の窒化チタ
ニウム23をエッチング除去して開口部にのみ窒化チタ
ニウム23を残す。After that, as shown in FIG. 4 (b), the titanium nitride 23 is entirely etched back, and then a photoresist film 24 is formed only around the opening as shown in FIG. 4 (c). As shown in d), the titanium nitride 23 on the interlayer insulating film is removed by etching to leave the titanium nitride 23 only in the opening.
【0008】その後、図4(e)に示すように窒化チタ
ニウム上にWF6をシラン(SiH4)により還元して、
選択的にW25を成長させて開口部をW25で埋め込
み、さらに図4(f)に示すようにAl合金26でAl
配線を形成する(例えば特開平4−7825号公報参
照)。After that, as shown in FIG. 4 (e), WF 6 was reduced on the titanium nitride by silane (SiH 4 ),
W25 is selectively grown to fill the opening with W25, and as shown in FIG.
Wiring is formed (see, for example, JP-A-4-7825).
【0009】[0009]
【発明が解決しようとする課題】図4に示した従来の半
導体装置の製造方法では、開口部の底のみに窒化チタニ
ウムを残す工程が複雑であり、コスト高になってしまう
という問題点がある。さらに開口部の埋め込みは主にW
で行っており、Wを厚く成長しなければならず、Wを層
間絶縁膜上には全く成長させずに、窒化チタニウム上に
のみ厚く形成するのは非常に困難であるため、層間絶縁
膜上にも粒状にWが成長してしまう。たとえば1.0μ
mの厚さにWを形成する場合には0.5μm径程度のW
粒が層間絶縁膜上に形成されてしまう。その上にAl合
金膜を成膜して配線を形成する際、Al合金のエッチン
グでWはエッチングされず残ってしまうため、図4
(f)に示すように配線間を短絡してしまうという問題
もある。In the conventional method for manufacturing a semiconductor device shown in FIG. 4, there is a problem that the step of leaving titanium nitride only at the bottom of the opening is complicated and the cost becomes high. . Furthermore, the opening is mainly filled with W
Since it is very difficult to form W thickly only on titanium nitride without growing W on the interlayer insulating film at all, it is very difficult to grow W on the interlayer insulating film. Also, W grows granularly. For example 1.0μ
When forming W with a thickness of m, W with a diameter of about 0.5 μm
Grains are formed on the interlayer insulating film. When an Al alloy film is formed thereon to form a wiring, W is not etched and remains by etching the Al alloy.
There is also a problem that the wirings are short-circuited as shown in (f).
【0010】また径が0.3μm以下のように微細であ
る開口部を窒化チタニウムで埋め込む場合は、その上に
Al合金等で配線を形成する際、開口部と配線の位置合
わせの余裕がほとんどなく、配線から開口部がはみ出し
てしまうような場合、配線がAlあるいはAl合金又は
CrあるいはCu合金の場合、塩素系のガスでエッチン
グするため、窒化チタニウムがエッチングされてしま
い、配線からはみ出した開口部の窒化チタニウムがエッ
チングされて窪みが形成されてしまう(図5(a))。When a fine opening having a diameter of 0.3 μm or less is filled with titanium nitride, there is almost no margin for alignment between the opening and the wiring when the wiring is formed thereon with an Al alloy or the like. In the case where the opening protrudes from the wiring, if the wiring is made of Al, Al alloy, Cr, or Cu alloy, titanium nitride is etched because the etching is performed with a chlorine-based gas, and the opening that protrudes from the wiring is formed. Part of the titanium nitride is etched to form a depression (FIG. 5A).
【0011】窪みが形成されてしまうと、その上に形成
するシリコン酸化膜32等の層間絶縁膜の被覆性が悪く
なり、配線の信頼性を低下させると共に層間絶縁膜の平
坦化が困難となってくるという問題点がある(図5
(b))。When the depression is formed, the coverage of the interlayer insulating film such as the silicon oxide film 32 formed on the depression is deteriorated, the reliability of the wiring is lowered, and it is difficult to flatten the interlayer insulating film. There is a problem that it comes (Fig. 5
(B)).
【0012】本発明の目的は、上層配線を塩素系ガスで
エッチングする際に窒化チタニウムがエッチングされる
のを防止するようにした構造をもつ半導体装置及びその
製造方法を提供することにある。An object of the present invention is to provide a semiconductor device having a structure for preventing titanium nitride from being etched when the upper wiring is etched with chlorine gas and a method for manufacturing the same.
【0013】[0013]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置は、素子あるいは配線間を
接続するために層間絶縁膜に設けた貫通口を高融点金属
や高融点金属化合物で埋め込んだ半導体装置であって、
前記貫通口のほとんどは窒化チタニウム膜で埋め込ま
れ、前記窒化チタニウム膜上は薄いタングステン膜ある
いはタングステン化合物膜で覆われたものである。In order to achieve the above object, a semiconductor device according to the present invention has a through-hole provided in an interlayer insulating film for connecting elements or wirings with a refractory metal or refractory metal compound. It is a semiconductor device embedded with
Most of the through holes are filled with a titanium nitride film, and the titanium nitride film is covered with a thin tungsten film or a tungsten compound film.
【0014】また前記高融点金属や高融点金属化合物で
埋め込まれた貫通口上の配線は、主にアルミニウム,ア
ルミニウム合金,銅,銅合金の中から選ばれたものであ
る。The wiring on the through hole filled with the refractory metal or the refractory metal compound is mainly selected from aluminum, aluminum alloy, copper and copper alloy.
【0015】また前記タングステン膜あるいはタングス
テン化合物膜の膜厚は、20〜200nmである。The thickness of the tungsten film or the tungsten compound film is 20 to 200 nm.
【0016】また本発明に係る半導体装置の製造方法
は、埋込工程と、エッチング工程と、成膜工程とを有
し、素子あるいは配線間を接続するために層間絶縁膜に
設けた貫通口を高融点金属や高融点金属化合物で埋め込
む半導体装置の製造方法であって、前記埋込工程は、窒
化チタニウム膜の全面成長により前記貫通口を埋め込む
処理であり、エッチング工程は、前記層間絶縁膜上の前
記窒化チタニウム膜を除去して前記貫通口内にのみ前記
窒化チタニウム膜を残す処理であり、成膜工程は、前記
窒化チタニウム膜上のみに薄いタングステン膜あるいは
タングステン化合物膜を形成する処理である。The method of manufacturing a semiconductor device according to the present invention includes an embedding step, an etching step, and a film forming step, and a through hole provided in an interlayer insulating film for connecting elements or wirings is formed. A method of manufacturing a semiconductor device to be embedded with a refractory metal or a refractory metal compound, wherein the embedding step is a step of filling the through-holes by overall growth of a titanium nitride film, and the etching step is a step of forming an etching on the interlayer insulating film. Is a process of removing the titanium nitride film to leave the titanium nitride film only in the through hole, and the film forming process is a process of forming a thin tungsten film or a tungsten compound film only on the titanium nitride film.
【0017】また前記窒化チタニウム膜の除去方法は、
全面エッチバック法である。The method of removing the titanium nitride film is as follows:
It is a full-etch back method.
【0018】また前記窒化チタニウム膜の除去方法は、
研磨法である。The method of removing the titanium nitride film is as follows.
It is a polishing method.
【0019】また前記窒化チタニウム膜の成長方法は、
化学気相成長法である。The method of growing the titanium nitride film is as follows.
It is a chemical vapor deposition method.
【0020】また前記貫通口の径は300nm以下であ
り、前記窒化チタニウム膜の成長膜厚は300nm以上
である。The diameter of the through hole is 300 nm or less, and the grown film thickness of the titanium nitride film is 300 nm or more.
【0021】また前記タングステン膜を化学気相成長法
により前記窒化チタニウム膜上のみに選択的に形成する
ものである。Further, the tungsten film is selectively formed only on the titanium nitride film by a chemical vapor deposition method.
【0022】また前記窒化チタニウム膜の比抵抗は30
μΩcm以下である。The specific resistance of the titanium nitride film is 30.
It is μΩcm or less.
【0023】また前記タングステン膜あるいはタングス
テン化合物膜を形成する工程の後、全面にアルミニウ
ム,アルミニウム合金,銅,銅合金のいずれかを主とす
る金属層を形成する工程と、前記金属層を塩素を含むガ
スにてエッチングしてパターニングする工程を含むもの
である。After the step of forming the tungsten film or the tungsten compound film, a step of forming a metal layer mainly containing aluminum, an aluminum alloy, copper, or a copper alloy on the entire surface, and the step of forming the metal layer with chlorine. It includes a step of patterning by etching with a gas containing the same.
【0024】また前記タングステン膜あるいはタングス
テン化合物の形成膜厚は20〜200nmである。The film thickness of the tungsten film or the tungsten compound is 20 to 200 nm.
【0025】以上のように本発明によれば、層間絶縁膜
に設けた貫通口内に窒化チタニウムを埋め込み、その窒
化チタニウムの表層を薄いタングステンあるいはタング
ステン化合物とすることにより、上層配線を塩素系ガス
にてエッチングする際に前記貫通口内の窒化チタニウム
がエッチングされないようにしている。As described above, according to the present invention, titanium nitride is buried in the through hole provided in the interlayer insulating film, and the surface layer of the titanium nitride is made of thin tungsten or a tungsten compound, so that the upper layer wiring is changed to chlorine gas. The titanium nitride in the through hole is prevented from being etched during the etching.
【0026】[0026]
【発明の実施の形態】次に本発明について図面を用いて
説明する。Next, the present invention will be described with reference to the drawings.
【0027】(実施形態1)図1は本発明の実施形態1
を製造工程順に示す断面図である。図1(a)に示すよ
うに、まず素子が形成されたシリコン基板1上にシリコ
ン酸化膜2を1.5μmの厚さに形成する。シリコン酸
化膜2にはボロンやリンを添加しても良い。シリコン酸
化膜2の所望の位置に通常のリソグラフィ技術及びドラ
イエッチング技術により直径0.3μmの貫通口2aを
シリコン基板1に達する深さに形成する。貫通口2aは
深さ1.5μmに対して直径が0.3μmであるため、
そのアスペクト比は5である。(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 6 is a cross-sectional view showing the step of manufacturing. As shown in FIG. 1A, first, a silicon oxide film 2 having a thickness of 1.5 μm is formed on a silicon substrate 1 on which elements are formed. Boron or phosphorus may be added to the silicon oxide film 2. A through hole 2a having a diameter of 0.3 μm is formed at a desired position of the silicon oxide film 2 by a usual lithography technique and a dry etching technique to a depth reaching the silicon substrate 1. Since the diameter of the through hole 2a is 0.3 μm for a depth of 1.5 μm,
Its aspect ratio is 5.
【0028】その後、シリコン酸化膜2の全面にコリメ
ートスパッタ法によりチタニウム膜3を100nm,窒
化チタニウム膜4を埋め込みに必要な膜厚(ここでは1
50〜300nmの厚さ)に順次形成する。窒化チタニ
ウム膜4は応力が大きく300nmより厚く形成すると
剥がれたり、クラックが発生したりするが、300nm
以上の膜厚で埋め込めるコンタクトに適用するのが望ま
しい。After that, a titanium film 3 having a thickness of 100 nm and a titanium nitride film 4 having a film thickness (here, 1) are formed by collimating sputtering on the entire surface of the silicon oxide film 2.
(Thickness of 50 to 300 nm). The titanium nitride film 4 has a large stress and is peeled off or cracks are formed when it is formed thicker than 300 nm.
It is desirable to apply it to a contact that can be embedded with the above film thickness.
【0029】コリメートスパッタ法とは、ターゲットと
基板の間に多数の孔を設けたコリメート板と呼ばれるも
のを設置し、基板に対して垂直に近い方向に入射するス
パッタ粒子のみを選択して基板に到達するようにし、開
口部の底部での被覆性を向上させたスパッタ法であり、
ここではコリメート板の厚み:コリメート板の開口部の
直径が2:1のものを用いており、貫通口2aの底部に
およそ10nmのチタニウム膜3が形成される。In the collimated sputtering method, a so-called collimated plate in which a large number of holes are provided between a target and a substrate is installed, and only sputtered particles that are incident in a direction almost perpendicular to the substrate are selected and the substrate is selected. Is a sputtering method with improved coverage at the bottom of the opening,
Here, the thickness of the collimator plate: the diameter of the opening of the collimator plate is 2: 1 and the titanium film 3 of about 10 nm is formed on the bottom of the through hole 2a.
【0030】窒化チタニウム膜4は、テトラキシデメチ
ルアミノチタニウム(TDMAT)の熱分解により形成
する。アンモニア(NH3)を加えて窒化させる方法も
あるが、段差被覆性が悪化するので、微細な開口部を埋
め込むのには適さない。成長時の圧力は0.3〜1.0
Torrとし、基板温度は350〜450℃とする。こ
の程度の温度範囲では表面律速反応で成長するため、段
差被覆に優れ微細な貫通孔2aへの埋め込みに適してい
る。The titanium nitride film 4 is formed by thermal decomposition of tetraxidemethylaminotitanium (TDMAT). There is also a method of nitriding by adding ammonia (NH 3 ), but this is not suitable for filling a fine opening because the step coverage deteriorates. Pressure during growth is 0.3-1.0
The substrate temperature is 350 to 450 ° C. In this temperature range, the growth is performed by the surface rate-determining reaction, so that it is excellent in step coverage and is suitable for embedding in the fine through holes 2a.
【0031】次に図1(b)に示すように、3塩化ホウ
素(BCl3)ガスを用いた反応性イオンエッチング法
により窒化チタニウム膜4及びチタニウム膜3を全面エ
ッチングし、シリコン酸化膜2上から除去し、これらを
貫通口2a内のみに残す。その際、オーバエッチングを
行い、貫通口2aの上部開口縁から10〜20nm程度
下方に凹んだ位置に窒化チタニウム膜4及びチタニウム
膜3が存在するようにしている。Next, as shown in FIG. 1B, the titanium nitride film 4 and the titanium film 3 are entirely etched by a reactive ion etching method using a boron trichloride (BCl 3 ) gas, and the silicon oxide film 2 is covered. And leave them only in the through hole 2a. At that time, over-etching is performed so that the titanium nitride film 4 and the titanium film 3 are present at positions recessed downward by about 10 to 20 nm from the upper opening edge of the through hole 2a.
【0032】次に図1(c)に示すようにスパッタリン
グ法を用い、タングステン中に重量で10%程度チタニ
ウムを加えたチタニウムタングステン(TiW)膜5を
200〜500nmの厚さに形成する。スパッタリング
法では、段差被覆性は良くないが、貫通口2a内におけ
る窒化チタニウム膜4及びチタニウム膜3の凹み程度が
極く小さいため、スパッタリング法により貫通口2a内
の凹み部分をチタニウムタングステン膜5で完全に埋め
込むことが可能である。Next, as shown in FIG. 1C, a titanium tungsten (TiW) film 5 in which about 10% by weight of titanium is added to tungsten is formed to a thickness of 200 to 500 nm by using a sputtering method. In the sputtering method, the step coverage is not good, but since the depression degree of the titanium nitride film 4 and the titanium film 3 in the through hole 2a is extremely small, the titanium tungsten film 5 is used in the depression portion in the through hole 2a by the sputtering method. It can be completely embedded.
【0033】次に図1(d)に示すようにCF4ガスを
用いた反応性イオンエッチング法によりチタニウムタン
グステン膜を全面エッチングしてシリコン酸化膜2上か
ら除去し、これを貫通口2a内の凹み部分にのみ残し、
ほぼ平坦面にする。Next, as shown in FIG. 1D, the titanium-tungsten film is entirely etched by reactive ion etching using CF 4 gas to remove it from the silicon oxide film 2, and this is removed from the inside of the through hole 2a. Leave only in the recessed part,
Make it almost flat.
【0034】ここでチタニウムタングステン膜を全面成
長させてエッチバックにより貫通口2aの凹み部分を埋
め込む方法に代えて、図2に示すようにタングステン膜
9を減圧化学気相成長法によりチタニウム膜3と窒化チ
タニウム膜4上にのみ選択的に10〜20nm成長させ
るようにしても良い。この場合タングステン膜9は、六
弗化タングステン(WF6)ガスをSiH4にて還元して
成長させる。その成長温度は200〜270℃とし、S
iH4の流量はWF6の50〜100%とし、トータル圧
力は10〜100mTorrとする。Here, instead of the method of growing the titanium tungsten film over the entire surface and filling the recessed portion of the through hole 2a by etching back, the tungsten film 9 is replaced with the titanium film 3 by the low pressure chemical vapor deposition method as shown in FIG. You may make it selectively grow 10-20 nm only on the titanium nitride film 4. In this case, the tungsten film 9 is grown by reducing tungsten hexafluoride (WF 6 ) gas with SiH 4 . The growth temperature is 200 to 270 ° C., and S
The flow rate of iH 4 is 50 to 100% of WF 6 , and the total pressure is 10 to 100 mTorr.
【0035】タングステン膜9の膜厚は10〜20nm
と薄いため、シリコン酸化膜2上にはほとんどタングス
テン膜9は成長しない。タングステン膜9を窒化チタニ
ウム膜4上に選択成長する場合、ガスを流してからタン
グステン膜9が成長を開始するまでの時間が窒化チタニ
ウム膜4の比抵抗により変化し、比抵抗が高いと、タン
グステン膜9は成長しにくく、シリコン酸化膜2上と選
択性を保つのは困難なため、窒化チタニウム膜4の比抵
抗は300μΩcm以下にすることが望ましい。窒化チ
タニウム膜4の比抵抗を300μΩcm以下にすれば、
タングステン膜9を10〜20nm成長させても全くシ
リコン酸化膜2上にはタングステン膜9は成長しない。The film thickness of the tungsten film 9 is 10 to 20 nm.
Since it is thin, the tungsten film 9 hardly grows on the silicon oxide film 2. When the tungsten film 9 is selectively grown on the titanium nitride film 4, the time from the gas flow to the start of growth of the tungsten film 9 changes depending on the specific resistance of the titanium nitride film 4. Since the film 9 is difficult to grow and it is difficult to maintain the selectivity with respect to the silicon oxide film 2, it is desirable that the specific resistance of the titanium nitride film 4 be 300 μΩcm or less. If the specific resistance of the titanium nitride film 4 is 300 μΩcm or less,
Even if the tungsten film 9 is grown to a thickness of 10 to 20 nm, the tungsten film 9 does not grow on the silicon oxide film 2 at all.
【0036】次に図1(e)に示すように第2の窒化チ
タニウム膜6を50〜100nm,Al合金膜7を0.
3〜1.0μmの厚さにスパッタリング法により順次形
成した後、フォトレジスト膜8を塗布してAl配線とな
る所望のパターンを露光,現像により形成する。その
際、貫通口2aとAl配線の位置合わせの余裕が小さい
と、貫通口2aがフォトレジスト膜8からはみ出してし
まう。Next, as shown in FIG. 1 (e), the second titanium nitride film 6 has a thickness of 50 to 100 nm and the Al alloy film 7 has a thickness of 0.
After sequentially forming a film having a thickness of 3 to 1.0 μm by a sputtering method, a photoresist film 8 is applied and a desired pattern to be an Al wiring is formed by exposure and development. At this time, if there is a small margin for the alignment of the through hole 2a and the Al wiring, the through hole 2a will protrude from the photoresist film 8.
【0037】次に図1(f)に示すように塩素を含むガ
ス、例えばCl2,BCl3,CCl4,SiCl4等のガ
スを用い反応性イオンエッチング法により、Al合金膜
7,窒化チタニウム膜6をエッチングした後、フォトレ
ジスト膜8を除去する。その際、貫通口2aの表面が露
出してしまうが、その表面はチタニウムタングステン膜
9が存在するため、塩素系のガスではほとんどエッチン
グされず、貫通口2a内に凹みが形成されることなく、
Al配線を形成することができる。Next, as shown in FIG. 1F, an Al alloy film 7 and a titanium nitride film are formed by a reactive ion etching method using a gas containing chlorine, for example, a gas such as Cl 2 , BCl 3 , CCl 4 , or SiCl 4. After etching the film 6, the photoresist film 8 is removed. At that time, the surface of the through hole 2a is exposed, but since the titanium tungsten film 9 is present on the surface, it is hardly etched by a chlorine-based gas, and a recess is not formed in the through hole 2a.
Al wiring can be formed.
【0038】(実施形態2)図3は本発明の実施形態2
を製造工程順に示す断面図である。図3(a)に示すよ
うに、まずシリコン酸化膜12で表面が覆われたシリコ
ン基板11上に多結晶シリコン13により第1の配線を
形成する。次に第2のシリコン酸化膜14を形成した
後、通常のリソグラフィ技術とドライエッチング技術を
用いて、シリコン基板11と多結晶シリコン13に達す
る貫通口14aと14bを形成し、その後チタニウム膜
15及び窒化チタニウム膜16を化学気相成長法により
順次形成する。(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
FIG. 6 is a cross-sectional view showing the step of manufacturing. As shown in FIG. 3A, first, a first wiring is formed of polycrystalline silicon 13 on a silicon substrate 11 whose surface is covered with a silicon oxide film 12. Next, after forming the second silicon oxide film 14, the through holes 14a and 14b reaching the silicon substrate 11 and the polycrystalline silicon 13 are formed by using the ordinary lithography technique and dry etching technique, and then the titanium film 15 and the titanium film 15 are formed. The titanium nitride film 16 is sequentially formed by the chemical vapor deposition method.
【0039】チタニウム膜15は、四塩化チタニウム
(TiCl4)に水素を加えてプラズマCVD法にて形
成する。窒化チタニウム膜16は、TiCl4をアンモ
ニア(NH3)により窒化させ、プラズマを用いない通
常の減圧CVD法で形成する。The titanium film 15 is formed by plasma CVD by adding hydrogen to titanium tetrachloride (TiCl 4 ). The titanium nitride film 16 is formed by nitriding TiCl 4 with ammonia (NH 3 ) and using a normal low pressure CVD method without using plasma.
【0040】チタニウム膜15は、段差被覆性が良いた
め、5〜20nmの厚さで良い。また、窒化チタニウム
膜16は、実施形態1と同様に貫通口14a,14bを
埋め込める以上の膜厚とするが、厚過ぎると膜剥がれや
クラックが発生するため、300nm以下としたほうが
良い。また本方法では、膜中に炭素が含まれないため、
実施形態1に比べて窒化チタニウム膜16の比抵抗を1
00〜150μΩcmと小さくすることが可能であり、
その上に選択的にタングステン膜を成長させるのに有利
である。Since the titanium film 15 has good step coverage, it may have a thickness of 5 to 20 nm. Further, the titanium nitride film 16 has a thickness larger than that in which the through holes 14a and 14b can be embedded as in the first embodiment. However, if it is too thick, film peeling or cracks occur, so it is preferable to set the thickness to 300 nm or less. Further, in this method, since the film does not contain carbon,
Compared with the first embodiment, the specific resistance of the titanium nitride film 16 is 1
It is possible to make it as small as 00 to 150 μΩcm,
It is advantageous to selectively grow a tungsten film on it.
【0041】次に図3(b)に示すように化学的機械的
研磨法にて窒化チタニウム膜16とチタニウム膜15を
研磨して、シリコン酸化膜14上から除去する。これに
より表面はほぼ平坦となる。Next, as shown in FIG. 3B, the titanium nitride film 16 and the titanium film 15 are polished by the chemical mechanical polishing method and removed from the silicon oxide film 14. This makes the surface almost flat.
【0042】次に図3(c)に示すように減圧CVD法
によりタングステン膜17を20〜200nmの厚さに
チタニウム膜15と窒化チタニウム膜16の表面に選択
的に形成する。タングステン膜17は実施形態1と同様
にWF6をSiH4により還元して形成してもよいが、W
F6を水素により還元して形成してもよい。水素により
還元する方法は、SiH4により還元する方法に比べて
成長速度は小さいが、成長膜厚が小さいため問題とはな
らない。Next, as shown in FIG. 3C, a tungsten film 17 having a thickness of 20 to 200 nm is selectively formed on the surfaces of the titanium film 15 and the titanium nitride film 16 by a low pressure CVD method. The tungsten film 17 may be formed by reducing WF 6 with SiH 4 as in the first embodiment.
It may be formed by reducing F 6 with hydrogen. The method of reducing with hydrogen has a smaller growth rate than the method of reducing with SiH 4 , but there is no problem because the grown film thickness is small.
【0043】タングステン膜17は表面が平坦なため、
成長膜厚とほぼ同じだけ横にも成長するので、厚くする
と隣接する配線等と短絡する可能性があり、あまり厚く
形成することはできず、200nm以下、望ましくは1
00nm以下とするのが望ましい。またタングステン膜
17が20nmよりも薄いと、その後Al合金をエッチ
ングする際にエッチングされてしまい、タングステン膜
17の下のチタニウム膜15や窒化チタニウム膜16ま
でもエッチングされてしまうことがあるため、タングス
テン膜17は20nm以上とする。Since the surface of the tungsten film 17 is flat,
Since the film grows laterally as much as the grown film thickness, if it is made thick, it may short-circuit with an adjacent wiring or the like, and it cannot be formed too thick.
It is desirable that the thickness is 00 nm or less. Further, if the tungsten film 17 is thinner than 20 nm, it may be etched when the Al alloy is etched thereafter, and the titanium film 15 and the titanium nitride film 16 under the tungsten film 17 may also be etched. The film 17 has a thickness of 20 nm or more.
【0044】次に図3(d)に示すようにタングステン
膜17を成長後、Al合金膜18をスパッタリング法に
より形成し、その上にフォトレジスト膜19を塗布し、
Al配線となる所望のパターンを露光現像により形成す
る。その際、貫通口14a,14bとAl配線の位置合
わせの余裕が小さいと、貫通口14a,14bがフォト
レジスト膜19からはみ出してしまう。Next, as shown in FIG. 3D, after growing a tungsten film 17, an Al alloy film 18 is formed by a sputtering method, and a photoresist film 19 is applied thereon.
A desired pattern to be an Al wiring is formed by exposure and development. At this time, if the margin for alignment between the through holes 14a and 14b and the Al wiring is small, the through holes 14a and 14b will protrude from the photoresist film 19.
【0045】次に図3(e)に示すように塩素を含むガ
スにて反応性イオンエッチング法によりAl合金膜18
をエッチングした後、フォトレジスト膜19を除去して
Al配線を完成する。その際、貫通口14a,14bの
表面が露出してもタングステン膜17は塩素系ガスによ
りほとんどエッチングされないため、下の窒化チタニウ
ム膜16,チタニウム膜15がエッチングされることは
ない。Next, as shown in FIG. 3E, an Al alloy film 18 is formed by a reactive ion etching method using a gas containing chlorine.
After etching, the photoresist film 19 is removed to complete the Al wiring. At this time, even if the surfaces of the through holes 14a and 14b are exposed, the tungsten film 17 is hardly etched by the chlorine-based gas, so that the titanium nitride film 16 and the titanium film 15 below are not etched.
【0046】本実施形態のように深さの違う貫通口14
aと14bとにも同時に形成可能である。Through holes 14 having different depths as in this embodiment
It is possible to form a and 14b at the same time.
【0047】以上説明した実施形態では、シリコン基板
や多結晶シリコンに接続する貫通口を設けたが、これに
限られるものではなく、下層のAl配線等に接続する貫
通口についても本発明が適用できることはいうまでもな
い。下層配線が高融点金属あるいは、そのシリサイド、
あるいはAl合金膜が高融点金属で覆われている場合、
窒化チタニウム膜の下層にチタニウム膜を特に必要とし
ないため、貫通口の形成後、直接窒化チタニウム膜を成
長させて貫通口を埋め込んでもよい。In the embodiment described above, the through-hole connecting to the silicon substrate or the polycrystalline silicon is provided, but the present invention is not limited to this, and the present invention is also applied to the through-hole connecting to the underlying Al wiring or the like. It goes without saying that you can do it. The lower wiring is a refractory metal or its silicide,
Or when the Al alloy film is covered with a refractory metal,
Since the titanium film is not particularly required as the lower layer of the titanium nitride film, the titanium nitride film may be directly grown after the formation of the through hole to fill the through hole.
【0048】また上層の配線はAl合金を用いたが、こ
れに限られるものではなく、銅や銅合金も塩素ガスを用
いて紫外線を照射しながらプラズマエッチによりエッチ
ングを行うことが可能である。Although the upper layer wiring is made of Al alloy, it is not limited to this, and copper or copper alloy can be etched by plasma etching while irradiating ultraviolet rays using chlorine gas.
【0049】[0049]
【発明の効果】以上説明したように本発明は、層間絶縁
膜に設けた貫通口のほとんどを窒化チタニウム膜で埋め
込み、その窒化チタニウム膜上を薄いタングステン膜あ
るいは、タングステン化合物膜で覆うことにより、その
上に配線金属となるAl合金や銅を形成し、塩素を含む
ガスにてエッチングする際、位置合わせの余裕がなく配
線から貫通口がはみ出しても、貫通口内の窒化チタニウ
ム膜が全くエッチングされることがなく、その上に層間
絶縁膜を被覆性良く形成することができ、微細な貫通口
を有する微細多層配線を信頼性を悪化させることなく容
易に形成できる。As described above, according to the present invention, most of the through holes provided in the interlayer insulating film are filled with a titanium nitride film, and the titanium nitride film is covered with a thin tungsten film or a tungsten compound film. When forming an Al alloy or copper as a wiring metal on it and etching with a gas containing chlorine, the titanium nitride film in the through hole is completely etched even if the through hole protrudes from the wiring because there is no alignment margin. It is possible to form the interlayer insulating film on the insulating film with good coverage, and it is possible to easily form the fine multilayer wiring having the fine through holes without deteriorating the reliability.
【0050】窒化チタニウム膜上のタングステン膜を選
択的にCVD法で形成する場合も、その膜厚は薄くても
よいため、選択性が悪化してタングステン膜による配線
間の短絡等は全くなく、歩留り良く配線を形成できる。Even when the tungsten film on the titanium nitride film is selectively formed by the CVD method, the film thickness may be thin, so that the selectivity is deteriorated and there is no short circuit between wirings due to the tungsten film. Wiring can be formed with good yield.
【図1】本発明の実施形態1を製造工程順に示す断面図
である。FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in the order of manufacturing steps.
【図2】本発明の実施形態1における途中の工程の別の
例を示す図である。FIG. 2 is a diagram showing another example of a process on the way in the first embodiment of the present invention.
【図3】本発明の実施形態2を製造工程順に示す断面図
である。FIG. 3 is a cross-sectional view showing a second embodiment of the present invention in the order of manufacturing steps.
【図4】従来例を製造工程順に示す断面図である。FIG. 4 is a cross-sectional view showing a conventional example in the order of manufacturing steps.
【図5】従来技術の問題点を示す断面図である。FIG. 5 is a cross-sectional view showing a problem of the conventional technique.
1,11,21 シリコン基板 2,12,14,22,32 シリコン酸化膜 3,15 チタニウム膜 4,6,16,23 窒化チタニウム 5 チタニウムタングステン(TiW)膜 9,17,25 タングステン(W)膜 7,18,26,31 Al合金 8,19,24 フォトレジスト膜 13 多結晶シリコン 1,11,21 Silicon substrate 2,12,14,22,32 Silicon oxide film 3,15 Titanium film 4,6,16,23 Titanium nitride 5 Titanium tungsten (TiW) film 9,17,25 Tungsten (W) film 7, 18, 26, 31 Al alloy 8, 19, 24 Photoresist film 13 Polycrystalline silicon
Claims (12)
間絶縁膜に設けた貫通口を高融点金属や高融点金属化合
物で埋め込んだ半導体装置であって、 前記貫通口のほとんどは窒化チタニウム膜で埋め込ま
れ、前記窒化チタニウム膜上は薄いタングステン膜ある
いはタングステン化合物膜で覆われたものであることを
特徴とする半導体装置。1. A semiconductor device in which a through hole provided in an interlayer insulating film for connecting elements or wirings is filled with a high melting point metal or a high melting point metal compound, and most of the through hole is a titanium nitride film. A semiconductor device in which the titanium nitride film is buried and covered with a thin tungsten film or a tungsten compound film.
め込まれた貫通口上の配線は、主にアルミニウム,アル
ミニウム合金,銅,銅合金の中から選ばれたものである
ことを特徴とする請求項1に記載の半導体装置。2. The wiring on the through hole filled with the refractory metal or the refractory metal compound is mainly selected from aluminum, aluminum alloy, copper and copper alloy. Item 2. The semiconductor device according to item 1.
ン化合物膜の膜厚は、20〜200nmであることを特
徴とする請求項2に記載の半導体装置。3. The semiconductor device according to claim 2, wherein the film thickness of the tungsten film or the tungsten compound film is 20 to 200 nm.
程とを有し、素子あるいは配線間を接続するために層間
絶縁膜に設けた貫通口を高融点金属や高融点金属化合物
で埋め込む半導体装置の製造方法であって、 前記埋込工程は、窒化チタニウム膜の全面成長により前
記貫通口を埋め込む処理であり、 エッチング工程は、前記層間絶縁膜上の前記窒化チタニ
ウム膜を除去して前記貫通口内にのみ前記窒化チタニウ
ム膜を残す処理であり、 成膜工程は、前記窒化チタニウム膜上のみに薄いタング
ステン膜あるいはタングステン化合物膜を形成する処理
であることを特徴とする半導体装置の製造方法。4. An embedding step, an etching step, and a film forming step, wherein a through hole provided in an interlayer insulating film for connecting elements or wirings is filled with a refractory metal or a refractory metal compound. A method of manufacturing a semiconductor device, wherein the burying step is a step of burying the through hole by overall growth of a titanium nitride film, and the etching step removes the titanium nitride film on the interlayer insulating film to remove the titanium nitride film. A method of manufacturing a semiconductor device, which is a process of leaving the titanium nitride film only in the through-hole, and the film forming process is a process of forming a thin tungsten film or a tungsten compound film only on the titanium nitride film.
面エッチバック法であることを特徴とする請求項4に記
載の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein the method of removing the titanium nitride film is a full surface etchback method.
磨法であることを特徴とする請求項4に記載の半導体装
置の製造方法。6. The method of manufacturing a semiconductor device according to claim 4, wherein the method of removing the titanium nitride film is a polishing method.
学気相成長法であることを特徴とする請求項4,5及び
6に記載の半導体装置の製造方法。7. The method for manufacturing a semiconductor device according to claim 4, wherein the growth method of the titanium nitride film is a chemical vapor deposition method.
り、前記窒化チタニウム膜の成長膜厚は300nm以上
であることを特徴とする請求項7に記載の半導体装置の
製造方法。8. The method of manufacturing a semiconductor device according to claim 7, wherein the diameter of the through hole is 300 nm or less, and the grown film thickness of the titanium nitride film is 300 nm or more.
より前記窒化チタニウム膜上のみに選択的に形成するこ
とを特徴とする請求項4,5,6,7または8に記載の
半導体装置の製造方法。9. The manufacturing of a semiconductor device according to claim 4, wherein the tungsten film is selectively formed only on the titanium nitride film by a chemical vapor deposition method. Method.
μΩcm以下であることを特徴とする請求項9に記載の
半導体装置の製造方法。10. The specific resistance of the titanium nitride film is 30.
The method for manufacturing a semiconductor device according to claim 9, wherein the value is μΩcm or less.
テン化合物膜を形成する工程の後、全面にアルミニウ
ム,アルミニウム合金,銅,銅合金のいずれかを主とす
る金属層を形成する工程と、前記金属層を塩素を含むガ
スにてエッチングしてパターニングする工程を含むこと
を特徴とする請求項4,5,6,7,8,9又は10に
記載の半導体装置の製造方法。11. A step of forming a metal layer mainly containing aluminum, an aluminum alloy, copper, or a copper alloy on the entire surface after the step of forming the tungsten film or the tungsten compound film; 11. The method of manufacturing a semiconductor device according to claim 4, 5, 6, 7, 8, 9, or 10, including a step of patterning by etching with a gas containing
テン化合物の形成膜厚は20〜200nmであることを
特徴とする請求項11に記載の半導体装置の製造方法。12. The method of manufacturing a semiconductor device according to claim 11, wherein a film thickness of the tungsten film or the tungsten compound is 20 to 200 nm.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7194647A JPH0945770A (en) | 1995-07-31 | 1995-07-31 | Semiconductor device and its manufacture |
| KR1019960031817A KR100221760B1 (en) | 1995-07-31 | 1996-07-31 | Semiconductor device including protective layer for protecting via hole from etching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7194647A JPH0945770A (en) | 1995-07-31 | 1995-07-31 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0945770A true JPH0945770A (en) | 1997-02-14 |
Family
ID=16327996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7194647A Pending JPH0945770A (en) | 1995-07-31 | 1995-07-31 | Semiconductor device and its manufacture |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH0945770A (en) |
| KR (1) | KR100221760B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028360A (en) * | 1997-06-30 | 2000-02-22 | Hitachi, Ltd. | Semiconductor integrated circuit device in which a conductive film is formed over a trap film which in turn is formed over a titanium film |
| US6576509B1 (en) | 1999-08-18 | 2003-06-10 | Hitachi Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
| KR100464384B1 (en) * | 1997-05-31 | 2005-02-28 | 삼성전자주식회사 | Method for forming VIA hole in semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100558034B1 (en) * | 1999-06-30 | 2006-03-07 | 주식회사 하이닉스반도체 | Semiconductor Device Manufacturing Method to Prevent Plug Damage in Tungsten Bitline Formation |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766202A (en) * | 1993-08-27 | 1995-03-10 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH053254A (en) * | 1991-06-24 | 1993-01-08 | Sony Corp | Method of forming laminated wiring |
-
1995
- 1995-07-31 JP JP7194647A patent/JPH0945770A/en active Pending
-
1996
- 1996-07-31 KR KR1019960031817A patent/KR100221760B1/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766202A (en) * | 1993-08-27 | 1995-03-10 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100464384B1 (en) * | 1997-05-31 | 2005-02-28 | 삼성전자주식회사 | Method for forming VIA hole in semiconductor device |
| US6028360A (en) * | 1997-06-30 | 2000-02-22 | Hitachi, Ltd. | Semiconductor integrated circuit device in which a conductive film is formed over a trap film which in turn is formed over a titanium film |
| US6492730B1 (en) | 1997-06-30 | 2002-12-10 | Hitachi, Ltd. | Method for fabricating semiconductor integrated circuit |
| US6605530B2 (en) | 1997-06-30 | 2003-08-12 | Hitachi, Ltd. | Method for fabricating semiconductor integrated circuit |
| US6853081B2 (en) | 1997-06-30 | 2005-02-08 | Hitachi, Ltd. | Method for fabricating semiconductor integrated circuit |
| US7119443B2 (en) | 1997-06-30 | 2006-10-10 | Hitachi, Ltd. | Semiconductor integrated circuit device having a conductive film which contains metal atoms bondable to a halogen element |
| US6576509B1 (en) | 1999-08-18 | 2003-06-10 | Hitachi Ltd. | Semiconductor integrated circuit device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100221760B1 (en) | 1999-09-15 |
| KR970008418A (en) | 1997-02-24 |
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