JPH0945887A - Solid-state imaging device - Google Patents

Abstract

(57) Abstract: It is an object to secure a gain of a carrier transmission MOSFET by enabling a pixel miniaturization process fabrication in a MOS type solid-state imaging device. In a solid-state imaging device in which a MOS transistor is provided for pixel readout, and a signal potential due to an optical signal charge received at the gate of the MOS transistor is output from the drain of the MOS transistor, a change in the gate potential of the MOS transistor and the output are output. It is characterized in that the ratio to the potential change is negative. Further, the MOS transistor is characterized by being of an enhancement type. Further, in a solid-state imaging device in which a MOS transistor is provided for pixel readout and a signal potential due to the optical signal charge received at the gate of the MOS transistor is output from the drain of the MOS transistor, the gate of the MOS transistor is reset to the output line potential of the pixel. It is characterized by

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification type solid state image pickup device using a MOS transistor.

[0002]

2. Description of the Related Art Conventionally, as a solid-state image pickup device, a light receiving surface composed of a large number of photodiodes for receiving light emitted from an object, a scanning circuit for scanning an image appearing on the light receiving surface to take out as an image signal, and this light receiving surface It is composed of a switch that connects the surface and the scanning circuit. The solid-state image sensor of this photodiode includes a M0S system and a CCD system.
S is an abbreviation for Metal-Oxide-Semiconductor, and both types are MOS type, to be exact, MOS structure FET type and MO type.
There is an S structure CCD type.

FIG. 4 shows an example of a circuit in which the photocarriers stored in this MOS structure FET type photodiode are taken out by a MOS transistor, led out to a scanning circuit and outputted.
Shown in That is, as described above, the solid-state imaging device that accumulates the optical signal charge in the gate of the MOS transistor and reads the signal by the source follower operation is, for example, 1993 IEDM.
P. 583 Eric R. Proposed by Fossum and others. FIG. 4 is an equivalent circuit diagram for showing the operation of such a solid-state imaging device. In the figure, 1 is a unit pixel, 2 is a photodiode, 3 is a source follower MOS transistor operating with a source follower, and 4 is an MO.
A transfer MOS transistor for transferring the optical signal charge from the photodiode 2 to the gate of the S-transistor 3, 5 is a reset MOS transistor for resetting the gate of the MOS transistor 3, and 6 is a scanning / selecting pixel for reading. This is a selection MOS transistor, and the pixel 1 is constituted by the respective elements 2, 3, 4, 5, 6 described above.

In FIG. 4, 7 is a vertical output line, and 8 is a load MOS transistor that serves as a constant current source. The source follower MOS transistor 3 and the load MOS transistor 8 form a source follower. Further, 9 is an offset storage capacitance for storing the pixel offset output voltage, 10 is a pixel storage capacitance for storing the pixel output voltage, 11 is a pixel offset output transfer MOS transistor, and 12 is a pixel output transfer MOS transistor. Transistor,
Reference numerals 13 and 14 are MOS transistors for transferring the voltages stored in the offset storage capacitor 9 and the pixel storage capacitor 10 to the horizontal output lines 15 and 16, respectively, and 17 is a differential amplifier for subtracting the offset amount from the pixel output signal, Reference numeral 18 is an output terminal of the differential amplifier 17. Also, φTX, φ
R, φS, φT1, and φT2 represent control pulses input to the gates of the MOS transistors 4, 5, 6, 11, and 12, respectively, and φH represents a horizontal line output control pulse input to the gates of the MOS transistors 13 and 14. Also, V
DD, VSS and VL represent power supply voltages for forming a source follower.

Although the circuit is simplified in FIG. 4, the reference numerals 7, 8, 9, 1 as the vertical output circuit system are shown.
A plurality of 0, 11, 12, 13, and 14 are actually arranged in parallel, and the pixel 1 connected to each vertical output line has a plurality of pixels connected in parallel on each vertical output line. There are hundreds of thousands arranged in rows and columns.

Next, the operation of the sensor shown in FIG. 4 will be described with reference to FIG. First, the control pulse φS is set to High to select the read pixel 1, and then a High pulse is input to the control pulse φR to reset the gate of the source follower MOS transistor 3 to the power supply VDD. The offset output voltage of the source follower MOS transistor 3 is stored in the offset storage capacitor 9 by turning on the pixel offset output transfer MOS transistor 11 by the High pulse of the control pulse φT1. Next, by the high pulse of the control pulse φTX, the photocharges stored in the photodiode 2 are transferred to the gate of the source follower MOS transistor 3 through the transfer MOS transistor 4. This causes the source follower output to be the offset plus the signal, which is the control pulse φT2.
Is transferred to the pixel storage capacitor 10 through the pixel output transfer MOS transistor 12. After the control pulse φS is set to Low and the reading selection of the pixel 1 is completed, by the High pulse of the control pulse φH,
The offset output and the pixel output obtained by adding a signal to the offset are transferred to the horizontal output lines 15 and 16 through the horizontal line output MOS transistors 13 and 14, respectively, and the signal without the offset amount that has passed through the differential amplifier 17 is output from the terminal 18. Output.

As can be seen from the above operation, the offset output obtained by resetting each pixel and the output of the pixel signal added to the reset gate can be subtracted, so that fixed pattern noise, which is a variation in each pixel output, is also generated. Therefore, it is possible to obtain a signal that does not include random noise that is kTC noise generated at reset.

[0008]

However, in the above conventional example, one pixel is a photodiode and four MOs.
Since it is composed of S-transistor, and VDD power line and ground line pass through in the pixel, the opening area is remarkably reduced or the miniaturization process in the case where the pixel size is small in the application requiring high density pixel. However, there is a drawback that a pixel having an effective area cannot be manufactured even by using. Further, since the gate of the source follower is reset to the level of the power supply VDD, the high level of the reset pulse φR is the power supply V
It must be higher than DD, and requires a pulse with a wide voltage range.

Further, the maximum gain of the source follower is 1
Therefore, from the storage capacitors 9 and 10 to the horizontal output lines 15 and 1,
When the signal is transferred to 6, the signal potential is lowered due to capacitance division, and S / due to the noise of the horizontal output line and the differential amplifier.
There is also a drawback that N tends to decrease.

[0010]

In order to solve the above-mentioned problems, the solid-state image pickup device of the present invention has a pixel which is composed of a photodiode and a MOS transistor, and has a gate to which the photocharge from the photodiode is transferred. The MOS transistor is characterized in that it forms an inverting amplifier together with the MOS transistor connected to the vertical output line. In the above-described configuration, the signal is read by using the difference between the offset output and the output obtained by adding the signal to the offset as the sensor output, as in the conventional example.

Specifically, in a solid-state image pickup device in which a MOS transistor is provided for pixel readout and a signal potential due to an optical signal charge received at the gate of the MOS transistor is output from the drain of the MOS transistor, the gate potential of the MOS transistor It is characterized in that the ratio between the change and the output potential change is negative. When reading out the photocharges of the photodiode or phototransistor, an inverting amplification type MOS transistor circuit can be used to obtain an image signal of high output level and high S / N.

Further, the MOS transistor is characterized by being of an enhancement type. This is because a 1-gate MOS transistor is used instead of a 2-gate MOS transistor.

Further, in a solid-state image pickup device in which a MOS transistor is provided for pixel readout and a signal potential due to an optical signal charge received by the gate of the MOS transistor is output from the drain of the MOS transistor, the gate of the MOS transistor is the output line of the pixel. It is characterized in that it is reset to a potential. An accurate image signal can be obtained by eliminating the residual photocharge of the gate. Further, it is characterized in that a MOS transistor for a constant current source is connected to the drain of the MOS transistor. When the power is supplied to perform amplification, a constant current is applied to the output line.

[0014]

【Example】

(1) First Embodiment FIG. 1 is an equivalent circuit diagram of a peripheral portion including pixels of a solid-state imaging device according to a first embodiment of the present invention. In the figure, 20 is a MOS transistor for receiving a photocharge from the photodiode 2 at its gate and outputting a signal from its drain, and 22 is a MOS transistor for forming an MOS transistor 20 and an inverting amplifier. The drain and gate of 22 are connected to the power supply VDD, and the source is connected to the vertical output line 7. Reference numeral 21 is a MOS transistor that resets the gate of the MOS transistor 20 to the potential of the output line 7. In FIG. 1, parts common to those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 2 is a diagram showing the input / output characteristics of the inverting amplifier composed of the MOS transistor 20 and the MOS transistor 22. The gate potential of the MOS transistor 20 reset through the MOS transistor 21 is the input potential of the inverting amplifier = The potential is determined by the output potential.

The operation of the solid-state image pickup device will be described below. The sensor shown in FIG. 1 is driven at the same pulse timing as shown in FIG. First, the control pulse φS becomes high, the MOS transistor 20 is turned on, and the first gate potential is amplified. Next, the control pulse φR becomes high, the MOS transistor 21 is turned on, and the first gate of the MOS transistor 20 becomes the output line 7.
To conduct. At the same time, the control pulse φT1 goes high and MO
When the S transistor 11 is turned on, the MOS transistor 2
The high potential output from the drain of 0 is MO through the output line 7.
The potential of the first gate of the S transistor 20 is stored in the storage capacitor 9 as amplified offset charge. Next, the control pulse φR goes low, and then the control pulse φT1 goes low, ending the reset process. Next, the control pulse φTX and the control pulse φT2 become high, and the photocharge of the photodiode 2 is turned on by turning on the MOS transistor 4.
Transfer the photocharge to the first gate of the transistor 20 and the control pulse φS remains high, so
Output to the drain of the transistor 20. Then M
Since the OS transistor 22 is a constant current source, the MOS transistor 20 amplifies the gate voltage to a predetermined amplification degree and outputs it to the output line 7. The amplified photocharge on the output line 7 is M
The OS transistor 12 is turned on, and the offset charge and the photocharge that have been amplified are stored in the storage capacitor 10.

After that, the control pulse φS becomes low, and M
The operation of the OS transistor 20 is turned off, then the control pulse φH becomes high, the MOS transistors 13 and 14 are turned on, and the amplified offset charge and photocharge of the storage capacitors 9 and 10 are output to the vertical output lines 15 and 16. Then, the difference amplifier 17 obtains the difference between the electric charges of both the output lines 15 and 16 and amplifies it, cancels and eliminates the offset potential, and outputs the amplified image signal of the true photocharge from the output terminal 18. It

The above-mentioned one vertical output is similarly scanned for the other vertical output lines, and the same scanning is repeated for the horizontal output line (not shown) to sequentially output the photocharges of the pixels arranged vertically and horizontally. Thus, the image output signal of the image sensor or the area sensor can be output.

In the present invention, the MOS transistor 2
The ratio between the change in the gate potential of 0 and the change in the drain output potential becomes negative, and the output is inverted as compared with the conventional example shown in FIG. 4, but the inverting amplifier gain can be set to 1 or more, and the differential amplifier, etc. The decrease in S / N due to various noises coming from the circuit is suppressed small. Also, the MOS transistor 2
Since the amplification type is 0, 22 and the MOS transistor 22 is operated as a constant current source, a low voltage driving solid-state imaging device can be obtained by configuring the MOS transistor to have a low voltage operation structure.

Further, since the VDD power supply line does not pass through the pixel as compared with the conventional one, the difficulty of forming a fine pixel in the pixel portion is alleviated, and the aperture area can be made larger than that of the conventional pixel. It is possible to improve and obtain a high quality image signal.

(2) Second Embodiment FIG. 3 shows a solid-state image pickup device 1 according to a second embodiment of the present invention.
It is an equivalent circuit diagram including a pixel and a periphery. In the figure, 2
Reference numeral 3 denotes a switch MOS transistor for grounding the output line 7, and the switch is controlled by a pulse control pulse φVC applied to the gate of the MOS transistor 23. The gate of the MOS transistor 22 has a control pulse φ.
Controlled by L. In the second embodiment, there is no MOS transistor for reading and selecting from the pixel, and the drain of the inverting amplifier MOS transistor 20 is directly connected to the output line 7. Therefore, the MOS transistor 20 of the pixel that is not read out must be turned off. Therefore, the control pulse φL is set to low to turn off the MOS transistor 22, and the control pulse φVC is set to high to set MO.
The S transistor 23 is turned on, the output line 7 is grounded, and in this state, a high pulse of the control pulse φR causes a reset M
MOS transistor 20 through OS transistor 21
Ground the gate of to reset. The MOS transistor 20 is made to have non-conduction enhancement when the gate-source voltage is zero, and is inverted when the gate potential of the inverting amplifier MOS 20 of the pixel which is not read, that is, the non-selected pixel is set to 0V (GND). Amplifier MOS2
Since 0 must be completely turned off, there is no output from non-selected pixels. Next, with the control pulse φVC set to low and the control pulse φL set to high, the read pixels are selected and read according to the timing shown in FIG.

That is, with the control pulse φVC set to low and the control pulse φL set to high, the enhancement-type MOS transistor 20 becomes conductive, the control pulse φT1 becomes high, and the offset amplified by the inverting amplifier MOS transistor 20. The potential is stored in the storage capacitor 9, the control pulse φTX is set to high to turn on the transfer MOS transistor, and the control pulse φT2 is set to high to store the amplified photocharge and the offset potential in the storage capacitor 10. , The control pulse φH is set to high to output the accumulated charges of the storage capacitors 9 and 10 to the vertical output lines 15 and 16, and the differential amplifier 17 obtains and amplifies the difference between the charges of both output lines 15 and 16, The offset potential is deleted, and the amplified image signal of the true photocharge is output from the output terminal 18.

In the above embodiment, the operation of one pixel which outputs the photocharge detected by one photodiode has been described. However, when a line sensor is used, a plurality of pixels for one line are arranged side by side and sequentially output vertically. 1 by scanning the line
Image signals for lines can be obtained, and when it is used as an area sensor, a plurality of pixels are arranged vertically and horizontally,
A two-dimensional image signal can be obtained by sequentially scanning each horizontal line and each vertical line.

According to the configuration of the second embodiment as described above,
Compared with the conventional example, the pixel does not have a VDD power supply line, and the MOS transistors in the pixel are three for inverting amplifier, transfer, and reset. This is extremely advantageous over the conventional one in terms of the size of the part.

[0025]

As described above, according to the present invention,
Since the pixel output is performed by the MOS transistor for the inverting amplifier that can set the gain to 1 or more, the sensor output potential can be made larger than that of the conventional amplification type MOS sensor, so that the decrease of the S / N can be suppressed. Is effective for.
Further, compared to the conventional pixel configuration, the power line is not provided, and M
The number of OS transistors can be reduced, manufacturing can be facilitated for applications of fine pixels, and the opening area can be widened, so that S / N is improved.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an input / output characteristic diagram that determines a reset potential of a pixel of the present invention.

FIG. 3 is an equivalent circuit diagram showing a second embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of a conventional solid-state imaging device.

FIG. 5 is a pulse timing diagram showing a pixel driving method of the present invention and a conventional example.

[Explanation of symbols]

 1 Pixel 2 Photodiode 3, 4, 5, 6 MOS Transistor 7 Output Line 8 MOS Transistor 9, 10 Storage Capacitance 11, 12 MOS Transistor 13, 14 MOS Transistor 15, 16 Output Line 17 Differential Amplifier 18 Output Terminal 20, 21 , 22, 23 MOS transistors

Claims (4)

[Claims] 1. A solid-state imaging device in which a MOS transistor is provided for pixel readout, and a signal potential due to an optical signal charge received at the gate of the MOS transistor is output from the drain of the MOS transistor, the gate potential change amount of the MOS transistor A solid-state imaging device, wherein the ratio of the change in output potential to the change in output potential is negative. 2. The solid-state imaging device according to claim 1, wherein the MOS transistor is an enhancement type. 3. A solid-state imaging device, wherein a MOS transistor is provided for pixel readout, and a signal potential due to an optical signal charge received by the gate of the MOS transistor is output from the drain of the MOS transistor, wherein the gate of the MOS transistor outputs the pixel. A solid-state imaging device characterized by being reset to a line potential. 4. The solid-state imaging device according to claim 3, wherein a MOS transistor for a constant current source is connected to the drain of the MOS transistor.