JPH0945016A - Information processing device - Google Patents

Abstract

(57) An object of the present invention is to improve the error correction capability without impairing the effect of high density recording as an optical disk device, and without prolonging the time required for correction as in the case of multiplexing error correction codes. Provided is an information processing device which can be improved. Out of the signals from an 8-bit shift register, data that does not match the code conversion rule of the demodulation ROM 44 is detected, and the interleave in the memory 2 in which the same data as the detected data exists is specified. Then, of the data in the memory 2, the contents of the designated interleaved data are corrected based on the same interleaved error correction code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, for example, records / reproduces information on / from an optical disk (disc-shaped information storage medium) by irradiating a laser beam and utilizing changes in the refractive index of a recording film. The present invention relates to an information processing device such as an optical disk device.

[0002]

2. Description of the Related Art An analog signal reproduced from an optical disk is converted into a binary digital signal of "1" and "0". This operation is called binarization. As a binarization method, a method using a slice level and a method using a signal obtained by differentiating a reproduction signal are known.

The binarized digital signal is a PLL (Ph
ase Locked Loop) circuit to obtain a data sequence synchronized with the recovered clock. This data series is called a channel data series.

A sequence consisting of "1" and "0" obtained through the PLL circuit after binarization is, for example, a (2,7) -modulated code sequence. (2,7) modulation is RLL
This is a type of (Run Length Limited) code and is called (2,7) modulation because the minimum run is "2" and the maximum run is "7". A run generally means a continuous or continuous bit length of the same bit (“0” or “1”), but here, the number of continuous bits of “0” is called a run without particular notice.

In (2,7) modulation, there is no continuation of "1",
The number of consecutive bits of "0" is "2" or more and "7" or less.
The RLL code means a code having a finite maximum inversion interval. The data sequence that the user of the drive device wants to record (hereinafter referred to as the user data sequence) may have a large number of consecutive "1" s and "0" s. A code in which "1" is generated is obtained.

Since the PLL circuit performs the phase comparison from the timing of the transition from "0" to "1" or "1" to "0" of the binarized signal (hereinafter referred to as a binarized signal), ( 2, 7) By performing modulation, the phase comparison interval can be kept within a certain period. The channel data sequence is input to the demodulator and inversely converted into the user data sequence.

The user data sequence is recorded on the optical disc in units called sectors. The size of the sector is, for example, "512B", "1KB", "2KB" or the like. B
Represents a byte, which is the same as the "8" bit of user data. To this sector, for example, a header portion formed of embossed pits, user data recorded by irradiating a laser beam during data recording, VFO, a sector number, a synchronization code, a CRC code, an ECC code, etc. are added, 2, 7) Modulation is performed, and information is recorded by, for example, mark-to-mark recording.

The synchronization code is, for example, user data "15".
It is a special data series that "1B" is added to B ".
Bit errors and the like are corrected by this synchronization code to prevent the propagation of errors. The CRC code is used for such purposes as determining whether or not there is an error in the read user data, and for example, a "4B" CRC code is added to "512B" user data.

The ECC code is a code for detecting an error position and correcting an error, for example, "512B".
An ECC code of "80B" is added to the user data of. The sector number is recorded in a portion called a pointer area, and, for example, "4B" sector number data is added to "512B" user data. User data is input to the optical disk drive device from an information input terminal or the like via a SCSI bus or the like.

SCSI (Small Computer System Interf
ace) is a peripheral device interface of a small computer and is used in optical disk drive devices, CD-ROMs, hard disks, image scanners, and the like. The user data obtained is sector-by-sector (DRAM (Dynamic Rand)
om Access Memory).

User data is interleaved to convert burst errors into random errors and short byte errors. For example, when the user data per “1” sector is “512B”, the pointer (4B), CRC
"600B" data obtained by adding (4B) and ECC (80B) is arranged in a (120 × 5) matrix. This matrix consists of five "120B" columns, each column containing "104B" data (user data, pointer, C
One of RC) and an ECC code of "16B". This ECC code is, for example, LDC (Long Dista).
nt Code) is used.

LDC is a code having a long minimum distance and a high correction capability, and is one of standardization plans for optical disks. In this case, the LDC performs error detection and error correction in one row consisting of "120B", but "8B" when there is no loss.
Can be corrected up to.

The disappearance means an error whose position is known but whose pattern (numerical value) is not known. It is known that if the erasure can be detected accurately, error correction up to "16B" can be performed with one row of "120B". However, the conventional technique does not detect erasure, but corrects up to "8B" per column without erasure. With this method, a maximum of "4" per "1" sector
Only error correction up to 0B "is possible.

[0014]

As a method for performing high density recording on an optical disk, there are a method of reducing the distance between pits and a method of reducing the distance between tracks. In particular, when the method of reducing the interval between pits is adopted, that is, when the recording linear density is increased, the distance (along the track) required to record 1B becomes small.

Therefore, an optical disc having a large linear density and an optical disc having a small linear density cause a difference in the number of error bytes even with scratches and dust on the same size disc, and an optical disc having a large linear density has an error correction aspect. May cause disadvantages.

There are several possible ways to solve this problem. For example, a method of increasing the redundancy and improving the error correction capability can be considered. Redundancy is the ratio of the number of bytes in the entire sector to the number of redundant (ECC, etc.) bytes in the sector. With this method, the number of bytes of the ECC code increases, so that the amount of information that must be recorded increases and the effect of high-density recording may decrease.

A method of improving the error correction capability by using a plurality of correction sequences called product codes is also conceivable. In the product code, an error correction code is added to each of a plurality of vertical and horizontal sequences by interleaving, and the error correction code is multiplexed to form a code having a high error correction capability. However, the time required for correction becomes long, which may cause a problem in data transfer speed at the time of reproducing information.

The present invention takes the above circumstances into consideration,
It is an object of the invention to provide an information processing apparatus capable of improving the error correction capability without impairing the effect of high density recording and without prolonging the time required for correction.

[0019]

An information processing apparatus according to a first aspect of the present invention includes a reproduction signal generating means for receiving a reflected light beam from an information storage medium and generating a reproduced signal corresponding to the reflected light beam, and this reproducing means. Binarizing means for binarizing the reproduction signal generated from the signal generating means, conversion means for converting the output of the binarizing means into a data sequence synchronized with the reproduction clock signal of the reproducing means, and this conversion Demodulation means for demodulating the output of the means based on a predetermined code conversion rule,
Storage means for arranging and storing each data and each error correction code demodulated by this demodulation means in a matrix, and forming a plurality of interleaved columns each consisting of a predetermined number of data and a predetermined number of error correction codes in the array. And a specifying means for detecting data that does not match the code conversion rule of the demodulating means among the outputs of the converting means, and specifying interleaving in the storing means where the same data as the detected data exists, and in the storing means Correction means for correcting the contents of the interleaved data designated by the designating means based on the error correction code of the same interleave.

The information processing apparatus of the second invention receives a reflected light beam from the information storage medium and generates a reproduced signal corresponding to the reflected light beam, and a reproduced signal generating means for generating the reproduced signal. Binarizing means for binarizing the reproduced signal, converting means for converting the output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means, and the output of the converting means is predetermined. The demodulation means for demodulating based on the code conversion rule, and the data and the error correction codes demodulated by the demodulation means are arrayed and stored in a matrix form, and a predetermined number of data and a predetermined number of data are stored in the array. Storage means for forming a plurality of interleaved sequences of error correction codes, and data of the output of the conversion means that does not match the code conversion rule of the demodulation means are detected and detected. The first data specifying the interleave in the storage means in which the same data as the existing data exists, and when the number of the interleaves specified by the first specification means is a predetermined value or more, all the interleaves in the storage means A second designating means for designating and a correcting means for correcting the content of the interleaved data designated by the first or second designating means among the respective data in the storage means based on the error correction code of the same interleave. When,
Is provided.

The information processing apparatus of the third invention receives a reflected light beam from the information storage medium and generates a reproduced signal corresponding to the reflected light beam, and a reproduced signal generating means for generating the reproduced signal. Binarizing means for binarizing the reproduced signal, converting means for converting the output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means, and the output of the converting means is predetermined. The demodulation means for demodulating based on the code conversion rule, and the data and the error correction codes demodulated by the demodulation means are arrayed and stored in a matrix form, and a predetermined number of data and a predetermined number of data are stored in the array. Storage means for forming a plurality of interleaved sequences of error correction codes, and data of the output of the conversion means that does not match the code conversion rule of the demodulation means are detected and detected. The interleaving data designated by the first designating means among the respective data in the storage means and the interleaving data designated by the first designating means in which the same data as the stored data exists. First correction means for correcting the error correction code based on the error correction code, and detection means for sequentially detecting a plurality of synchronization signals existing in each data demodulated by the demodulation means,
When there is an abnormality in the time interval of each synchronization signal detected by the detecting means, a third specifying means for specifying the data in the storage means corresponding to the period of the abnormality and the respective data in the storage means Second correction means for correcting the content of the data designated by the third designation means based on the interleaved error correction code in which the data exists.

An information processing apparatus according to a fourth aspect of the present invention receives a reflected light beam from an information storage medium and generates a reproduced signal corresponding to the reflected light beam, and a reproduced signal generating means for generating the reproduced signal. Binarizing means for binarizing the reproduced signal, converting means for converting the output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means, and the output of the converting means is predetermined. The demodulation means for demodulating based on the code conversion rule, and the data and the error correction codes demodulated by the demodulation means are arrayed and stored in a matrix form, and a predetermined number of data and a predetermined number of data are stored in the array. Storage means for forming a plurality of interleaved sequences of error correction codes, and data of the output of the conversion means that does not match the code conversion rule of the demodulation means are detected and detected. The first data specifying the interleave in the storage means in which the same data as the existing data exists, and when the number of the interleaves specified by the first specification means is a predetermined value or more, all the interleaves in the storage means A first designating means for designating and a content of interleaved data designated by the first or second designating means among the respective data in the storage means are corrected based on an error correction code of the same interleave. When there is an abnormality in the time interval between the correction means, the detection means for sequentially detecting a plurality of synchronization signals existing in each data demodulated by the demodulation means, and the synchronization signals detected by the detection means,
A third designating means for designating data in the storage means corresponding to the abnormal period and the content of the data designated by the third designating means among the data in the storage means are present in the data. Second correction means for correcting the error based on the interleaved error correction code.

The information processing apparatus of the fifth invention receives a reflected light beam from the information storage medium and generates a reproduced signal corresponding to the reflected light beam, and a reproduced signal generating means for generating the reproduced signal. Binarizing means for binarizing the reproduced signal, converting means for converting the output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means, and the output of the converting means is predetermined. The demodulation means for demodulating based on the code conversion rule, and the data and the error correction codes demodulated by the demodulation means are arrayed and stored in a matrix form, and a predetermined number of data and a predetermined number of data are stored in the array. Storage means for forming a plurality of interleaved sequences of error correction codes, and data of the output of the conversion means that does not match the code conversion rule of the demodulation means are detected and detected. The first data specifying the interleave in the storage means in which the same data as the existing data exists, and when the number of the interleaves specified by the first specification means is a predetermined value or more, all the interleaves in the storage means A first designating means for designating and a content of interleaved data designated by the first or second designating means among the respective data in the storage means are corrected based on an error correction code of the same interleave. Correction means, detection means for sequentially detecting a plurality of sync signals existing in each data demodulated by the demodulation means, and whether or not there is an abnormality in the time interval of each sync signal detected by the detection means An abnormality detecting means, and a third specifying means for specifying the data in the storage means corresponding to the period of the abnormality when the abnormality detecting means detects the abnormality Among the data in the storage means, the contents of the data specified by the third specifying means, comprising a second correcting means for correcting, based on the error correction code interleaving the data resides, the.

The information processing apparatus of the sixth invention receives a reflected light beam from the information storage medium and generates a reproduced signal corresponding to the reflected light beam, and a reproduced signal generating means for generating the reproduced signal. Binarizing means for binarizing the reproduced signal, converting means for converting the output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means, and the output of the converting means is predetermined. The demodulation means for demodulating based on the code conversion rule, and the data and the error correction codes demodulated by the demodulation means are arrayed and stored in a matrix form, and a predetermined number of data and a predetermined number of data are stored in the array. Storage means for forming a plurality of interleaved sequences of error correction codes, and data of the output of the conversion means that does not match the code conversion rule of the demodulation means are detected and detected. Specifying means for issuing an error flag signal for specifying the interleave in the storage means in which the same data as the existing data exists, and interleaving of the interleave specified by the error flag signal of the specifying means among the respective data in the storage means. Correction means for correcting the content of the data based on the same interleaved error correction code.

The information processing apparatus according to the seventh aspect of the present invention receives a reflected light beam from the information storage medium and generates a reproduced signal according to the reflected light beam, and a reproduced signal generating means for generating the reproduced signal. Binarizing means for binarizing the reproduced signal, converting means for converting the output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means, and the output of the converting means is predetermined. The demodulation means for demodulating based on the code conversion rule, and the data and the error correction codes demodulated by the demodulation means are arrayed and stored in a matrix form, and a predetermined number of data and a predetermined number of data are stored in the array. Storage means for forming a plurality of interleaved sequences of error correction codes, and data of the output of the conversion means that does not match the code conversion rule of the demodulation means are detected and detected. The first designating means for issuing an error flag signal for designating the interleave in the storage means in which the same data as the stored data exists, and the number of interleaves designated by the error flag signal of the first designating means are equal to or more than a predetermined value At this time, the second designating means for issuing an error flag signal for designating all the interleaves in the storage means, and the error flag signal of the first or second designating means among the respective data in the storage means are designated. Correction means for correcting the content of interleaved data based on the same interleaved error correction code.

An information processing apparatus according to an eighth aspect of the present invention receives a reflected light beam from an information storage medium and generates a reproduced signal according to the reflected light beam, and a reproduced signal generating means for generating the reproduced signal. Binarizing means for binarizing the reproduced signal, converting means for converting the output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means, and the output of the converting means is predetermined. The demodulation means for demodulating based on the code conversion rule, and the data and the error correction codes demodulated by the demodulation means are arrayed and stored in a matrix form, and a predetermined number of data and a predetermined number of data are stored in the array. Storage means for forming a plurality of interleaved sequences of error correction codes, and data of the output of the conversion means that does not match the code conversion rule of the demodulation means are detected and detected. Designated by the error flag signal of the first designating means among the respective data in the storage means, and a first designating means for issuing an error flag signal for designating the interleave in the storage means in which the same data as the stored data exists. First correction means for correcting the content of the interleaved data based on the same interleaved error correction code, and detection means for sequentially detecting a plurality of synchronization signals existing in each data demodulated by the demodulation means. A third designating means for issuing an error flag signal for designating the data in the storage means corresponding to the abnormal period when there is an abnormality in the time interval of each synchronization signal detected by the detecting means; Of each data in the storage means,
Second correction means for correcting the content of the data designated by the error flag signal of the third designation means based on the interleaved error correction code in which the data exists;
Is provided.

The information processing apparatus according to the ninth aspect of the invention receives a reflected light beam from the information storage medium and generates a reproduced signal according to the reflected light beam, and a reproduced signal generation means for generating the reproduced signal. Binarizing means for binarizing the reproduced signal, converting means for converting the output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means, and the output of the converting means is predetermined. The demodulation means for demodulating based on the code conversion rule, and the data and the error correction codes demodulated by the demodulation means are arrayed and stored in a matrix form, and a predetermined number of data and a predetermined number of data are stored in the array. Storage means for forming a plurality of interleaved sequences of error correction codes, and data of the output of the conversion means that does not match the code conversion rule of the demodulation means are detected and detected. The first designating means for issuing an error flag signal for designating the interleave in the storage means in which the same data as the stored data exists, and the number of interleaves designated by the error flag signal of the first designating means are equal to or more than a predetermined value. At this time, the second designating means for issuing an error flag signal for designating all the interleaves in the storage means, and the error flag signal of the first or second designating means among the respective data in the storage means are designated. First correction means for correcting the content of the interleaved data based on the same interleaved error correction code, and detection means for sequentially detecting a plurality of synchronization signals existing in each data demodulated by the demodulation means. When there is an abnormality in the time interval of each synchronization signal detected by this detection means, the above-mentioned corresponding to the period of the abnormality is described. The third designating means for issuing an error flag signal for designating the data in the means, and the contents of the data designated by the error flag signal of the third designating means among the respective data in the storage means, A second correction means for correcting the interleave error correction code based on the existing interleave error correction code.

The information processing apparatus according to the tenth aspect of the present invention receives a reflected light beam from the information storage medium and generates a reproduced signal corresponding to the reflected light beam, and a reproduced signal generating means for generating the reproduced signal. Binarizing means for binarizing the reproduced signal, converting means for converting the output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means, and the output of the converting means is predetermined. The demodulation means for demodulating based on the code conversion rule, and the data and the error correction codes demodulated by the demodulation means are arrayed and stored in a matrix form, and a predetermined number of data and a predetermined number of data are stored in the array. Storage means for forming a plurality of interleaved sequences of error correction codes, and data of the output of the conversion means that does not match the code conversion rule of the demodulation means are detected and detected. A first specifying means for issuing an error flag signal for specifying the interleave in the storage means the same data resides and data, when the number of interleaving specified in the first designating means is a predetermined value or more,
Second designation means for issuing an error flag signal for designating all interleaves in the storage means, and one of the data in the storage means designated by the error flag signal of the first or second designation means. A first correction means for correcting the content of the interleaved data based on the same interleaved error correction code; and a detection means for sequentially detecting a plurality of synchronization signals present in each data demodulated by the demodulation means, Abnormality detection means for detecting whether or not there is an abnormality in the time interval of each synchronization signal detected by the detection means, and when this abnormality detection means detects an abnormality, the data in the storage means corresponding to the period of the abnormality is displayed. A third designating means for issuing an error flag signal for designating, and an error flag signal of the third designating means among the respective data in the storage means. Ri comprises a contents data designated, and a second correction means for correcting, based on the error correction code interleaving the data resides, the.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 3, reference numeral 1 denotes an optical disk which is an information storage medium, and is rotated by a motor 3 at a constant speed, for example. The motor 3 is controlled by a motor control circuit 4. Recording and reproduction of information on the optical disc 1 are performed by the optical head 5. The optical head 5 is fixed to a drive coil 7 constituting a movable part of a linear motor 6, and the drive coil 7 is connected to a linear motor control circuit 8.

A speed detector 9 is connected to the linear motor control circuit 8, and the optical head 5 detected by the speed detector 9 is connected.
Is sent to the linear motor control circuit 8. A permanent magnet (not shown) is provided at a fixed portion of the linear motor 6. When the drive coil 7 is excited by the linear motor control circuit 8, the optical head 5 is moved in the radial direction of the optical disc 1.

The optical head 5 is provided with an objective lens 10 supported by a wire or a leaf spring (not shown). The objective lens 10 can be moved in the focusing direction (the direction of the optical axis of the lens) by driving the drive coil 11, and can be moved in the tracking direction (the direction orthogonal to the optical axis of the lens) by driving the drive coil 12. Is possible.

A laser light beam is emitted from the semiconductor laser oscillator 9 under the drive control of the laser control circuit 13.
The laser control circuit 13 includes a modulation circuit 14 and a laser drive circuit 15, and operates in synchronization with the recording clock signal supplied from the PLL circuit 16. The modulation circuit 14 modulates the recording data supplied from the error correction circuit 32 into a signal suitable for recording, that is, 2-7 modulation data. The laser drive circuit 15 drives a semiconductor laser oscillator (or an argon neon laser oscillator) 19 according to the 2-7 modulation data from the modulation circuit 14.

The PLL circuit 16 divides the basic clock signal emitted from the crystal oscillator into a frequency corresponding to the recording position on the optical disc 1 at the time of recording, thereby generating a clock signal for recording, and at the time of reproducing. , Generates a reproduction clock signal corresponding to the reproduced synchronization code, and detects a frequency abnormality of the reproduction clock signal. This abnormal frequency is detected by whether or not the frequency of the reproduction clock signal is within a predetermined frequency range corresponding to the recording position of the data to be reproduced on the optical disc 1. Also, PL
The L circuit 16 selectively outputs a clock signal for recording or reproduction in response to a control signal from the CPU 30 and a signal from the counting unit 47 of the data reproducing circuit 18.

The laser light beam emitted from the semiconductor laser oscillator 19 is irradiated onto the optical disc 1 through the collimator lens 20, the half prism 21 and the objective lens 10. The reflected light from the optical disc 1
0, a half prism 21, a condenser lens 22, and a cylindrical lens 23, and are guided to a photodetector 24.

The photodetector 24 is a four-divided photodetector cell 24
a, 24b, 24c, and 24d. The output signal of the photodetector cell 24a is supplied to one end of the adder 26a via the amplifier 25a. The output signal of the light detection cell 24b is supplied to one end of an adder 26b via an amplifier 25b. The output signal of the light detection cell 24c is
It is supplied to the other end of the adder 26a via 5c. The output signal of the light detection cell 24d is supplied to the other end of the adder 26b via the amplifier 25d.

Furthermore, the output signal of the photodetector cell 24a is
The signal is supplied to one end of the adder 26c via the amplifier 25a. The output signal of the light detection cell 24b is supplied to one end of an adder 26d via an amplifier 25b. Photodetection cell 24
The output signal of c is supplied to the other end of the adder 26d via the amplifier 25c. The output signal of the light detection cell 24d is supplied to the other end of the adder 26c via the amplifier 25d.

The output signal of the adder 26a is a differential amplifier OP.
2, and the output signal of the adder 26b is supplied to the non-inverting input terminal of the differential amplifier OP. The differential amplifier OP2 outputs a signal related to the focus point according to the difference between the two output signals of the adders 26a and 26b. This output is supplied to the focusing control circuit 27. The output signal of the focusing control circuit 27 is supplied to the focusing drive coil 12. Thus, the laser light beam is controlled to be always just focused on the optical disc 1.

The output signal of the adder 26c is a differential amplifier OP.
1, and the output signal of the adder 26d is supplied to the non-inverting input terminal of the differential amplifier OP1. The differential amplifier OP1 outputs a track difference signal according to the difference between the two output signals of the adders 26c and 26d. This output is supplied to the tracking control circuit 28. The tracking control circuit 28 creates a track drive signal according to the track difference signal from the differential amplifier OP1.

The track drive signal output from the tracking control circuit 28 is the drive coil 1 in the tracking direction.
1 is supplied. Further, a track difference signal used in the tracking control circuit 28 is supplied to the linear motor control circuit 8.

By performing the focusing and tracking, each photodetecting cell 24a of the photodetector 24,
... the sum signal of the output signals of 24d,
The change in the reflectance from the pits (recording information) formed on the track is reflected in the output signal of the adder 26e, which is the addition of the two output signals c and 26d. This signal is supplied to the data reproducing circuit 18. Data reproduction circuit 18
Reproduces recorded data based on a reproduction clock signal from the PLL circuit 16.

Further, the data reproducing circuit 18 includes an adder 26
The sector mark in the preformatted data is detected based on the output signal of e and the reproduction clock signal from the PLL circuit 16, and the sector mark is detected based on the binarized signal and the reproduction clock signal supplied from the PLL circuit 16. A track number and a sector number as address information are reproduced from the binarized signal.

The reproduction data of the data reproduction circuit 18 is the bus 2
9 is supplied to the error correction circuit 32. The error correction circuit 32 outputs an error correction code (EC
C) to correct the error, or add an error correction code (ECC) to the recording data supplied from the interface circuit 35 and output it to the memory 2.

The reproduced data error-corrected by the error correction circuit 32 is the bus 29 and the interface circuit 3.
5 is supplied to a storage medium control device 36 as an external device. The recording data emitted from the storage medium control device 36 is supplied to the error correction circuit 32 via the interface circuit 35 and the bus 29.

When the objective lens 10 is moved by the tracking control circuit 28, the linear motor 6 is moved by the linear motor control circuit 8 so that the objective lens 10 is located near the center position in the optical head 5. Be moved.

The D / A converter 31 controls the focusing control circuit 27, the tracking control circuit 28, the linear motor control circuit 8 and the CPU 30 which controls the entire optical disk device.
Used for exchanging information with

The motor control circuit 4, the linear motor control circuit 8, the laser control circuit 15, the PLL circuit 16, the data reproduction circuit 18, the focusing control circuit 27, the tracking control circuit 28, the error correction circuit 32, etc. are connected via a bus 29. It is controlled by the CPU 30. The CPU 30 performs a predetermined operation according to the program recorded in the memory 2.

Here, an example of the sector format in the optical disc 1 is shown in FIG. The case where the user data per sector is "512B" is shown. The numbers in the figure represent the number of (data) bytes. In the following description, the term “byte” simply means the number of user bytes, and the channel bit is the same as 16 bits.

VFO1 (Variable Frequency Oscillato
r) is an area for pulling in the PLL, and is a channel bit in which a sequence of "010 ..." Is recorded for "12" bytes (192 bits in the channel bit).

AS is an abbreviation for (Address Sync), which is a "1" byte synchronization code indicating where the sector address starts, and may also be referred to as AM (Address Mark). As the pattern, a special pattern that does not appear in the data part "0100100000000100" is used.

ID1 (Identifier) to ID3 are "5"
This is an area showing byte address information. The sector address (including ID number) is "3" in the contents of "5" bytes.
Byte and CRC are "2" bytes.

The sector address is “22” bits before modulation, that is, user bits, and the ID number is “24” user bits = “3” bytes in total for “2” user bits. Therefore, in this format, "4", "194", and "304" values can be taken as the sector address.

The ID number is "1" for ID1, for example.
So, it is a number that represents the number of the three times overwritten. Since it can take values from "1" to "3", "2" bits are required.

CRC (Cyclic Redundancy Check) is
The error detection code for the "3" bytes of the sector address (including the ID number) is "2" bytes. It is possible to detect the presence / absence of an error in the read ID (“5” bytes).

Similar to VFO1, VFO2 has the same pattern for locking the PLL recorded for "8" bytes. PA (Postambles) is an area of "1" bytes or "6" bytes called a postamble and has ID3.
Or it is located after the data section. This is an area provided so that word delimiters always occur until the end when the modulation is performed to the (2, 7) modulation code which is the variable word length modulation method. GAP
In a region without (Gap), any length of "16" to "32" channel bits is randomly taken.

ALPC (Auto Laser Power Control)
Has a length of "4" bytes, for example in hexadecimal notation,
The patterns "33", "33", "30", and "1A" are recorded. Although VFO3 is also an area for PLL lock, it is also an area for the purpose of synchronizing byte boundaries by inserting a synchronization code in the same pattern.

DS (Data Sync) is DM (Data Mark)
) Is also called, and is a synchronization code for synchronizing byte boundaries for the data portion that follows. DATA (Data
field) is called a data part, and is a user data, a resync code, an error correction code (ECC; Erro).
r Correction Code), CRC, pointer area, etc. These data are arranged in a matrix in a predetermined order (2, 7) and modulated, and then recorded on the optical disc 1.

The BUF (Buffer) is an area for absorbing disk rotation fluctuations and the like and does not record anything. In the information processing apparatus so-called optical disk apparatus configured as described above, the main part of the present invention is mounted in the data reproducing circuit 18.
This essential part is shown in FIG.

As shown in FIG. 1, the signal reproduced by the optical disk reproducing means is supplied to a binarizing circuit 41, where it is binarized based on a constant threshold level TH. The output signal of the binarization circuit 41 is supplied to the PLL circuit 16 and converted into a data series synchronized with the reproduction clock signal of the optical disk reproduction means.

The output signal of the PLL circuit 16 is supplied to the 8-bit shift register 42, where it is converted into an 8-bit parallel signal. This signal is the pattern detection circuit 4
3, demodulation ROM 44, and error flag generation circuit 45
Is supplied to.

The pattern detection circuit 43 detects the resync code, which is the synchronization signal, of the signals from the 8-bit shift register 42. The demodulation ROM 44 demodulates the signal from the 8-bit shift register 42 based on a predetermined (2, 7) code conversion rule, for example. This demodulated signal has an effective length counter 46 and P
It is supplied to the / S (parallel / serial) conversion circuit 47.

The effective length counter 46 is for knowing the word boundary of the variable length block code by the (2,7) code conversion. P / S (parallel / serial) conversion circuit 47
Converts the output signal of the 8-bit shift register 42 into a serial signal for each word according to the output of the effective length counter 46, and outputs the serial signal. This output signal is supplied to the memory 2 and stored therein.

Under the control of the CPU 30, each data to be demodulated and each error correction code are arranged and stored in a matrix in the memory 2, and a predetermined number of data and a predetermined number of error correction codes ( A plurality of interleaved rows of ECC) are formed. The format of each data and each error correction code in this memory 2 is shown in FIG.

Although DS1 to DS3 are data sync codes and are not included in the data part, they are shown in the drawing. "1" in the figure
“512” represents the “1” to “512” bytes of the user data. "P1.1" to "P1.4" are
The self-address and the like are recorded in the pointer area (4 bytes).

"CRC1" to "CRC4"("4" bytes) can detect an error of (user data "512" bytes + pointer "4" bytes). "E
1.1 ”to“ E5.16 ”are error correction codes,
"80" bytes are added. This error correction code can perform error correction in the vertical direction of this figure. The columns in the vertical direction are called interleaves, and there are five columns in the vertical direction, numbered “0” to “4” for each column, and called interleave “0”.

One interleave is "104" bytes of user data, pointer data, CRC and "1".
It consists of 6 ”bytes of error correction code, and is“ 1 ”in total.
It is 20 "bytes.

It is known that the error detection and error correction capability by the error correction code is assigned "8" bytes for one interleave when there is no erasure and "16" bytes for one interleave when there is erasure. There is.

The disappearance means an error whose position is known but the error pattern (numerical value) is not known. Therefore, in the case of disappearance mentioned above, "1
For all 6 "byte errors, only the position is known. When there is no loss, the error position and error pattern are not known for all" 8 "byte errors. Each error and the error pattern are considered to be one unknown, and this is "1.
If it is 6 "or less, it can be corrected.

For example, "4" bytes are not erased and "8" bytes are erased with an error "12".
The bytes are correctable. This is because {(position + pattern) × 4 = 8} for “4” bytes and {(pattern) × 8 = 8} for “8” bytes, and the total number of unknowns is “16”.

"1" of each data and error correction code
For every 5 "bytes, resync codes" RS1 "to" RS
39 ". On the other hand, the error flag generation circuit 45 has the following functional means [1] to [4].

[1] For detecting data out of the signal from the 8-bit shift register 42 that does not match the code conversion rule of the demodulation ROM 44, and specifying the interleave in the memory 2 in which the same data as the detected data exists. First designating means for issuing an error flag signal. In this case, in order to detect data that does not match the code conversion rule, the demodulation R
The same demodulation ROM as the OM44 is provided.

[2] Second designating means for issuing an error flag signal for designating all interleaving in the memory 2 when the number of interleaves designated by the first designating means is equal to or larger than a predetermined value "3".

[3] Abnormality detecting means for detecting whether or not there is an abnormality (such as missing bits) in the time interval of each resync code detected by the pattern detection circuit 43. [4] Third designating means for issuing an error flag signal for designating the data in the memory 2 corresponding to the period of the abnormality when the abnormality detecting means detects the abnormality.

These error flag signals are supplied to the error correction circuit 32. The error correction circuit 32 has the following functional means [1] and [2]. [1] A first correction for correcting the content of the interleaved data designated by the error flag signal from the first or second designating means among the respective data in the memory 2 based on the same interleaved error correction code means.

[2] A second correction for correcting the content of the data designated by the error flag signal of the third designation means among the respective data in the memory 2 based on the interleaved error correction code in which the data exists. means.

Next, the operation of the above configuration will be described. The reproduction signal generated by the reproduction signal generating means is binarized by the binarization circuit 41. This binarized signal is the PLL circuit 1
6, the data sequence is converted into a data sequence synchronized with the reproduction clock signal. The output of the PLL circuit is converted into a parallel signal by the 8-bit shift register 42 and supplied to the pattern detection circuit 43, the demodulation ROM 44, and the error flag generation circuit 45.

The pattern detection circuit 43 detects a resync code in the signal from the 8-bit shift register 42. Then, this detection signal is supplied to the error flag generation circuit 45.

In the demodulation ROM 44, the signal from the 8-bit shift register 42 is demodulated based on the (2,7) code conversion rule. This demodulated signal is converted into a serial signal by the P / S conversion circuit 47 and supplied to the memory 2.

In the memory 2, each data to be demodulated and each error correction code are arranged and stored in a matrix form, and an interleaved column consisting of a predetermined number of data and a predetermined number of error correction codes (ECC) in the array. Are formed in plural.

In the error flag generating circuit 45, of the signals from the 8-bit shift register 42, the demodulation ROM 44
The data that does not match the (2, 7) code conversion rule is detected, and an error flag signal for designating the interleave in the memory 2 in which the same data as the detected data exists is issued.

For example, in FIG. 4, when error data that does not match the (2, 7) code conversion rule exists in the interleave "3", the error flag is set for the interleave "3" as shown in FIG. Can be set up.

In the error correction circuit 32, the interleave "3" is designated based on the error flag signal from the error flag generation circuit 45, and the data content (pattern) of the interleave "3" is the same interleave "3". It is corrected based on the error correction code.

By thus designating the error position of the data by the error flag generation circuit 45, all the error correction codes for "16" bytes in each interleave are used only for the content (pattern) correction. be able to. So-called erasure correction is possible.

Therefore, it is possible to improve the error correction capability without impairing the effect of high-density recording as an optical disk device and without prolonging the time required for correction as in the case of multiplexing error correction codes. Can be achieved.

Incidentally, for example, the attachment of dust to the optical disc 1 not only damages the data of "1" bytes, but also often adversely affects the data before and after it. Therefore, in a situation in which an error flag is set in three or more interleaves, for example, in a situation in which an error flag is set in the interleaves “1”, “3”, and “4” as shown in FIG. Similarly, all interleaves “0”, “1”, “2”, and “3” are judged based on the judgment that the data may be damaged.
An error flag (actual error flag) is set for "4".

In this case, all interleaves "0"
The data content (pattern) in "1", "2", "3", and "4" is corrected based on the error correction code of each interleave.

On the other hand, as an error that cannot be detected by the (2, 7) code conversion rule, there is an error such as a missing bit due to a defect of the optical disc 1. If this error occurs, the data series will be completely different from the original one.

Therefore, the resync code "RS" that exists for each "15" byte of each data and error correction code.
1 "to" RS39 "are detected by the pattern detection circuit 43, and the time interval of each detected resync code is counted by the error flag generation circuit 45.

For example, if the time interval from the detection of the resync code "RS1" to the detection of the resync code "RS2" is smaller than the reference value, it is determined that the two resync codes are abnormal. An error flag is set for the data between the resync codes “RS1” and “RS2” as shown in FIG.

In this case, the contents (patterns) of all the data between "RS1" and "RS2" are corrected based on the error correction code of each interleave.
As described above, since the error of the data series can be corrected, the error correction capability can be further improved in addition to the correction based on the (2, 7) code conversion rule.

In the above embodiment, the case of performing the (2,7) code conversion has been described as an example, but the same can be applied to the case of performing other code conversion, for example, the (1,7) code conversion. is there. In addition, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention.

[0091]

As described above, according to the present invention, since the designating means for designating the error position of the data is provided and all the error correction codes are used only for the pattern correction, it is possible to improve the performance. The error correction ability can be improved without impairing the effect of density recording and without prolonging the time required for correction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration of the same embodiment.

FIG. 3 is a diagram showing a sector format in the embodiment.

FIG. 4 is a diagram showing a format of each data and each error correction code in the memory in the embodiment.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical display location G11B 7/00 9464-5D G11B 7/00 R

Claims (10)

[Claims] 1. An information processing apparatus for irradiating an information storage medium with a light beam to read information, receives a reflected light beam from the information storage medium, and generates a reproduction signal according to the reflected light beam. Reproducing signal generating means, binarizing means for binarizing the reproducing signal generated from the reproducing signal generating means, and an output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means. Conversion means for converting, demodulation means for demodulating the output of the conversion means based on a predetermined code conversion rule, and data and error correction codes demodulated by the demodulation means are arranged and stored in a matrix form. Storage means for forming a plurality of interleaved columns each having a predetermined number of data and a predetermined number of error correction codes in the array, and the recovery unit of the output of the conversion unit. Specifying means for detecting data that does not match the code conversion rule of the adjusting means, and specifying interleaving in the storage means in which the same data as the detected data exists, and among the respective data in the storage means, the specifying means An information processing apparatus comprising: a correction unit that corrects the content of designated interleaved data based on the same interleaved error correction code. 2. An information processing device for irradiating an information storage medium with a light beam to read information, receives a reflected light beam from the information storage medium, and generates a reproduction signal according to the reflected light beam. Reproducing signal generating means, binarizing means for binarizing the reproducing signal generated from the reproducing signal generating means, and an output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means. Conversion means for converting, demodulation means for demodulating the output of the conversion means based on a predetermined code conversion rule, and data and error correction codes demodulated by the demodulation means are arranged and stored in a matrix form. Storage means for forming a plurality of interleaved columns each having a predetermined number of data and a predetermined number of error correction codes in the array, and the recovery unit of the output of the conversion unit. First specifying means for detecting data that does not match the code conversion rule of the adjusting means, and specifying the interleave in the storage means in which the same data as the detected data exists, and the number of interleaves specified by the first specifying means Is greater than or equal to a predetermined value, second specifying means for specifying all interleaves in the storage means, and the first or second of the respective data in the storage means
An information processing apparatus comprising: a correction unit that corrects the content of interleaved data designated by the designation unit based on an error correction code of the same interleave. 3. An information processing apparatus for irradiating an information storage medium with a light beam to read information, receives a reflected light beam from the information storage medium, and generates a reproduction signal according to the reflected light beam. Reproducing signal generating means, binarizing means for binarizing the reproducing signal generated from the reproducing signal generating means, and an output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means. Conversion means for converting, demodulation means for demodulating the output of the conversion means based on a predetermined code conversion rule, and data and error correction codes demodulated by the demodulation means are arranged and stored in a matrix form. Storage means for forming a plurality of interleaved columns each having a predetermined number of data and a predetermined number of error correction codes in the array, and the recovery unit of the output of the conversion unit. First specifying means for detecting data that does not match the code conversion rule of the adjusting means, and specifying interleave in the storage means in which the same data as the detected data exists; First, the content of the interleaved data designated by the first designating means is corrected based on the same interleaved error correction code.
Correction means, detection means for sequentially detecting a plurality of synchronization signals existing in each data demodulated by the demodulation means, and when there is an abnormality in the time interval of each synchronization signal detected by the detection means, the abnormality A third designating means for designating the data in the storage means corresponding to the period, and the contents of the data designated by the third designating means among the respective data in the storage means are interleaved. An information processing apparatus comprising: a second correction unit that corrects based on an error correction code. 4. An information processing device for irradiating an information storage medium with a light beam to read information, receives a reflected light beam from the information storage medium, and generates a reproduction signal according to the reflected light beam. Reproducing signal generating means, binarizing means for binarizing the reproducing signal generated from the reproducing signal generating means, and an output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means. Conversion means for converting, demodulation means for demodulating the output of the conversion means based on a predetermined code conversion rule, and data and error correction codes demodulated by the demodulation means are arranged and stored in a matrix form. Storage means for forming a plurality of interleaved columns each having a predetermined number of data and a predetermined number of error correction codes in the array, and the recovery unit of the output of the conversion unit. First specifying means for detecting data that does not match the code conversion rule of the adjusting means, and specifying the interleave in the storage means in which the same data as the detected data exists, and the number of interleaves specified by the first specifying means Is greater than or equal to a predetermined value, second specifying means for specifying all interleaves in the storage means, and the first or second of the respective data in the storage means
First correction means for correcting the content of the interleaved data designated by the designating means based on the same interleaved error correction code, and a plurality of synchronization signals existing in each data demodulated by the demodulation means are sequentially detected. And a third designating means for designating data in the storage means corresponding to a period of the abnormality when there is an abnormality in the time interval of each synchronization signal detected by the detection means. A second correction means for correcting the content of the data designated by the third designating means based on the interleave error correction code in which the data exists. apparatus. 5. An information processing apparatus for irradiating an information storage medium with a light beam to read information, receives a reflected light beam from the information storage medium, and generates a reproduction signal according to the reflected light beam. Reproducing signal generating means, binarizing means for binarizing the reproducing signal generated from the reproducing signal generating means, and an output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means. Conversion means for converting, demodulation means for demodulating the output of the conversion means based on a predetermined code conversion rule, and data and error correction codes demodulated by the demodulation means are arranged and stored in a matrix form. Storage means for forming a plurality of interleaved columns each having a predetermined number of data and a predetermined number of error correction codes in the array, and the recovery unit of the output of the conversion unit. First specifying means for detecting data that does not match the code conversion rule of the adjusting means, and specifying the interleave in the storage means in which the same data as the detected data exists, and the number of interleaves specified by the first specifying means Is greater than or equal to a predetermined value, second specifying means for specifying all interleaves in the storage means, and the first or second of the respective data in the storage means
First correction means for correcting the content of the interleaved data designated by the designating means based on the same interleaved error correction code, and a plurality of sync signals existing in each data demodulated by the demodulation means are sequentially detected. Detecting means, an abnormality detecting means for detecting whether or not there is an abnormality in the time interval of each sync signal detected by the detecting means, and when the abnormality detecting means detects an abnormality, the abnormality corresponding to the period of the abnormality. A third designating means for designating data in the storage means, and a content of data designated by the third designating means among the respective data in the storage means, based on an interleave error correction code in which the data exists. An information processing apparatus comprising: a second correcting unit for correcting the image. 6. An information processing device for irradiating an information storage medium with a light beam to read information, receives a reflected light beam from the information storage medium, and generates a reproduction signal according to the reflected light beam. Reproducing signal generating means, binarizing means for binarizing the reproducing signal generated from the reproducing signal generating means, and an output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means. Conversion means for converting, demodulation means for demodulating the output of the conversion means based on a predetermined code conversion rule, and data and error correction codes demodulated by the demodulation means are arranged and stored in a matrix form. Storage means for forming a plurality of interleaved columns each having a predetermined number of data and a predetermined number of error correction codes in the array, and the recovery unit of the output of the conversion unit. Specifying means for detecting data that does not match the code conversion rule of the adjusting means, and issuing an error flag signal for specifying the interleave in the storage means where the same data as the detected data exists, and each data in the storage means An information processing apparatus comprising: a correction unit that corrects the content of interleaved data designated by an error flag signal of the designation unit based on an error correction code of the same interleave. 7. An information processing apparatus for irradiating an information storage medium with a light beam to read information, receives a reflected light beam from the information storage medium, and generates a reproduction signal according to the reflected light beam. Reproducing signal generating means, binarizing means for binarizing the reproducing signal generated from the reproducing signal generating means, and an output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means. Conversion means for converting, demodulation means for demodulating the output of the conversion means based on a predetermined code conversion rule, and data and error correction codes demodulated by the demodulation means are arranged and stored in a matrix form. Storage means for forming a plurality of interleaved columns each having a predetermined number of data and a predetermined number of error correction codes in the array, and the recovery unit of the output of the conversion unit. First specifying means for detecting data that does not match the code conversion rule of the adjusting means, and issuing an error flag signal for specifying the interleave in the storage means in which the same data as the detected data exists, and the first specifying means. Second specifying means for issuing an error flag signal for specifying all the interleaves in the storage means when the number of interleaves specified by the error flag signal is equal to or more than a predetermined value, and each data in the storage means. Of which, the first or second
An information processing apparatus comprising: a correction unit that corrects the content of interleaved data designated by an error flag signal of the designation unit based on an error correction code of the same interleave. 8. An information processing apparatus for irradiating an information storage medium with a light beam to read information, receives a reflected light beam from the information storage medium, and generates a reproduction signal according to the reflected light beam. Reproducing signal generating means, binarizing means for binarizing the reproducing signal generated from the reproducing signal generating means, and an output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means. Conversion means for converting, demodulation means for demodulating the output of the conversion means based on a predetermined code conversion rule, and data and error correction codes demodulated by the demodulation means are arranged and stored in a matrix form. Storage means for forming a plurality of interleaved columns each having a predetermined number of data and a predetermined number of error correction codes in the array, and the recovery unit of the output of the conversion unit. First specifying means for detecting data that does not match the code conversion rule of the adjusting means, and issuing an error flag signal for specifying the interleave in the storage means where the same data as the detected data exists; Of the respective data, the first correction means for correcting the content of the interleaved data designated by the error flag signal of the first designation means based on the same interleaved error correction code, and each demodulated by the demodulation means When there is an abnormality in the detection means for sequentially detecting a plurality of synchronization signals existing in the data and the time interval of each synchronization signal detected by this detection means, the data in the storage means corresponding to the period of the abnormality is detected. Third designating means for issuing an error flag signal for designating, and an error flag of the third designating means among the respective data in the storage means. An information processing device, comprising: a second correction means for correcting the content of the data designated by the error signal based on the interleaved error correction code in which the data exists. 9. An information processing device for irradiating an information storage medium with a light beam to read information, receives a reflected light beam from the information storage medium, and generates a reproduction signal according to the reflected light beam. Reproducing signal generating means, binarizing means for binarizing the reproducing signal generated from the reproducing signal generating means, and an output of the binarizing means into a data sequence synchronized with the reproducing clock signal of the reproducing means. Conversion means for converting, demodulation means for demodulating the output of the conversion means based on a predetermined code conversion rule, and data and error correction codes demodulated by the demodulation means are arranged and stored in a matrix form. Storage means for forming a plurality of interleaved columns each having a predetermined number of data and a predetermined number of error correction codes in the array, and the recovery unit of the output of the conversion unit. First specifying means for detecting data that does not match the code conversion rule of the adjusting means, and issuing an error flag signal for specifying the interleave in the storage means in which the same data as the detected data exists, and the first specifying means. Second specifying means for issuing an error flag signal for specifying all the interleaves in the storage means when the number of interleaves specified by the error flag signal is equal to or more than a predetermined value, and each data in the storage means. Of which, the first or second
First correction means for correcting the content of the interleaved data designated by the error flag signal of the designation means based on the error correction code of the same interleave, and a plurality of synchronization signals existing in each data demodulated by the demodulation means And an error flag signal for designating the data in the storage means corresponding to the period of the abnormality when there is an abnormality in the time interval of each synchronization signal detected by the detecting means. A third designating means to be issued, and of the data in the storage means, the contents of the data designated by the error flag signal of the third designating means are corrected based on the interleaved error correction code in which the data exists. 2. An information processing device comprising: a correction unit. 10. An information processing apparatus for irradiating an information storage medium with a light beam to read information, receives a reflected light beam from the information storage medium, and generates a reproduction signal according to the reflected light beam. Reproducing signal generating means, binarizing means for binarizing the reproducing signal generated from the reproducing signal generating means, and an output of the binarizing means into a data series synchronized with the reproducing clock signal of the reproducing means. Conversion means for converting, demodulation means for demodulating the output of the conversion means based on a predetermined code conversion rule, and data and error correction codes demodulated by the demodulation means are arranged and stored in a matrix form. Of the output of the conversion means, the storage means forming a plurality of interleaved columns each having a predetermined number of data and a predetermined number of error correction codes in the array. First designating means for detecting data that does not match the code conversion rule of the demodulating means, and issuing an error flag signal for designating the interleave in the storage means where the same data as the detected data exists; When the number of interleaves specified by is greater than or equal to a predetermined value, second specifying means for issuing an error flag signal for specifying all interleaving in the storage means; 1 or 2
First correction means for correcting the content of the interleaved data designated by the error flag signal of the designation means based on the error correction code of the same interleave, and a plurality of synchronization signals existing in each data demodulated by the demodulation means Detecting means for sequentially detecting the abnormality, an abnormality detecting means for detecting whether or not there is an abnormality in the time interval of each synchronization signal detected by the detecting means, and a period of the abnormality when the abnormality detecting means detects the abnormality. Of the data designated by the error flag signal of the third designating means among the respective data in the storage means, the third designating means issuing an error flag signal for designating the data in the storage means corresponding to Second correction means for correcting the content based on the interleaved error correction code in which the data exists, The information processing apparatus.