JPH0973795A - Number of significant levels discriminating circuit and associative memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent that an erroneous collated result is outputted and a malfunction is generated in a circuit processing collated results because whether the number of stored word data coinciding with word data for collation becomes a number which is not permitted in a device can not be detected. SOLUTION: All match signals from a associative memory cell array 1 are inputted a circuit and whether the number of match signals expressing that stored word data coincide with word data for collation or are similar to them is of not more or of not less than a prescribed number is discriminated in this circuit. This memory is provided with a multibit detecting circuit 2 outputting the signal MHIT of the discriminated result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a significant level number discriminating circuit for discriminating whether the number of signals having a significant level among a plurality of logic input signals is a predetermined number or more, and such a significant level number discriminating circuit. The present invention relates to an associative memory device using the.

[0002]

2. Description of the Related Art Semiconductor memories are applied to various electronic and electric circuits.
Associative memory is applied instead of AM and ROM.

The associative memory has not only the function of inputting / outputting an address and accessing, but also inputting a data string (word data) to determine whether or not there is stored word data which matches (or is similar to) the address and its address. It has a collating function that can check and output the number and the number in a single cycle (see Reference 1, pp.176-177).

Reference 1 "Takuo Sugano, edited by Tetsuya Iizuka," C
MOS VLSI Design ", Baifukan, April 25, 1989
First edition issued ”In order to have such a collating function, the associative memory cell has a configuration in which the collating function is realized in addition to the SRAM cell configuration as shown in FIG. In FIG. 2, transistors T1 to T6 form a CMOS type SRAM cell, and transistors T7 to T10 are provided to collate the stored information with external input information.

The basic operation as a RAM is basically the same as that of a 6-transistor CMOS type cell. At this time, all the search enable lines are set to the "L" level for access.

On the other hand, in the collating operation, all the word lines are set to the "L" level, the search enable line and the match line are set to the "H" level, and the bit line pair B to be searched.
Data for collation is input to L and BL / (indicated by an overline in the drawing, and in this specification, "/" is added to the end of the code for convenience of notation). The bit line pair BL, BL / corresponding to the bit not to be searched (masked) is kept at the “H” level.

In the detected bit (associative memory cell), if the stored data does not match the matching data, the potential of the match line is changed from the "H" level to the "L" level by the "L" level side of the bit line pair. Withdrawn. For example, if the matching data is “0” and the storage data is “1”, the bit line BL side is at the “L” level in the situation where the transistor T8 is in the ON state due to the storage data “1”. The potential of the match line is pulled down by the "L" level of the bit line BL via the transistor T7 which is on by the search enable line and the transistor T8 which is on based on the stored data. On the other hand, if the verification data is "1" and the stored data is "0", the bit line BL / side is at the "L" level in the state where the transistor T9 is in the ON state, and therefore the transistor T9 is in the on state.
Through 9 and T10, the potential of the match line is pulled down by the "L" level of this bit line BL /.

Therefore, in all of the associative memory cells of each bit connected to the same match line corresponding to the word,
Only when the stored data and the matching data match, the match line is kept at the “H” level, and even one of the associative memory cells related to the word has the stored data and the matching data. If they do not match, the match line changes to "L" level.

Various functions are added to the peripheral circuit of the associative memory according to the requirements of the application system. For example, there is an associative memory device including a peripheral circuit having a function as described in Document 2.

Reference 2 "Ogura et al.," 4 Kb CMOS Associative Memory LSI ", Technical Report, SSD85-78, 19
1983, pp.45-52 "The associative memory device (associative memory L
SI) is provided with a peripheral circuit which sequentially outputs a plurality of matched word information to the encoder as an address.

However, although it is possible to realize a circuit that selects and separates a plurality of pieces of word information, the application system (peripheral circuit) ensures that the number of pieces of word information for matching is 1 or less. Controlled content addressable memory devices are common.

[0012]

However, in such an associative memory device in which the number of pieces of word information for which matching is to be performed is controlled to be a predetermined number (for example, one) or less, a bug in such a control configuration is caused. Therefore, there may be a case where the number of pieces of word information for matching exceeds the number. However, conventionally, there has been a case where the associative memory device malfunctions and an incorrect final output is sent without the provision of a countermeasure structure for such a case.

[0013]

In order to solve such a problem, according to the first aspect of the present invention, when the matching word data is input to the associative memory cell array, the stored word data matches or is similar to the matching word data. In the associative memory device that outputs from the associative memory cell array a match signal corresponding to each stored word data indicating whether or not the match word data is input, the stored word data matches or is similar to the matching word data. It is characterized by comprising a multi-hit detection circuit for discriminating whether the number of match signals indicating that the number is equal to or less than a predetermined number and outputting the discrimination result signal.

By providing such a multi-hit detection circuit, it is possible to detect that the number of stored word data that matches the matching word data is not permitted by the apparatus, and an incorrect matching result is output. It is possible to prevent the occurrence of malfunction or malfunction of the circuit that processes the matching result.

A second aspect of the present invention relates to a significant level number discriminating circuit which can be used in the multi-hit detecting circuit of the first aspect of the present invention. That is, among n (n is an integer of 2 or more) logical input signals, the number of signals having a significant level is m (m is a natural number).
The present invention relates to a significant level number discrimination circuit that determines whether or not the following.

The significant level number discriminating circuit of the second invention is
Each of the first and second terminals are commonly connected, and n first transistors having the same characteristics to which any corresponding logic input signal is input to the control terminal, and a predetermined potential to the control terminal. And a second transistor to which is applied, the parallel circuit of the n first transistors and the second transistor are connected so as to form a differential amplification pair of the differential amplification circuit, and n Of the current flowing through the parallel circuit of the first transistor and the current flowing through the second transistor when the number of the first transistors of the number m of n or less is ON, and when the number of the first transistors is larger than that. The characteristics of each first transistor and the characteristics of the second transistor are selected so as to be opposite when the first transistor is turned on, and the current flowing through the parallel circuit of the n first transistors is Second Characterized by delivering a potential corresponding to the difference between the current flowing through the transistor as an output signal.

Of n (n is an integer of 2 or more) logical input signals, the number of significant level discriminating circuits for determining whether the number of signals having a significant level is m (m is a natural number) or less is m or less. It is possible to simply consider a realization configuration by providing a logic circuit for detection of each combination of the logical input signals that becomes, and a logic circuit that collects the outputs of the above-described logic circuits in the number of combinations. However, although the structure is complicated and large in size, the significant level number discriminating circuit according to the second aspect of the present invention can be realized with a simple structure having a small number of elements.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

(A) First Embodiment Hereinafter, a first embodiment of the associative memory device according to the present invention will be described in detail with reference to the drawings.

Here, FIG. 1 is a block diagram showing a main part configuration of the associative memory device of the first embodiment. Although FIG. 1 shows an associative memory device having a structure of 4 words × 3 bits, this is for convenience of description, and an associative memory device having a structure of m words × n bits (m, n: positive integer) is shown. Of course, it is okay.

In FIG. 1, this associative memory device comprises an associative memory cell array 1 and a multi-hit detection circuit (significance level number discrimination circuit) 2.

The associative memory cell array 1 is constructed by arranging, for example, 12 associative memory cells CAM00 to CAM32 having the internal structure shown in FIG. 2 in 4 rows and 3 columns (the search enable line is shown in FIG. 1). Is omitted). Associative memory cells CAM00 to CAM in each row connected to the same word line WORD0, ..., WORD3
02, CAM10 to CAM12, CAM20 to CAM2
2. CAM30 to CAM32 are units for storing word data (3-bit data). Associative memory cells CAM00 to CAM02, CA of each row connected to the same word line WORD0, ..., WORD3.
M10-CAM12, CAM20-CAM22, CAM
Stored word data of 30 to CAM32 and three bit line pairs BL0 and BL0 /, BL1 and BL1 /, BL2
And the matching result with the matching word data given to BL2 /, as described above, match lines MATCH0-MA
Appears at TCH3 logic level. Each match line MATCH
0, ..., MATCH 3 are “1” level (hereinafter, referred to as “hit” when the stored word data and the matching word data match (hereinafter, matching is referred to as hit)). 2), and takes "0" level (note that it is referred to as "H" level in FIG. 2) when they do not match.

These match lines MATCH0 to MATCH
3 is connected to the multi-hit detection circuit 2. The associative memory device of the first embodiment is controlled by a peripheral circuit (not shown) at the time of writing so that the number of pieces of word information for matching is always one or less.

The multi-hit detection circuit 2 takes one logic level ("0" level) when the number of match lines taking "1" level indicating a match is 1 or less and sets the "1" level indicating a match. Output signal MHIT which takes the other logic level (“1” level) when the number of match lines to be taken is 2 or more
Is formed and output.

That is, the multi-hit detection circuit 2 generates an error in a processing unit (not shown) for processing the matched word data when there is a number of matching word data that cannot guarantee that the associative memory device operates normally. For forming the output signal MHIT.

FIG. 3 is a block diagram showing the detailed structure of the multi-hit detection circuit 2 of the first embodiment. Further, FIG. 4 is a chart (truth table) showing the logic level in each part of the multi-hit detection circuit 2.

In FIG. 3, the multi-hit detection circuit 2
Is provided in an associative memory device having a four-word structure, and is therefore composed of four inverters 11 to 14, five 4-input NOR gates 21 to 25, and one 5-input NOR gate 31. ing. Note that, for example, the multi-hit detection circuit 2 in an associative memory device having an 8-word structure includes eight inverters, nine 8-input NOR gates, and one 9-input NOR gate.

All the match lines MA are connected to the NOR gate 21.
The logic levels of TCH0 to MATCH3 are input as they are, and the NOR gate 21 obtains their NOR outputs and gives them to the NOR gate 31. Therefore, the output from the NOR gate 21 takes the "1" level only when the logic levels of all the match lines MATCH0 to MATCH3 take the "0" level as shown in FIG. .

The NOR gate 22 has a match line MATCH.
The logic level of 0 is inverted and input through the inverter 11, and the other match lines MATCH1 to MATC
The logic level of H3 is input as it is, and the NOR gate 22
Obtain their NOR output and provide them to the NOR gate 31.
Therefore, the output from the NOR gate 22 takes the "1" level, as is clear from FIG.
The logical level of CH0 takes "1" level indicating the coincidence,
Further, it is only when the logic levels of the other match lines MATCH1 to MATCH3 are "0" level indicating the mismatch.

The NOR gate 23 has a match line MATCH.
The logic level of 1 is inverted and input through the inverter 12, and the other match lines MATCH0 and MATC
The logic levels of H2 and MATCH3 are input as they are,
The NOR gate 23 obtains those NOR outputs and gives them to the NOR gate 31. Therefore, it is clear from FIG. 4 that the output from the NOR gate 23 takes the "1" level.
"1" indicating that the match line MATCH1 logic level is coincident
Take a level and match other match lines MATCH0, MA
This is only when the logical levels of TCH2 and MATCH3 are "0", which indicates a mismatch.

The NOR gate 24 has a match line MATCH.
The logic level of 2 is inverted and input through the inverter 13, and the other match lines MATCH0 and MATC
The logic levels of H1 and MATCH3 are input as they are,
The NOR gate 24 obtains those NOR outputs and supplies them to the NOR gate 31. Therefore, it is clear from FIG. 4 that the output from the NOR gate 24 takes the "1" level.
"1" indicating that the match line MATCH2 has a matching logic level
Take a level and match other match lines MATCH0, MA
This is only when the logical levels of TCH1 and MATCH3 take the "0" level indicating a mismatch.

The NOR gate 25 has a match line MATCH.
3 is inverted and input via the inverter 14, and the other match lines MATCH0 to MATC
The logic level of H2 is input as it is, and NOR gate 25
Obtain their NOR output and provide them to the NOR gate 31.
Therefore, the output from the NOR gate 25 takes the "1" level, as is clear from FIG.
The logical level of CH3 takes "1" level, which indicates coincidence,
In addition, it is only when the logic levels of the other match lines MATCH0 to MATCH2 take "0" level indicating a mismatch.

The NOR gate 31 of the output stage to which the output signals of the NOR gates 21 to 25 are input obtains the NOR outputs thereof and outputs them as the output signal MHIT from the circuit 2 to the circuit of the subsequent stage. NOR gates 21 and 2 which take "1" level only under different conditions as described above
Since the output signal from the No. 5 is given, the signal from the NOR gate 31 takes a significant "0" level, as is apparent from FIG. 4, only from one of the NOR gates 21, ..., 25. Is only output.

That is, in the multi-hit detection circuit 2, when all the match lines show a mismatch, the NOR gate 21 takes out and only one match line shows a match.
, 25 are taken out respectively and the cases where the outputs of these NOR gates 21 to 25 are significant are put together by the NOR gate 31, so that the number of match lines having "1" level indicating a match is 1 or less. In the case of 1, the output signal MHIT takes one "0" level and takes "1" level to indicate a match and the number of match lines is two or more.

As described above, according to the associative memory device of the first embodiment, since the multi-hit detection circuit 2 is provided, if the operation at the time of writing or the collation is normal, there is one match. Even if there is more than one word information to be viewed, this abnormality can be detected by the multi-hit detection circuit, and it is possible to prevent erroneous collation results from being output or malfunctions in the circuit that processes collation results. Become.

(B) Second Embodiment Next, a second embodiment of the associative memory device according to the present invention will be described in detail with reference to the drawings.

The associative memory device of the second embodiment is
The detailed configuration of the multi-hit detection circuit (significance level number discrimination circuit) 2 is different from that of the associative memory device of the first embodiment. Therefore, in the second embodiment, the multi-hit detection circuit 2 will be described. Note that FIG.
6 is a circuit diagram showing a detailed configuration of a multi-hit detection circuit 2 of the second embodiment.

This multi-hit detection circuit 2 conceptually uses the so-called sense amplifier structure of the differential amplifier structure having a current mirror type load as described on pages 186 to 189 of Document 1 above. It was done by.

In FIG. 5, the multi-hit detection circuit 2 includes two PMOS transistors T11 and T12.
And six NMOS transistors T13 to T18.

The NMOS transistors T13 to T16 are connected in parallel. That is, each transistor T1
The sources of 3, ..., T16 are commonly connected, and the drains thereof are also commonly connected. However, the gates of the transistors T13, ..., T16 are connected to different match lines MATCH0 ,. That is, the drain current of the parallel circuit as a whole changes in accordance with the number of match lines taking the "L" level.

When such a parallel circuit of the transistors T13 to T16 is viewed as one transistor, the NMOS transistor T17 forming a differential amplification pair with this transistor has a drain current of the parallel circuit of the transistors T13 to T16. A reference drain current for comparison is made to flow, and its gate is connected to the power supply voltage (Vdd).

Transistors T1 forming a parallel circuit
, ..., T16 have equivalent characteristics. The characteristics of the transistors T13, ..., T16 are as follows:
It is defined to satisfy the following relationship with the characteristic of the transistor T17 that sets the comparison standard.

That is, each of the transistors T13, ..., T
When the on-resistance of 16 is R0 and the on-resistance of the transistor T17 is Rref, its characteristics are determined so as to satisfy R0>Rref> R0 / 2 (1).

In other words, the four transistors T13
In the case where one or less transistors are on in T16 to T16, the combined resistance of the parallel circuits of these transistors T13 to T16 is larger than the on resistance of the transistor T17, and conversely, among the four transistors T13 to T16, The ON resistances R0 and Rref are set so that the combined resistance of the parallel circuit of the transistors T13 to T16 becomes smaller than the ON resistance of the transistor T17 when the number of transistors that are on is two or more. In other words, when the number of transistors that are on is one or less among the four transistors T13 to T16, the sum of the drain currents of the parallel circuits of these transistors T13 to T16 is smaller than the drain current of the transistor T17. ,
On the contrary, when two or more transistors among the four transistors T13 to T16 are turned on, the sum of the drain currents of the parallel circuits of the transistors T13 to T16 becomes larger than the drain current of the transistor T17. Thus, the on-resistances R0 and Rref are defined.

When the relationship between the on-resistances R0 and Rref is set by selecting the transistor size, for example, the following relationship may be satisfied.

That is, each of the transistors T13, ..., T
When the gate length of 16 and the gate length of the transistor T17 are made equal, each of the transistors T13, ..., T16
The gate width of W0 and the gate width of the transistor T17 is W
If ref is set, the gate widths W0 and Wref may be selected so as to satisfy W0 <Wref <2 · W0 (2).

The transistor T18, whose drains are commonly connected to the sources of the transistors T13 to T16 and the source of the transistor T17, detects the multi-hit according to the sense enable signal ΦSE applied to its gate. It controls execution and non-execution of the operation of the circuit 2, and at the time of operation, it functions as a constant current source that controls the source potentials of the transistors T13 to T16 and the source potential of the transistor T17.

Two PMOS transistors T11 and T
Reference numeral 12 has a source connected to the second power supply voltage, a gate commonly connected, and a drain of the transistor T11 connected to a common gate to form a current mirror type load. Also, the transistor T
The drain of 11 is connected to the drains of the transistors T13 to T16, and the drain of the transistor T12 is connected to the drain of the transistor T17. Here, the transistors T11 and T12 are designed to have equivalent characteristics.

The potential of the connection point of the transistors T12 and T17 is used as the output signal MHIT.

In the multi-hit detection circuit 2 of the second embodiment having the above-mentioned configuration, the gate of the transistor T12 is set so that the transistors T11 and T12 forming the current mirror type load flow equal drain currents. Is also biased, while transistors T13-
Since the combined drain current of the parallel circuit of T16 and the reference drain current of the transistor T17 do not match, the potential of the connection point of the transistors T12 and T17 (M
HIT) changes depending on the magnitude relationship between the combined drain current and the reference drain current, and is amplified to the logic level.

That is, when the potential obtained by amplifying the current difference is obtained and the combined drain current is smaller than the reference drain current, the output signal MHIT takes the "L" level, and the combined drain current is higher than the reference drain current. When it is larger, the output signal MHIT takes the "H" level.

Here, at the time of matching, if there is no stored word data that matches the matching word data (when the number of hits is 0), all match lines MAT.
CH0 to MATCH3 are at the “L” level, the drain current does not flow in the transistors T13 to T16, and the drain current flows only in the transistor T17.
The potential of HIT becomes "L" level.

Further, at the time of matching, when there is only one stored word data that matches the matching word data (when the number of hits is 1), only one match line (MATCH0 here) is used. Is at "H" level, the other match lines MATCH1 to MATCH3 are at "L" level. In this case, the drain current flows through the transistors T13 and T17, but as shown in the above equation (1), the on-resistance Rref of the transistor T17 is set to be smaller than the on-resistance R0 of the transistor T13. The drain current flowing through T17 is larger than the drain current flowing through the transistor T13 (parallel circuit of the transistors T13 to T16), and as a result, the potential of the output signal MHIT becomes "L" level.

On the other hand, at the time of matching, when there are two or more pieces of stored word data that match the matching word data (when the number of hits is two or more), two or more match lines (MATCH0 to MATCH2 in this case). Becomes "H" level, and the other match line MATCH3 becomes "L" level. In this case, the transistors T13-
A drain current flows through T15, and each transistor T13,
The drain current flowing through each of T15 is ...
Due to the relationship (1), it is smaller than the drain current flowing through the transistor T17, but since the transistors T13 to T15 are connected in parallel, the combined drain current is smaller than the drain current flowing through the transistor T17 because of the relationship (1) above. As a result, the output signal MHIT becomes "H" level.

Therefore, since the multi-hit detection circuit 2 is provided also in the associative memory device of the second embodiment, if the operation at the time of writing or the collation is normal, there is only one word information for matching. Even if a plurality of occurrences occur, such an abnormality can be detected by the multi-hit detection circuit, and it is possible to prevent an incorrect collation result from being output or a malfunction in a circuit that processes the collation result.

Further, according to the associative memory device of the second embodiment, the multi-hit detection circuit is configured by utilizing the so-called sense amplifier configuration of the differential amplifier configuration having the current mirror type load. Compared with the device of the first embodiment, the number of elements can be reduced and high-speed operation can be expected.

For example, in FIG. 3, each inverter is composed of two normal transistors, the four-input NOR gate is composed of eight normal transistors, and the five-input NOR gate is composed of ten normal transistors. The multi-hit detection circuit of the first embodiment requires 58 transistors. On the other hand, the multi-hit detection circuit of the second embodiment is composed of eight transistors, as shown in FIG. As the number of words that can be stored and the number of bits per word increase, the difference in the number of required elements becomes even greater.

Further, in the multi-hit detection circuit of the first embodiment, since the output signal MHIT is formed from the logic level of the match line via the logic gates of three stages, the transmission delay of each logic gate and the like can be prevented. Affected output signal MHIT
It takes a long time to change effectively. On the other hand, in the multi-hit detection circuit of the second embodiment, the output signal MHIT changes effectively as soon as a difference appears in the drain currents of the transistors (one of which is a parallel circuit) of the differential amplification pair. The time required for the change is shorter than that of the multi-hit detection circuit of the first embodiment. It should be noted that as the number of words that can be stored and the number of bits per word increase, the fan-out number and fan-in number of each logic gate in the first embodiment also increase, so the transmission delay in each stage becomes even larger. Therefore, the difference in the changing speed from the second embodiment becomes larger and larger.

Furthermore, since the load is the current mirror load, the amplification factor can be increased and the transistors T13 to T1 can be increased.
Even in a situation where the difference between the current flowing through 6 and the current flowing through the transistor T17 is small (for example, when the number of hits is 1), it can be amplified to a sufficient level as the logical level of the output signal.

Further, the sense amplifier structure having the current mirror type load is generally adopted for the sense amplifier of the bit line pair, and the manufacturing process (etching etc.) for realizing this multi-hit detection circuit on a semiconductor is as follows. This can be done at the same time as the manufacturing process of the bit line pair sense amplifier.

The PMOS transistors T11 and T
When the common gate of 12 is connected not to the drain side of the transistors T13 to T16 but to the drain side of the transistor T17 and the output is taken from the drain side of the transistors T13 to T16 (see the right half of FIG. 6). (See the configuration), the output signal of the inverted logic level compared with the above-mentioned output signal MHIT, that is, the output signal (MH) which takes the “L” level when the number of hits is too large.
IT /) can be obtained.

(C) Third Embodiment Next, an associative memory device according to a third embodiment obtained by partially modifying the above-described second embodiment will be described.

The structure of the main part of the associative memory device of the third embodiment is also as shown in FIG. 1 described above, and the detailed structure of the multi-hit detection circuit 2 is the second embodiment in terms of a circuit diagram. It is as shown in FIG.

However, the second embodiment is different from the transistors T13 to T16 in the multi-hit detection circuit 2 in that
The characteristic relationship with the transistor T17 is different.

That is, in the third embodiment, the on-resistance R0 of each of the transistors T13, ..., T16.
And the on-resistance Rref of the transistor T17 have a relationship that satisfies R0 / 2>Rref> R0 / 3 (3). In other words, among the four transistors T13 to T16, when the number of transistors that are on is two or less, these transistors T13 to T16
When the sum of the drain currents in the entire parallel circuit of 16 (combined drain current) is smaller than the drain current of the transistor T17, and conversely, among the four transistors T13 to T16, three or more transistors are on. , The sum of the combined drain currents of these transistors T13 to T16 is
The on resistances R0 and Rref are set so as to be larger than the drain current of the transistor T17.

When the relation between the ON resistances R0 and Rref is set by selecting the transistor size, for example, the following relation may be satisfied.

That is, each of the transistors T13, ..., T
When the gate length of 16 and the gate length of the transistor T17 are made equal, each of the transistors T13, ..., T16
Gate width W0 of the transistor T17 and the gate width Wref of the transistor T17
It is sufficient that the relation 2 · W0 <Wref <3 · W0 (4) holds.

As described above, the transistors T13 to T1
6 and the characteristic relationship between the transistor T17 and the transistor T17 have been selected, the detailed operation will not be described. However, at the time of verification, when the number of stored word data matching the verification word data is two or less, the transistors T13 to T16 are When the combined drain current becomes smaller than the drain current of the transistor T17, the potential of the output signal MHIT becomes the “L” level, and when there are three or more stored word data items that match the matching word data item, the transistors T13 to T16 are combined. The drain current becomes larger than the drain current of the transistor T17, and the potential of the output signal MHIT becomes "H" level.

That is, in the multi-hit detection circuit 2 of the third embodiment, it is possible to form the output signal MHIT which discriminates the case where the number of hits is 2 or less and the case where the number of hits is 3 or more.

Therefore, according to the third embodiment, in the associative memory device in which the storage number of the same word data is allowed up to 2, it is possible to detect the abnormality of the collation result in which the hit number is 3 or more. . The effect except this point is the same as the effect of the second embodiment.

Incidentally, in order to extend the technical idea of the multi-hit detection circuit 2 of the first embodiment, for example, when the number of hits is 2 or less and when the number of hits is 3 or more, the output signal is When trying to change the logic level of MHIT, the number of match line combinations when the number of hits is 2 (6)
Only 4-input NOR gates are additionally required, and two inverters are required on the input side of each of these NOR gates, resulting in a very large-scale configuration.

As is clear from the description of the second and third embodiments, the relationship between the characteristics of the transistors T13 to T16 and the characteristics of the transistor T17 (Equation (1) or (3)) should be selected appropriately. Thereby, the boundary of the number of hits for changing the logic level of the output signal MHIT can be arbitrarily set by the configuration shown in FIG.

(D) Fourth Embodiment Next, a second embodiment of the associative memory device according to the present invention will be described in detail with reference to the drawings.

The associative memory device of the fourth embodiment is also
The detailed configuration of the multi-hit detection circuit (significance level number discrimination circuit) 2 is different from that of the associative memory device of the first embodiment. FIG. 6 is a circuit diagram showing a detailed configuration of the multi-hit detection circuit 2 of the fourth embodiment. The same or corresponding portions as those of FIG. 5 according to the second embodiment are designated by the same or corresponding reference numerals. Shows.

In the multi-hit detection circuit 2 of the fourth embodiment, as is apparent from the comparison between FIGS. 5 and 6, two so-called sense amplifier configurations of a differential amplifier configuration having a current mirror type load are symmetrical. It is arranged and configured.

That is, the transistors T11 to T17 forming the multi-hit detection circuit of the second embodiment,
In addition to T180, a sense amplifier configuration having a current mirror type load composed of transistors T11a to T17a having substantially the same connection relationship is provided. Note that the transistor T180 is commonly provided in two sense amplifier configurations.

However, in the newly added sense amplifier configuration on the right side of FIG. 6, the common gates of the PMOS transistors T11a and T12a forming the current mirror type load are connected to the drain of the transistor T17a through which the reference drain current flows. are doing. The output signal MHI is output from the connection point of the transistors T12a and T17a.
I try to take out T /.

Therefore, like the sense amplifier configuration on the left side of FIG. 6, the sense amplifier configuration on the right side of FIG. 6 operates similarly to the multi-bit detection circuit of the second embodiment, and the transistors of the sense amplifier configuration on the left side are operated. The output signal MHIT similar to that of the multi-bit detection circuit of the second embodiment is obtained from the connection point of T12 and T17, and the connection point of the transistors T12a and T17a having the sense amplifier configuration on the right side is obtained from the connection point of the second embodiment. Output signal MHIT obtained by inverting the logic level of the output signal MHIT of the multi-bit detection circuit of
Get /.

As described above, according to the fourth embodiment, the complementary signals MHIT and MHIT / can be obtained as the output signals for switching the logic level depending on whether or not the number of hits is less than the predetermined number. A configuration for processing complementary inputs can be applied as a circuit portion for processing output signals.

In addition to this effect, it goes without saying that the effect of the second embodiment described above can be obtained. Although the number of transistors is increased from 8 to 15 as compared with the second embodiment, the number is significantly smaller than 58 in the multi-bit detection circuit of the first embodiment.

Incidentally, the complementary output signal can be obtained even with the configuration shown in FIG. That is, the other output signal may be taken out from the connection point between the common drain of the transistors T13 to T16 and the drain of the transistor T1. However, since the load is a current mirror load, changes in both output signals are not balanced, and it is preferable to obtain a complementary output signal according to the fourth embodiment.

(E) Fifth Embodiment Next, a fifth embodiment of the associative memory device according to the present invention will be described in detail with reference to the drawings.

The associative memory device of the fifth embodiment also has
The detailed configuration of the multi-hit detection circuit (significance level number discrimination circuit) 2 is different from that of the associative memory device of the first embodiment. FIG. 7 is a circuit diagram showing a detailed configuration of the multi-hit detection circuit 2 of the fifth embodiment. The same or corresponding portions as those of FIG. 5 according to the second embodiment are designated by the same or corresponding reference numerals. Shows.

The multi-hit detection circuit 2 according to the fifth embodiment has the second hit, as is clear from the comparison between FIG. 5 and FIG.
Further on the output side of the multi-hit detection circuit of the embodiment of
It is configured by arranging a sense amplifier configuration having a current mirror type load.

That is, in addition to the transistors T11 to T18 forming the multi-hit detection circuit of the second embodiment, a sense amplifier structure having a current mirror type load composed of transistors T21 to T25 is provided.

One of the NMOS transistors T23 and T24 forming a differential amplification pair in this sense amplifier configuration has a gate of the transistor T23 which is formed by the transistors T13 to T13.
The gate of the other transistor T24, which is connected to the connection point CA between the common drain of T16 and the drain of the transistor T11, and which forms a differential amplification pair, has the gate of the transistor T1.
7 is connected to the connection point CB between the drain of the transistor T12 and the drain of the transistor T12. Here, the transistor T23
, And T24 are designed to have equivalent characteristics.

These pair of transistors T23 and T2
NMOS whose drain is connected to the common source of 4
The transistor T25 is a constant current source that controls the execution or non-execution of the operation of the sense amplifier configuration according to the sense enable signal ΦSE applied to the gate, and at the time of operation, controls the source potentials of the transistors T23 and T24. It works.

Two PMOS transistors T21 and T
22 has a source connected to the second power supply voltage, a gate connected in common, and a drain of the transistor T21 connected to the common gate to form a current mirror type load. The drain of the transistor T21 is connected to the drain of the transistor T23, and the drain of the transistor T22 is connected to the drain of the transistor T24. Here, the transistors T21 and T22 are designed to have equivalent characteristics.

The potential of the connection point of the transistors T22 and T24 is used as the output signal MHIT /.

The same components as those of the multi-hit detection circuit of the second embodiment operate in the same manner as described in the second embodiment. However, note the following points. As described in the second embodiment, the potential of the connection point CB between the drain of the transistor T17 and the drain of the transistor T12 takes the "L" level when the number of hits is one or less, and the number of hits is two. In the above case, it takes the "H" level.
On the other hand, the potential of the connection point CA between the common drain of the transistors T13 to T16 and the drain of the transistor T11 is
The drain voltage of the transistor T11 is the transistor T1.
Since the gates of 1 and T12 are biased, they are not in equilibrium with the potential of the connection point CB.
Contrary to the potential of, the "H" level is set when the number of hits is one or less, and the "L" level is set when the number of hits is two or more.

While unbalanced, such a difference between the pair of complementary changing potentials is differentially amplified by the sense amplifier configuration having the current mirror type load composed of the transistors T21 to T25, and as a result, the transistor T22 and At the connection point of T24, an output signal (potential) MHIT / which takes the "H" level when the number of hits is one or less and takes the "L" level when the number of hits is two or more is obtained.

As described above, since the sense amplifier structure having the current mirror type load is cascade-connected in two stages, the difference between the output signals of the first stage (potentials at the connection points CA and CB) changes sufficiently. Even if not done, the output signal (potential) MHIT / sufficient as the logic level can be obtained from the sense amplifier configuration of the second stage by the amplification operation even if the level change in the first stage is in the middle.

That is, according to the fifth embodiment,
It can be expected that the multi-hit detection circuit 2 that can operate at a higher speed than the second embodiment is realized.

In addition to this effect, it goes without saying that the effect of the second embodiment described above can be obtained. Although the number of transistors is increased from 8 to 13 as compared with the second embodiment, the number is significantly smaller than 58 in the multi-bit detection circuit of the first embodiment.

(F) Other Embodiments (1) In the multi-hit detection circuit 2 of the second to fifth embodiments, the load in the differential amplifier circuit is a current mirror type load. It may be a general load simply connected in series to the transistors (T13 to T16 and T17) forming the dynamic amplification pair.

(2) The transistors in the multi-hit detection circuit 2 of the second to fifth embodiments are not limited to MOS transistors, and other unipolar transistors may be applied, or bipolar transistors are applied. Is also good. Further, the N-type and P-type are not limited to those of the embodiment.

(3) Of course, the amplifier circuit as in the fifth embodiment may be provided on the output side of the multi-hit detection circuit of the fourth embodiment. Further, the amplifier circuit provided on the output side is not limited to the sense amplifier configuration having the current mirror type load, including the fifth embodiment.

(4) It goes without saying that the technical idea of the third embodiment may be introduced into the multi-hit detection circuit 2 of the fourth and fifth embodiments. That is, the upper limit of the number of detected hits can be set arbitrarily.

(5) The configurations of the multi-hit detection circuit in the second to fifth embodiments are useful even when applied to other than the associative memory device. That is, it is useful as a significant level number discriminating circuit for discriminating whether or not the number of signals having a significant level is n or less (m is a natural number) among n (n is an integer of 2 or more) logical input signals. .

[0099]

As described above, according to the associative memory device of the first aspect of the present invention, all match signals are input, and the match word indicating that the stored word data matches or is similar to the matching word data. Since the multi-hit detection circuit that determines whether the number of signals is less than or equal to a predetermined number and outputs the determination result signal, the device allows the number of stored word data that matches the matching word data. It is possible to detect that the number has not reached, and prevent an incorrect collation result from being output or a malfunction in a circuit that processes the collation result.

According to the significant level number discriminating circuit of the second aspect of the present invention, each of the first and second terminals is connected in common, and any corresponding logical input signal is input to the control terminal. A differential amplifier circuit is configured by using n first transistors having the same characteristics and a second transistor to which a predetermined potential is applied to the control terminal as a differential amplifier pair, and the n first transistors are connected in parallel. The magnitude relation between the current flowing through the circuit and the current flowing through the second transistor is such that when m or less first transistors of the n transistors are turned on, and when a larger number of the first transistors are turned on. The characteristics of each first transistor and the second
The characteristics of the transistor are selected and the potential corresponding to the difference between the current flowing through the parallel circuit of the n first transistors and the current flowing through the second transistor is transmitted as an output signal. Among n (n is an integer of 2 or more) logical input signals, an output signal indicating whether or not the number of signals having a significant level is m (m is a natural number) or less can be formed by a simple configuration with a small number of elements. .

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a main part of a first embodiment.

FIG. 2 is a circuit diagram showing an associative memory cell configuration.

FIG. 3 is a block diagram showing a configuration of a multi-hit detection circuit of the first embodiment.

FIG. 4 is a table showing a truth value of each unit of the multi-hit detection circuit according to the first embodiment.

FIG. 5 is a circuit diagram showing a configuration of a multi-hit detection circuit according to a second embodiment.

FIG. 6 is a circuit diagram showing a configuration of a multi-hit detection circuit according to a fourth embodiment.

FIG. 7 is a circuit diagram showing a configuration of a multi-hit detection circuit according to a fifth embodiment.

[Explanation of symbols]

1 ... Associative memory cell array, 2 ... Multi-hit detection circuit (significance level number discrimination circuit) 11-14 ... Inverter,
21-25, 31 ... NOR gate, T11-T18, T1
1a to T17a, T180, T21 to T25 ... Transistors.

Claims (7)

[Claims] 1. A significant level number discriminating circuit for determining whether or not the number of signals having a significant level among n (n is an integer of 2 or more) logical input signals is m (m is a natural number) or less. , N first transistors having the same characteristics, in which the respective first terminals are connected to each other and the second terminals are connected to each other, and any corresponding logical input signal is input to the control terminal, and the control terminal A second transistor to which a predetermined potential is applied, and a parallel circuit of the n first transistors and the second transistor.
Is connected to form a differential amplifier pair of a differential amplifier circuit, and a magnitude relation between a current flowing through a parallel circuit of the n first transistors and a current flowing through the second transistor. However, each of the first first transistors is turned on when m or less of the n first transistors are turned on and when the first transistors of a larger number are turned on.
The characteristics of the second transistor and the characteristics of the second transistor are selected, and a potential corresponding to the difference between the current flowing through the parallel circuit of the n first transistors and the current flowing through the second transistor is output. A significant level number discriminating circuit characterized by being transmitted as a signal. 2. The load between the parallel circuit of the n first transistors and the second transistor, which constitutes the differential amplifier pair, is a current mirror type load. The significant level number discrimination circuit described in. 3. A differential amplifier circuit having n parallel circuits of the first transistors and a differential amplifier pair of the second transistors is symmetrically provided, and complementary output signals are transmitted. The significant level number discriminating circuit according to claim 2. 4. An amplifier circuit for amplifying an output signal from the differential amplifier circuit is further provided.
5. The significant level number discriminating circuit according to any one of 3 to 3. 5. The significant level number discriminating circuit according to claim 4, wherein the amplifier circuit in the output stage is a current mirror type sense amplifier. 6. When the matching word data is input to the associative memory cell array, a match signal corresponding to each storage word data indicating whether or not the storage word data matches or is similar to the matching word data, In the associative memory device that outputs from the associative memory cell array, all match signals are input, and the number of match signals indicating that the stored word data matches or is similar to the matching word data is equal to or less than a predetermined number. An associative memory device comprising a multi-hit detection circuit that determines whether or not the result is output. 7. The associative memory device according to claim 6, wherein the significance level number discrimination circuit according to any one of claims 1 to 5 is applied as the multi-hit detection circuit.