JPH0974193A - Silicon carbide semiconductor device - Google Patents

Abstract

(57) Abstract: A silicon carbide semiconductor device having high breakdown voltage, low loss, low threshold voltage, and low leak current is provided. An n ⁺ -type silicon carbide semiconductor substrate 1, an n ⁻ -type silicon carbide semiconductor layer 2 and a p-type silicon carbide semiconductor layer 3 are sequentially laminated. An n ⁺ type source region 4 is formed in a predetermined region of the surface layer portion in the p type silicon carbide semiconductor layer 3, and a groove 6 penetrates both the n ⁺ type source region 4 and the p type silicon carbide semiconductor layer 3 to form n.
^- it has reached the -type silicon carbide semiconductor layer 2. The n ⁺ -type source region 4, the p-type silicon carbide semiconductor layer 3, and the n-type source region 4 on the side surface of the trench 6 are formed.
^An n-type silicon carbide semiconductor thin film layer 7 is provided on the surface of the -type silicon carbide semiconductor layer 2. A gate electrode layer 9 is arranged in the trench 6 with a gate insulating film 8 interposed therebetween. Surface of p-type silicon carbide semiconductor layer 3 and low resistance p-type silicon carbide region 5
A source electrode layer 11 is formed on the surface of, and a drain electrode layer 12 is formed on the surface of the n ⁺ type silicon carbide semiconductor substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device, for example, an insulated gate field effect transistor, and more particularly to a vertical MOSFET for high power.

[0002]

2. Description of the Related Art Recently, a vertical power MOSF manufactured using a silicon carbide single crystal material as a power transistor has been developed.
ET is proposed. In order to reduce the loss of the power transistor, it is necessary to reduce the on-resistance, and as an element capable of effectively reducing the on-resistance, the trench gate type power MOSFET shown in FIG. 13 (for example, Japanese Patent Laid-Open No. 4-23977).
No. 8) has been proposed. The trench gate type power MOSFET in FIG. 13 is an n-type silicon carbide semiconductor substrate 21.
An n-type epitaxial layer 22 is formed on the n-type epitaxial layer 22.
P-type epitaxial layer 23 on the epitaxial layer 22.
And an n-type source region 24 is formed in a predetermined region of the p-type epitaxial layer 23. Further, a recess 25 penetrating the n-type source region 24 and the p-type epitaxial layer 23 to reach the n-type epitaxial layer 22 is formed, and a gate electrode 27 is formed in the recess 25 via a gate insulating film 26. ing. An insulating film 28 is formed on the upper surface of the gate electrode 27, a source electrode film 29 is formed on the n-type source region 24 including the insulating film 28, and a drain electrode film is formed on the surface of the n-type silicon carbide semiconductor substrate 21. 30 is formed.

Here, in the channel through which carriers flow between the source terminal and the drain terminal, a voltage is applied to the gate electrode 27, and the gate is sandwiched between the gate electrode 27 and the p-type epitaxial layer 23 on the side wall of the recess 25. An electric field is applied to the insulating film 26 to invert the conductivity type of the p-type epitaxial layer 23 in contact with the gate insulating film 26.

Further, a vertical power MO for inducing a channel in the accumulation mode shown in FIG. 14 is shown as an element capable of reducing the on-resistance, which is manufactured by using a silicon carbide single crystal material.
An SFET (US Pat. No. 5,323,040) has been proposed. The vertical power MOSFET in FIG. 14 is configured as follows. N ⁺ type drain region 33 is formed on first surface 32a of silicon carbide semiconductor substrate 31, and n type silicon carbide semiconductor drift region 34 is formed inward of n ⁺ type drain region 33. An n ⁺ type source region 35 is formed on second surface 32b of silicon carbide semiconductor substrate 31, and this n ⁺ type source region 35 and the aforementioned n
An n ⁻ type silicon carbide semiconductor channel region 36 is formed between the type silicon carbide semiconductor drift region 34 and the n ⁻ type silicon carbide semiconductor channel region 36. Further, a trench 37 reaching n-type silicon carbide semiconductor drift region 34 is formed on second surface 32b of silicon carbide semiconductor substrate 31, and mesa including n ⁺ type source region 35 and n ⁻ type silicon carbide semiconductor channel region 36 is formed. A region 38 is formed. An insulating film 39 is formed along the side surface 37a of the trench 37 and the bottom surface 37b of the trench 37. A gate electrode 40 is formed in the trench 37. n ⁺
A source electrode 41 and a drain electrode 42 are formed in the type source region 35 and the n ⁺ type drain region 33, respectively.

Here, for carrier conduction between the source terminal and the drain terminal, a positive voltage is applied to the gate electrode 40,
^- type trench side 3 of the silicon carbide semiconductor channel region 36
This is done by forming the n-type storage layer channel 43 in the vicinity of 7a. The work function of the gate electrode 40, the impurity concentration of the n ⁻ -type silicon carbide semiconductor channel region 36, and the width W of the mesa region 38 are designed so that the mesa region 38 is depleted when no voltage is applied to the gate electrode 40. Therefore, when a voltage is not applied to the gate electrode 40 or a negative voltage is applied, carrier conduction between the source terminal and the drain terminal is less likely to occur.

As described above, the vertical power MO shown in FIG.
In the SFET, the threshold voltage is lowered by inducing in the channel accumulation mode, and the unit cell 43 is downsized (the width W of the mesa region 38 is reduced to about 2 μm) to increase the degree of integration and reduce the on-resistance. ing.

[0007]

However, as shown in FIG.
In the trench gate type power MOSFET shown in FIG. 3, the impurity concentration of the region where the channel is formed is p type epitaxial layer 2
It was defined by the impurity concentration of 3. as a result,
The following problems will occur. One of the parameters for determining the source-drain breakdown voltage of the power MOSFET having the structure shown in FIG. 13 is the impurity concentration N _A of the p-type epitaxial layer 23 and the thickness a sandwiched between the source region 24 and the n-type epitaxial layer 22. Is. The source-drain breakdown voltage is governed by the avalanche condition of the pn junction between the p-type epitaxial layer 23 and the n-type epitaxial layer 22 and the condition that the p-type epitaxial layer 23 is depleted and punch-through occurs. Therefore, the impurity concentration N _A of the p-type epitaxial layer 23 must be sufficiently high and the thickness a must be sufficiently thick. However, when the impurity concentration N _A of the p-type epitaxial layer 23 is increased, there is a problem that the gate threshold voltage is increased, and the impurity mobility is increased, so that the channel mobility is decreased and the on-resistance is increased. Further, when the thickness a is increased, the channel length becomes longer, and there is a problem that the on-resistance increases.

As described above, in order to realize a power MOSFET having a high breakdown voltage, a small current loss during operation, and a low threshold voltage, it is necessary to independently control the impurity concentrations of the p-type epitaxial layer and the region where the channel is formed. However, it was difficult with the conventional structure.

As one of means for solving the above problems,
Groove gate type power MOSFE using silicon single crystal
At T, the concentration of the channel forming layer is reduced by the thermal diffusion method. However, in the trench gate type power MOSFET using silicon carbide, there is a new problem that the thermal diffusion method cannot be used because the thermal diffusion constant of impurity atoms in silicon carbide is extremely small.

Further, the vertical power MOSFET shown in FIG.
In, the device breakdown depends on the isolation of the trench bottom.
Since it is determined by the breakdown voltage of the edge film, the avalanche blur of the pn junction
Smaller breakdown strength than an element whose breakdown voltage is determined by breakdown
There was a problem. Also, when the transistor is off
Under high temperature conditions,⁺Mold source region 35 to n ^-
Of majority carriers to the silicon carbide semiconductor channel region 36
Supply occurs, and source-drain leakage current is large
There was a problem.

Therefore, an object of the present invention is to provide a silicon carbide semiconductor device having high breakdown voltage, low loss, low threshold voltage, and low leak current.

[0012]

According to a first aspect of the present invention, there are provided a first conductivity type low resistance semiconductor layer, a first conductivity type high resistance semiconductor layer, and a second conductivity type first semiconductor layer. A semiconductor substrate made of single-crystal silicon carbide, which is formed by stacking in order, a first-conductivity-type semiconductor region formed in a predetermined region of a surface layer portion of the first semiconductor layer, the semiconductor region, and the semiconductor region. A groove that penetrates the first semiconductor layer and reaches the high-resistance semiconductor layer, a semiconductor region on a side surface of the groove, the semiconductor region, a surface of the first semiconductor layer and the high-resistance semiconductor layer, and a silicon carbide thin film. A first conductive type second semiconductor layer, a gate insulating film formed on the surface of the second semiconductor layer in the groove, and a gate formed inside the gate insulating film in the groove An electrode layer, a surface of the first semiconductor layer and A first electrode layer formed on at least a part of the surface of the semiconductor region among a part of the surface of the semiconductor region, and a second electrode layer formed on the surface of the low resistance semiconductor layer. A silicon carbide semiconductor device is also the subject.

According to a second aspect of the present invention, there is provided a silicon carbide semiconductor device in which the crystal type of the second semiconductor layer in the first aspect of the invention is the same as that of the first semiconductor layer. Use as a summary.

According to a third aspect of the present invention, there is provided the first or second aspect.
The gist of the invention is a silicon carbide semiconductor device in which the semiconductor substrate and the second semiconductor layer in the invention described in (3) are made of hexagonal silicon carbide.

According to a fourth aspect of the present invention, in the semiconductor substrate according to any one of the first to third aspects, the surface of the substrate on which the semiconductor region is formed is approximately (000).
1) The gist is a silicon carbide semiconductor device having a carbon surface.

According to a fifth aspect of the invention, in the invention according to any one of the first to fourth aspects, the impurity concentration of the second semiconductor layer is such that the low resistance semiconductor layer and the semiconductor region have the same impurity concentration. A lower silicon carbide semiconductor device will be the gist. (Operation) According to the invention described in claim 1, by applying a voltage to the gate electrode layer (gate terminal) to apply an electric field to the gate insulating film, a storage channel is induced in the second semiconductor layer. , Carriers flow between the first electrode layer (source terminal) and the second electrode layer (drain terminal). That is, the second semiconductor layer serves as a channel formation region.

In this way, the MOSFET operation mode is
By setting the accumulation mode that induces the channel without inverting the conductivity type of the channel formation layer, the MOSFET can be operated at a lower gate voltage as compared with the MOSFET of the inversion mode that inverts the conductivity type and induces the channel. In addition, channel mobility can be increased, and a silicon carbide semiconductor device with low current loss and low threshold voltage can be obtained. Further, by independently controlling the impurity concentration of the first semiconductor layer (body layer) and the impurity concentration of the second semiconductor layer in which the channel is formed, high breakdown voltage, low current loss, and low threshold voltage silicon carbide are obtained. A semiconductor device is obtained. That is, the source-drain breakdown voltage is mainly controlled by the impurity concentration of the high resistance semiconductor layer and its film thickness, the impurity concentration of the first semiconductor layer, and the distance L sandwiched between the high resistance semiconductor layer and the semiconductor region. Therefore, the impurity concentration of the first semiconductor layer can be increased and the distance L sandwiched between the high resistance semiconductor layer and the semiconductor region can be shortened. The distance L between the high resistance semiconductor layer and the semiconductor region is almost equal to the channel length. In this way, the channel length can be shortened while maintaining high withstand voltage, and as a result, a silicon carbide semiconductor device with high withstand voltage and low current loss can be obtained. Further, by lowering the impurity concentration of the second semiconductor layer in which a channel is formed, the influence of impurity scattering when carriers flow can be reduced, so that the channel mobility can be increased and, as a result, A silicon carbide semiconductor device having high breakdown voltage and low current loss can be obtained.

Further, since the first semiconductor layer and the second semiconductor layer in which the channel is formed may be made of silicon carbide having a different crystal type, carriers may be used in the crystal type of the second semiconductor layer in which the channel is formed. A silicon carbide semiconductor device with low current loss can be obtained by using a crystal type whose mobility in the flowing direction is larger than that of the first semiconductor layer.

Further, the source / drain current control when no gate voltage is applied is performed by expanding the depletion layer of the pn junction formed by the body layer, that is, the first semiconductor layer and the channel forming layer, that is, the second semiconductor layer. The normally-off characteristic is achieved by completely depleting the second semiconductor layer.

Since the body layer, that is, the first semiconductor layer and the drift layer, that is, the high-resistance semiconductor layer, form a pn junction, the breakdown voltage of the device depends on the avalanche of the pn junction between the body layer whose potential is fixed to the source electrode and the drift layer. Since it can be designed so as to be determined by breakdown, the breakdown resistance can be increased.

Further, the impurity concentration of the second semiconductor layer forming the channel is low, and further, by making the film thickness thin, the leak current between the source and drain can be made small even under high temperature conditions. You can

According to the invention of claim 2, according to claim 1,
In addition to the effect of the invention described in (1), the crystal type of the second semiconductor layer is the same as the crystal type of the first semiconductor layer, so that the structure of the present invention can be easily formed.

According to the third aspect of the present invention, the first aspect is provided.
Alternatively, in addition to the effect of the invention described in 2, the semiconductor substrate and the second semiconductor layer are made of hexagonal silicon carbide, which is more preferable.

According to the invention of claim 4, claim 1
In addition to the effect of the invention described in any one of 1 to 3, since the surface of the semiconductor substrate is a substantially (0001) carbon surface, the high breakdown voltage structure can be easily formed.

According to the invention of claim 5, claim 1
In addition to the action of the invention described in any one of to 4, the impurity concentration of the second semiconductor layer is lower than the impurity concentrations of the low resistance semiconductor layer and the semiconductor region, so that the channel resistance can be reduced.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows n in the present embodiment.
The sectional view of a channel type groove gate type power MOSFET (vertical type power MOSFET) is shown.

Hexagonal system silicon carbide is used for n ⁺ type silicon carbide semiconductor substrate 1 as the low resistance semiconductor layer. On this n ⁺ type silicon carbide semiconductor substrate 1, an n ⁻ type silicon carbide semiconductor layer 2 as a high resistance semiconductor layer and a p type silicon carbide semiconductor layer 3 as a first semiconductor layer are sequentially laminated.

Thus, the n ⁺ type silicon carbide semiconductor substrate 1
And n ⁻ -type silicon carbide semiconductor layer 2 and p-type silicon carbide semiconductor layer 3
The semiconductor substrate 13 made of single crystal silicon carbide is constituted by and the upper surface of the semiconductor substrate 13 is a substantially (0001) carbon surface.

An n ⁺ type source region 4 as a semiconductor region is formed in a predetermined region in the surface layer portion of p type silicon carbide semiconductor layer 3. Further, p-type silicon carbide semiconductor layer 3
A low resistance p-type silicon carbide region 5 is formed in a predetermined region on the outer peripheral side of the n ⁺ -type source region 4 in the inner surface layer portion.

A groove 6 is formed at a predetermined position of the n ⁺ type source region 4.
The trench 6 penetrates the n ⁺ type source region 4 and the p type silicon carbide semiconductor layer 3 to reach the n ⁻ type silicon carbide semiconductor layer 2. The groove 6 has a side surface 6 a perpendicular to the surface of the semiconductor substrate 13 and a bottom surface 6 b parallel to the surface of the semiconductor substrate 13.

On the surface of the n ⁺ type source region 4, the p type silicon carbide semiconductor layer 3 and the n ⁻ type silicon carbide semiconductor layer 2 on the side surface 6a of the groove 6, an n type silicon carbide semiconductor thin film as a second semiconductor layer is formed. Layer 7 is extended. The n-type silicon carbide semiconductor thin film layer 7 is a thin film having a thickness of about 1000 to 5000 Å, which is thinner than the width W = 2 μm of the mesa region 38 in the device shown in FIG. The crystal type of the n-type silicon carbide semiconductor thin film layer 7 is the same as that of the p-type silicon carbide semiconductor layer 3, and is 6H—SiC, for example. In addition, 4H-SiC or 3C-SiC may be used. The impurity concentration of n-type silicon carbide semiconductor thin film layer 7 is lower than the impurity concentrations of n ⁺ -type silicon carbide semiconductor substrate 1 and n ⁺ -type source region 4.

Further, a gate insulating film 8 is formed on the surface of the n-type silicon carbide semiconductor thin film layer 7 in the groove 6 and the bottom surface 6b of the groove 6. A gate electrode layer 9 is filled inside the gate insulating film 8 in the trench 6. Gate electrode layer 9 is covered with insulating film 10. Source electrode layer 11 as a first electrode layer is formed on the surface of n ⁺ type source region 4 and the surface of low resistance p type silicon carbide region 5. n ⁺
A drain electrode layer 12 as a second electrode layer is formed on the front surface (back surface of the semiconductor substrate 13) of the silicon carbide semiconductor substrate 1.

The operation of this trench gate type power MOSFET is as follows. By applying a positive voltage to the gate electrode layer 9, a storage type channel is induced in the n-type silicon carbide semiconductor thin film layer 7, and the source electrode layer 11 and the drain are formed. Carriers flow to and from the electrode layer 12. That is, the n-type silicon carbide semiconductor thin film layer 7 becomes the channel formation region.

As described above, by setting the accumulation mode for inducing the channel as the MOSFET operation mode, the MOS in the inversion mode for inverting the conductivity type to induce the channel.
Compared with the FET, the MOSFET can be operated with a lower gate voltage, the channel mobility can be increased, and the threshold voltage becomes low with low current loss. or,
Source / drain current control when no gate voltage is applied is p
Formed by the n-type silicon carbide semiconductor thin film layer 7 (channel forming layer) and the n-type silicon carbide semiconductor layer 3 (body layer)
This is performed by expanding the depletion layer of the junction. The normally-off characteristic can be achieved by completely depleting the n-type silicon carbide semiconductor thin film layer 7. Further, since the p-type silicon carbide semiconductor layer 3 (body layer) and the n ⁻ -type silicon carbide semiconductor layer 2 (drift layer) form a pn junction, the breakdown voltage of the element is a p-type silicon carbide semiconductor layer fixed to the source electrode. Since it can be designed to be determined by the avalanche breakdown of the pn junction between the n ^- type silicon carbide semiconductor layer 2 and the n ⁻ type silicon carbide semiconductor layer 2, the breakdown resistance can be increased.

Further, by independently controlling the impurity concentration of p-type silicon carbide semiconductor layer 3 and the impurity concentration of n-type silicon carbide semiconductor thin film layer 7, a MOSFET having a high withstand voltage, low current loss and low threshold voltage can be obtained. . In particular, by lowering the impurity concentration of the n-type silicon carbide semiconductor thin film layer 7 forming the channel,
The influence of impurity scattering when carriers flow is reduced,
Channel mobility can be increased. Since the source-drain breakdown voltage is mainly controlled by the impurity concentration of the n ⁻ type silicon carbide semiconductor layer 2 and the p type silicon carbide semiconductor layer 3 and its film thickness, the impurity concentration of the p type silicon carbide semiconductor layer 3 is increased. Thus, the distance L sandwiched between the high resistance semiconductor layer and the semiconductor region can be shortened, and the channel length can be shortened while maintaining high withstand voltage. Therefore, the channel resistance can be dramatically reduced, and the on-resistance between the source and drain can be reduced.

Next, the manufacturing process of the trench gate type power MOSFET will be described with reference to FIGS. First, as shown in FIG. 2, an n ⁺ -type silicon carbide semiconductor substrate 1 is prepared, an n ⁻ -type silicon carbide semiconductor layer 2 is epitaxially grown on the surface of the n ⁻ -type silicon carbide semiconductor layer 2, and a p-type carbon carbide semiconductor layer 2 is further formed on the n ⁻ -type silicon carbide semiconductor layer 2. The silicon semiconductor layer 3 is epitaxially grown. Thus, semiconductor substrate 13 formed of n ⁺ type silicon carbide semiconductor substrate 1, n ⁻ type silicon carbide semiconductor layer 2 and p type silicon carbide semiconductor layer 3 is formed.

Next, as shown in FIG.
In a predetermined region of the surface portion of the conductor layer 3, n ⁺Mold source area 4
Are formed by, for example, ion implantation of nitrogen. further,
A low resistance is applied to another predetermined region of the surface layer portion of the p-type silicon carbide semiconductor layer 3.
The anti-p-type silicon carbide region 5 is formed by, for example, aluminum ions.
It is formed by injection.

Then, as shown in FIG. 4, n ⁻ -type source region 4 and p-type silicon carbide semiconductor layer 3 are penetrated together to form n ^{− −.}
Groove 6 reaching type silicon carbide semiconductor layer 2 is formed. Further, as shown in FIG. 5, n-type silicon carbide semiconductor thin film layer 7 is formed on side surface 6 a of groove 6. That is, the n ⁺ type silicon carbide semiconductor thin film layer 7 extending to the surfaces of the n ⁺ type source region 4, the p type silicon carbide semiconductor layer 3 and the n ⁻ type silicon carbide semiconductor layer 2 on the inner wall of the groove 6 is formed. Here, the impurity concentration of n-type silicon carbide semiconductor thin film layer 7 on trench side surface 6a is set lower than the impurity concentrations of n ⁺ -type silicon carbide semiconductor substrate 1 and n ⁺ -type source region 4. A more specific method for forming the n-type silicon carbide semiconductor thin film layer 7 is 6H-S by the CVD method.
A 6H—SiC thin film layer 7 is homoepitaxially grown on iC.

Subsequently, as shown in FIG. 6, gate insulating film 8 is formed on the surfaces of semiconductor substrate 13 and n-type silicon carbide semiconductor thin film layer 7 and on bottom surface 6b of trench 6. Then, as shown in FIG. 7, the gate electrode layer 9 is filled inside the gate insulating film 8 in the trench 6. Further, as shown in FIG. 8, the insulating film 10 is formed on the upper surface of the gate electrode layer 9. Then, FIG.
As shown in, the source electrode layer 11 is formed on the source region 4 including the insulating film 10 and the low resistance p-type silicon carbide region 5. Further, the drain electrode layer 12 is formed on the surface of the n ⁺ type silicon carbide semiconductor substrate 1 to form the trench gate type power MOSF.
Complete the ET.

As described above, in the present embodiment, the n-type silicon carbide semiconductor thin film layer 7 is arranged on the side surface 6a of the groove 6, and the gate electrode is formed on the n-type silicon carbide semiconductor thin film layer 7 via the gate insulating film 8. Since the layer 9 is provided, the n-type silicon carbide semiconductor thin film layer 7 serving as the channel forming region is formed as the p-type silicon carbide semiconductor layer 3
The concentration can be adjusted independently, and the threshold voltage can be lowered with high breakdown voltage and low current loss. Further, the impurity concentration of the n-type silicon carbide semiconductor thin film layer 7 forming the channel is low, and by further reducing the film thickness to about 1000 to 5000Å,
Even under high temperature conditions, the leak current between the source and drain can be reduced.

In addition to the configuration described above, for example, n
^The source electrodes formed in the ⁺ type source region 4 and the low resistance p type silicon carbide region 5 may be made of different materials. Also, low resistance p
The type silicon carbide region 5 can be omitted. In this case, the source electrode layer 11 is formed so as to contact the n ⁺ type source region 4 and the p type silicon carbide semiconductor layer 3. Also, the source electrode layer 11
Need only be formed on at least the surface of the n ⁺ type source region 4.

Further, in the above-mentioned example, the case where the invention is applied to the n-channel vertical MOSFET is explained, but FIG.
P-channel vertical MO with p-type and n-type interchanged
The same effect can be obtained in the SFET.

Further, in FIG. 1, the side surface 6a of the groove 6 is 90 ° with respect to the substrate surface, but as shown in FIG. 9, the angle between the side surface 6a of the groove 6 and the substrate surface is not always 9 °.
It need not be 0 °. Further, the groove 6 may be V-shaped without a bottom surface.

It should be noted that the angle formed between the side surface of the groove 6 and the surface of the substrate 13 is designed so that the channel mobility is large, so that a better effect can be obtained. Further, as shown in FIG. 10, the upper portion of the gate electrode layer 9 may have a shape extending above the n ⁺ type source region 4. With this configuration,
The connection resistance between n ⁺ type source region 4 and the channel induced in n type silicon carbide semiconductor thin film layer 7 can be reduced.

Further, as shown in FIG. 11, the thickness of gate insulating film 8 is substantially equal at the central portion and the lower end of n-type silicon carbide semiconductor thin film layer 7 in which a channel is formed, and at the same time n-type silicon carbide semiconductor thin film is formed. The structure may be such that the gate electrode layer 9 extends below the lower end of the layer 7. With this configuration, n
The connection resistance between the channel and the drain region induced in the silicon carbide semiconductor thin film layer 7 can be reduced.

Further, it may be carried out as shown in FIG. That is, as shown in FIG. 10, the upper part of gate electrode layer 9 has a shape extending above n ⁺ type source region 4, and as shown in FIG. 11, the lower end of n type silicon carbide semiconductor thin film layer 7 is formed. The structure may be such that the gate gate electrode layer 9 extends further down.

The n-type silicon carbide semiconductor thin film layer 7 and the p-type silicon carbide semiconductor layer 3 may have different crystal types.
The p-type silicon carbide semiconductor layer 3 is made of SiC of 6H and the n-type silicon carbide semiconductor thin film layer 7 is made of SiC of 4H to increase the mobility in the direction in which carriers flow to reduce MO current with low current loss.
SFET is obtained.

Needless to say, modifications are included without departing from the spirit of the present invention.

[0049]

As described above in detail, according to the present invention,
An excellent effect that a device having high withstand voltage, low loss, low threshold voltage, and low leak current can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional structure diagram of an n-channel groove type SiC MOSFET for explaining an embodiment.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of an n-channel groove type SiC MOSFET.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of an n-channel groove type SiC MOSFET.

FIG. 4 is a sectional view for explaining a manufacturing process of the n-channel groove type SiC MOSFET.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of the n-channel groove type SiC MOSFET.

FIG. 6 is a sectional view for explaining a manufacturing process of the n-channel groove type SiC MOSFET.

FIG. 7 is a sectional view for explaining a manufacturing process of the n-channel groove type SiC MOSFET.

FIG. 8 is a cross-sectional view for explaining the manufacturing process of the n-channel groove type SiC MOSFET.

FIG. 9 is an n-channel groove type Si for explaining an application example.
Schematic sectional view of a C-MOSFET.

FIG. 10 is an n-channel groove type S for explaining an application example.
Schematic sectional view of an iC-MOSFET.

FIG. 11 is an n-channel groove type S for explaining an application example.
Schematic sectional view of an iC-MOSFET.

FIG. 12 is an n-channel groove type S for explaining an application example.
Schematic sectional view of an iC-MOSFET.

FIG. 13: Conventional silicon carbide trench gate type power MOSF
Schematic diagram of the cross-sectional structure of ET.

FIG. 14 is a schematic cross-sectional structure diagram of a conventional silicon carbide vertical power MOSFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n ^<+> type | mold silicon carbide semiconductor substrate as a low resistance semiconductor layer, 2 ... n < ^- > type | mold silicon carbide semiconductor layer as a high resistance semiconductor layer, 3 ... p type silicon carbide semiconductor layer as a 1st semiconductor layer, 4 ... N ⁺ type source region as a semiconductor region, 6 ...
Groove, 6a ... Side surface, 6b ... Bottom surface, 7 ... N-type silicon carbide semiconductor thin film layer as second semiconductor layer, 8 ... Gate insulating film, 9
... gate electrode layer, 11 ... source electrode layer as first electrode layer, 12 ... drain electrode layer as second electrode layer, 1
3 ... Semiconductor substrate

Claims (5)

[Claims] 1. A single-crystal silicon carbide, which is formed by sequentially laminating a low-resistance semiconductor layer of a first conductivity type, a high-resistance semiconductor layer of a first conductivity type, and a first semiconductor layer of a second conductivity type. A semiconductor substrate made of: a semiconductor region of a first conductivity type formed in a predetermined region of a surface layer portion in the first semiconductor layer; the high-resistance semiconductor layer penetrating the semiconductor region and the first semiconductor layer; And a second conductivity type second semiconductor layer formed of a silicon carbide thin film and extending on the surfaces of the semiconductor region, the first semiconductor layer and the high resistance semiconductor layer on the side surface of the groove. A gate insulating film formed on at least the surface of the second semiconductor layer in the groove, a gate electrode layer formed inside the gate insulating film in the groove, and a surface of the first semiconductor layer And a part of the surface of the semiconductor region Of the silicon carbide, a first electrode layer formed on at least a part of the surface of the semiconductor region, and a second electrode layer formed on the surface of the low-resistance semiconductor layer. Semiconductor device. 2. The silicon carbide semiconductor device according to claim 1, wherein the crystal type of the second semiconductor layer is the same as the crystal type of the first semiconductor layer. 3. The silicon carbide semiconductor device according to claim 1, wherein the semiconductor substrate and the second semiconductor layer are made of hexagonal silicon carbide. 4. The silicon carbide semiconductor device according to claim 1, wherein the substrate surface of the semiconductor substrate on which the semiconductor region is formed has a substantially (0001) carbon surface. 5. The silicon carbide according to claim 1, wherein the impurity concentration of the second semiconductor layer is lower than the impurity concentrations of the low resistance semiconductor layer and the semiconductor region. Semiconductor device.