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JPH0990420A - Active matrix liquid crystal display device - Google Patents

Active matrix liquid crystal display device

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Publication number
JPH0990420A
JPH0990420A JP24910495A JP24910495A JPH0990420A JP H0990420 A JPH0990420 A JP H0990420A JP 24910495 A JP24910495 A JP 24910495A JP 24910495 A JP24910495 A JP 24910495A JP H0990420 A JPH0990420 A JP H0990420A
Authority
JP
Japan
Prior art keywords
active matrix
line
liquid crystal
display device
scanning line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24910495A
Other languages
Japanese (ja)
Other versions
JP3593391B2 (en
Inventor
Yasuyuki Hanazawa
康行 花澤
Tetsuya Iizuka
哲也 飯塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Development and Engineering Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP24910495A priority Critical patent/JP3593391B2/en
Publication of JPH0990420A publication Critical patent/JPH0990420A/en
Application granted granted Critical
Publication of JP3593391B2 publication Critical patent/JP3593391B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

(57)【要約】 【課題】 TFTを用いるアクティブマトリクス基板の
開口率向上を図ると共に、蓄積容量の安定化を図り、表
示不良を防止し、表示品位の向上を図る事を目的とす
る。 【解決手段】 走査線30の幅を最小加工限度寸法と
し、蓄積容量線13を最少加工限度寸法の間隙12を有
して走査線30に近接して設け、走査線30及び蓄積容
量線13の一部を接続部13aにて接続する。更に蓄積
容量線13上方にて一側43aが間隙12内に位置する
よう画素電極43をパターン形成する。
An object of the present invention is to improve the aperture ratio of an active matrix substrate using TFTs, stabilize the storage capacitance, prevent display defects, and improve display quality. A width of a scanning line 30 is set as a minimum processing limit size, and a storage capacitance line 13 is provided close to the scanning line 30 with a gap 12 having a minimum processing limit size. A part is connected at the connecting portion 13a. Further, the pixel electrode 43 is patterned so that one side 43 a is located in the gap 12 above the storage capacitance line 13.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、マトリクス状に配列さ
れた薄膜トランジスタ(以下TFTと略称する。)を駆
動素子として備えたアクティブマトリクス基板及び対向
基板との間に、液晶組成物を保持して成るアクティブマ
トリクス型液晶表示装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention holds a liquid crystal composition between an active matrix substrate provided with thin film transistors (hereinafter abbreviated as TFT) arranged in a matrix as driving elements and a counter substrate. And an active matrix type liquid crystal display device.

【0002】[0002]

【従来の技術】近年、高密度且つ大容量でありながら高
機能更には高精細を得る液晶表示装置の実用化が図られ
ている。
2. Description of the Related Art In recent years, a liquid crystal display device which has a high density and a large capacity but has a high function and a high definition has been put into practical use.

【0003】これ等液晶表示装置のうち、隣接する画素
間のクロストークが無く、高コントラスト表示を得られ
ると共に、透過型表示が可能であり且つ、大面積化も容
易である等の理由から、従来よりTFTを制御素子とし
て備えたアクティブマトリクス型の液晶表示装置が多用
されている。
Of these liquid crystal display devices, there is no crosstalk between adjacent pixels, a high contrast display can be obtained, a transmissive display is possible, and a large area can be easily obtained. Conventionally, an active matrix type liquid crystal display device including a TFT as a control element has been widely used.

【0004】そして、液晶表示装置に用いるアクティブ
マトリクス基板のうち、蓄積容量線を、走査線及びゲー
ト電極と同じ材質を用い、同じ形成工程にて一緒にパタ
ーン形成が成されるものにあっては、従来、図4に示す
第1の従来例の様な構造とされていた。
Among the active matrix substrates used for the liquid crystal display device, the ones in which the storage capacitor lines are made of the same material as the scanning lines and the gate electrodes and are patterned together in the same forming process are not used. Conventionally, the structure is the same as that of the first conventional example shown in FIG.

【0005】即ち、アクティブマトリクス基板1の絶縁
基板上には、走査線2及び信号線3の交差部に設けられ
るTFT4のソース電極4aに接続される画素電極6が
マトリクス状にパターン形成され、更に画素電極6の下
方には走査線2と同一工程にてパターン形成される遮光
部材からなる蓄積容量線7がパターン形成されており、
ゲート絶縁膜を介し、画素電極6との間で補助容量を形
成している。
That is, on the insulating substrate of the active matrix substrate 1, pixel electrodes 6 connected to the source electrodes 4a of the TFTs 4 provided at the intersections of the scanning lines 2 and the signal lines 3 are patterned in a matrix pattern, and further, Below the pixel electrode 6, a storage capacitor line 7 made of a light shielding member is patterned in the same process as the scanning line 2 is formed.
An auxiliary capacitance is formed between the pixel electrode 6 and the gate insulating film.

【0006】しかしながらこの様なアクティブマトリク
ス基板1にあっては、蓄積容量線7が画素電極6のほぼ
中央を横切る様に形成されており、この蓄積容量線7に
より画素電極6中の遮光面積が増大される事から、開口
率が低減されてしまっていた。従ってこの様なアクティ
ブマトリクス基板を液晶表示装置に用いた場合、表示さ
れた画面輝度が低下されてしまい、所要の輝度を得よう
とすると、バックライトの光量を上げなければ成らず、
その為の消費電力が増大され、装置の省エネルギー化が
妨げられるという問題を生じていた。
However, in such an active matrix substrate 1, the storage capacitance line 7 is formed so as to cross substantially the center of the pixel electrode 6, and the light storage area in the pixel electrode 6 is formed by the storage capacitance line 7. Since it is increased, the aperture ratio has been reduced. Therefore, when such an active matrix substrate is used in a liquid crystal display device, the displayed screen brightness is lowered, and in order to obtain the required brightness, the light amount of the backlight must be increased,
Therefore, there has been a problem that power consumption is increased and energy saving of the device is hindered.

【0007】このため、走査線と独立した蓄積容量線を
設けるのでは無く、図5に示す第2の従来例の様に、走
査線8の一部を蓄積容量線として作用させ、ゲート絶縁
膜を介し、走査線8及び画素電極9との重なり部分10
で補助容量を形成するアクテイブマトリクス基板11の
開発も成されている。
Therefore, instead of providing a storage capacitance line independent of the scanning line, as in the second conventional example shown in FIG. 5, a part of the scanning line 8 is made to act as a storage capacitance line, and the gate insulating film is formed. The overlapping portion 10 with the scanning line 8 and the pixel electrode 9
The active matrix substrate 11 that forms the auxiliary capacitance is also developed.

【0008】[0008]

【発明が解決しようとする課題】従来、TFTを駆動素
子とするアクティブマトリクス基板を用いた透過型の液
晶表示装置にあっては、走査線から独立した、画素電極
のほぼ中央を横切る位置に蓄積容量線を設け、画素電極
との重なり部分で補助容量を形成したり或いは、走査線
の一部を蓄積容量線とし、画素電極と走査線との重なり
部分で補助容量を形成していた。
Conventionally, in a transmissive liquid crystal display device using an active matrix substrate having a TFT as a driving element, accumulation is made at a position which is independent of a scanning line and crosses substantially the center of a pixel electrode. A capacitance line is provided and an auxiliary capacitance is formed at the overlapping portion with the pixel electrode, or a part of the scanning line is used as a storage capacitance line, and the auxiliary capacitance is formed at the overlapping portion between the pixel electrode and the scanning line.

【0009】このため前者にあっては、画素電極中の光
透過面積が低減され、ひいては液晶表示装置の開口率が
低減され、必要な画面輝度を得られず、バックライトの
光量を上昇しなければならず、省エネルギー化が妨げら
れるという問題を生じていた。
Therefore, in the former case, the light transmission area in the pixel electrode is reduced, the aperture ratio of the liquid crystal display device is reduced, the required screen brightness cannot be obtained, and the light amount of the backlight must be increased. Therefore, there was a problem that energy saving was hindered.

【0010】一方、後者にあっては、走査線の一部が蓄
積容量線を兼用する事から、画素電極を横切る蓄積容量
線を無くす事が出来、アクティブマトリクス基板の開口
率向上を図れるものの、補助容量が、画素電極端部にて
走査線との重なり部分で形成される事から、製造時に走
査線と画素電極のパターンの重ね合わせにずれを生じる
と、画素電極と走査線との重なり面積が変動する事か
ら、蓄積容量の大きさが大きく変化してしまっていた。
On the other hand, in the latter, since a part of the scanning line also serves as the storage capacitance line, the storage capacitance line which crosses the pixel electrode can be eliminated, and the aperture ratio of the active matrix substrate can be improved. Since the auxiliary capacitance is formed at the end portion of the pixel electrode that overlaps the scanning line, if there is a misalignment in the pattern of the scanning line and the pixel electrode during manufacturing, the overlapping area between the pixel electrode and the scanning line Because of the fluctuation of, the size of the storage capacity has changed greatly.

【0011】即ち例えば、図6に示す様に走査線8に対
して画素電極9が矢印s方向にずれを生じると、走査線
8及び画素電極9の重なり部分10が図5に比し縮小さ
れ、これに比例して蓄積容量も図5に示す場合に比し小
さくなってしまい、ショットムラや焼き付き等の表示不
良を生じ表示品位を低下するという問題を生じていた。
That is, for example, when the pixel electrode 9 is displaced from the scanning line 8 in the direction of the arrow s as shown in FIG. 6, the overlapping portion 10 of the scanning line 8 and the pixel electrode 9 is reduced as compared with FIG. However, in proportion to this, the storage capacity also becomes smaller than that shown in FIG. 5, and there is a problem in that display defects such as shot unevenness and image sticking occur and display quality is degraded.

【0012】更に大面積液晶表示装置において、一画面
を複数のブロックに分割して、ブロック毎に露光、エッ
チングを行い蓄積容量線或いは画素電極等をパターン形
成する様な場合には、ブロック毎の走査線及び画素電極
のパターンのずれによりブロック毎に蓄積容量の値がば
らつき、ブロック毎に焼き付きやショットむらによる表
示不良を生じ、ショットブロックが視認され表示品位が
低下されるという問題も生じていた。
Further, in a large-area liquid crystal display device, when one screen is divided into a plurality of blocks and each block is exposed and etched to form a storage capacitor line or a pixel electrode, a pattern is formed for each block. There is also a problem that the value of the storage capacitance varies from block to block due to the deviation of the pattern of the scanning line and the pixel electrode, display defects occur due to burn-in and shot unevenness in each block, and the shot block is visually recognized and the display quality deteriorates. .

【0013】そこで本発明は上記課題を除去するもの
で、TFTを駆動素子とするアクティブマトリクス基板
において、開口率の低下を招くこと無く、補助容量の安
定を図り、画面輝度を向上する事により、従来バックラ
イトに要していたエネルギーの省力化を図ると共に、表
示不良を防止し、表示品位の高いアクテイブマトリクス
型液晶表示装置を提供する事を目的とする。
Therefore, the present invention eliminates the above-mentioned problems, and in an active matrix substrate using a TFT as a driving element, the auxiliary capacitance is stabilized and the screen brightness is improved without lowering the aperture ratio. It is an object of the present invention to provide an active matrix type liquid crystal display device which has a high display quality while preventing a display defect while saving energy required for a conventional backlight.

【0014】[0014]

【課題を解決するための手段】上記課題を解決する為の
請求項1に記載の発明は、マトリクス状に配列される画
素電極を有するアクティブマトリクス基板及び、このア
クティブマトリクス基板に対向され対向電極を有する対
向基板並びに、前記アクティブマトリクス基板及び前記
対向基板の間に封入される液晶組成物とを具備するアク
テイブマトリクス型液晶表示装置において、前記アクテ
ィブマトリクス基板が、透明な絶縁基板上に形成され、
ゲート絶縁膜を介しゲート電極上方に設けられる活性領
域並びに、この活性領域を挾みソース電極更にはドレイ
ン電極を備え、マトリクス状に配列される複数の薄膜ト
ランジスタと、前記絶縁基板上にて形成され、前記ゲー
ト電極に走査信号を供給する細線状の複数の走査線と、
前記ドレイン電極に映像信号を供給する複数の信号線
と、前記絶縁基板上にて前段の走査線に細線状の間隙を
保持して近接形成され、一部が前記前段の走査線に接続
される蓄積容量線と、マトリクス上に配列され前記ソー
ス電極に接続される画素電極とを設けるものである。
According to a first aspect of the present invention for solving the above-mentioned problems, an active matrix substrate having pixel electrodes arranged in a matrix, and an opposite electrode facing the active matrix substrate are provided. In an active matrix type liquid crystal display device comprising a counter substrate having, and a liquid crystal composition enclosed between the active matrix substrate and the counter substrate, the active matrix substrate is formed on a transparent insulating substrate,
An active region provided above the gate electrode through the gate insulating film, and a plurality of thin film transistors arranged in a matrix, including a source electrode and a drain electrode sandwiching the active region, and formed on the insulating substrate, A plurality of thin line-shaped scanning lines for supplying a scanning signal to the gate electrode,
A plurality of signal lines for supplying a video signal to the drain electrode and a scanning line of the preceding stage are formed in proximity to each other on the insulating substrate with a thin line-shaped gap therebetween, and a part thereof is connected to the scanning line of the preceding stage. Storage capacitor lines and pixel electrodes arranged in a matrix and connected to the source electrodes are provided.

【0015】又請求項2に記載の発明は、請求項1に記
載のアクティブマトリクス型液晶表示装置において、走
査線の幅を最小加工限度寸法とするものである。
According to a second aspect of the invention, in the active matrix type liquid crystal display device according to the first aspect, the width of the scanning line is set as the minimum processing limit dimension.

【0016】又請求項3に記載の発明は、請求項1又は
請求項2に記載のアクティブマトリクス型液晶表示装置
において、画素電極の一側を、細線状の間隙内に位置
し、前段の走査線に重ならない様形成するものである。
According to a third aspect of the present invention, in the active matrix type liquid crystal display device according to the first or second aspect, one side of the pixel electrode is located in the thin line-shaped gap, and the preceding scanning is performed. It is formed so that it does not overlap the line.

【0017】又請求項4に記載の発明は、請求項1又は
請求項2に記載のアクティブマトリクス型液晶表示装置
において、細線状の間隙を10μm以下とするものであ
る。又請求項5に記載の発明は、請求項1又は請求項2
に記載のアクティブマトリクス型液晶表示装置におい
て、走査線の幅を10μm以下とするものである。
According to a fourth aspect of the invention, in the active matrix type liquid crystal display device according to the first or second aspect, the fine line-shaped gap is 10 μm or less. The invention described in claim 5 is the same as claim 1 or claim 2.
In the active matrix type liquid crystal display device described in (1), the width of the scanning line is 10 μm or less.

【0018】[0018]

【作用】本発明によれば、走査線を細線状に加工すると
共に、蓄積容量線を細線状の間隙を有するよう前段の走
査線に近接する一方、前段の走査線及び蓄積容量線を一
部で接続する事により、画素電極の面積の拡大を図り、
アクティブマトリクス基板の開口率ひいては画面輝度を
向上し、バックライトに要する電力の節約を図ると共
に、細線化したために走査線に断線を生じた場合であっ
ても、電気的には、蓄積容量線側にバイパスされ導通さ
れるので、信号伝達機能が損なわれる事が無い。
According to the present invention, the scanning line is processed into a fine line shape, and the storage capacitance line is close to the preceding scanning line so as to have a thin line-shaped gap, while the preceding scanning line and the storage capacitance line are partially formed. By connecting with, the area of the pixel electrode is increased,
The aperture ratio of the active matrix substrate and thus the screen brightness are improved to save the power required for the backlight, and even if the scan line is broken due to the thin line, it is electrically connected to the storage capacitor line side. The signal transmission function is not impaired because it is bypassed and conducted.

【0019】又本発明によれば、画素電極をその一側が
走査線及び蓄積容量線との細線状の間隙に位置する様に
形成する事により、走査線及び蓄積容量線のパターンと
画素電極のパターンの重ね合わせがずれたとしても、細
線状の間隙にてそのずれを補償出来るので、蓄積容量は
常に必要な一定値を得られ、焼き付きやショットむらに
よる表示不良の発生を防止し、表示品位の向上を図るも
のである。
Further, according to the present invention, the pixel electrode is formed so that one side thereof is located in the thin line-shaped gap between the scanning line and the storage capacitor line, so that the pattern of the scanning line and the storage capacitor line and the pixel electrode are formed. Even if the overlay of the patterns is misaligned, the misalignment can be compensated for by the thin line-shaped gap, so the storage capacitor can always obtain the required constant value, prevent the occurrence of display defects due to burn-in and shot unevenness, and improve the display quality. It is intended to improve.

【0020】[0020]

【実施例】以下、本発明の一実施例を図1及び図2を参
照して説明する。20は、アクティブマトリクス型の液
晶表示装置であり、駆動素子としてTFT21を用いる
アクティブマトリクス基板22及び対向基板23の間
に、ポリイミドからなる配向膜24、26を介して、液
晶組成物であるネマチック型液晶27が保持されると共
に偏光板53、54を有している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. Reference numeral 20 denotes an active matrix type liquid crystal display device, which is a nematic type liquid crystal composition which is a liquid crystal composition with alignment films 24 and 26 made of polyimide interposed between an active matrix substrate 22 and a counter substrate 23 using a TFT 21 as a driving element. The liquid crystal 27 is held and also has polarizing plates 53 and 54.

【0021】ここでアクティブマトリクス基板22は、
透明なガラスからなる絶縁基板28上に、タリウム(T
a)、モリブデン(Mo)、タングステン(W)、チタ
ン(Ti)、クロム(Cr)、アルミニウム(Al)、
銅(Cu)等の金属材料、あるいはその合金からなる単
層膜や積層膜からなり、走査信号を供給すると共に一部
がゲート電極31として突設され、最小加工限度寸法程
度の、幅5μmのN段目の走査線30及び、この走査線
30と幅5μmの細線状の間隙12を隔てると共に、接
続部13aにて走査線30と接続される(N+1)段目
の蓄積容量線13がパターン形成されている。
Here, the active matrix substrate 22 is
On the insulating substrate 28 made of transparent glass, thallium (T
a), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), aluminum (Al),
It is composed of a single layer film or a laminated film made of a metal material such as copper (Cu), or an alloy thereof, and supplies a scanning signal and partly projects as a gate electrode 31 and has a width of 5 μm, which is about the minimum processing limit dimension. The N-th stage scanning line 30 and the (N + 1) -th stage storage capacitance line 13 that is separated from the scanning line 30 by a thin line-shaped gap 12 having a width of 5 μm and is connected to the scanning line 30 at the connection portion 13a are patterned. Has been formed.

【0022】そしてこれ等の上には、酸化シリコン(S
iOx)からなるゲート絶縁膜32が被覆され、このゲ
ート絶縁膜32を介したゲート電極31上方には、i型
の水素化アモルファスシリコン(以下i型a−Si:H
と称する。)からなる半導体層34及び、窒化シリコン
(SiNx)からなる保護絶縁膜35並びに、良好なオ
ーミックコンタクトを得るためのn型アモルファスシリ
コン(以下n型a−Siと称する。)からなるオーミッ
ク膜40がパターン形成され、チャネル領域(A)を挾
み、ソース領域(B)、ドレイン領域(C)を有するT
FT21を形成している。
On top of these, silicon oxide (S
A gate insulating film 32 made of iOx) is covered, and above the gate electrode 31 via the gate insulating film 32, i-type hydrogenated amorphous silicon (hereinafter, i-type a-Si: H) is formed.
Called. ) Semiconductor layer 34, a protective insulating film 35 made of silicon nitride (SiNx), and an ohmic film 40 made of n-type amorphous silicon (hereinafter referred to as n-type a-Si) for obtaining a good ohmic contact. Patterned, T with channel region (A), source region (B), drain region (C)
FT21 is formed.

【0023】更にゲート絶縁膜32上にはインジウム錫
酸化物(以下ITOと称する。)からなる画素電極43
がパターン形成されるが、この画素電極43の蓄積容量
線13側端部43aは、蓄積容量線13及び走査線30
の間隙12のほぼ中央に位置する様、蓄積容量線13の
端部13bより約2μm大きくなるようパターン形成さ
れている。そして蓄積容量線13及び画素電極43との
重なり部分により蓄積容量を形成している。
Further, a pixel electrode 43 made of indium tin oxide (hereinafter referred to as ITO) is formed on the gate insulating film 32.
Are formed in a pattern, but the end portion 43a of the pixel electrode 43 on the side of the storage capacitance line 13 has the storage capacitance line 13 and the scanning line 30.
The pattern is formed so as to be located approximately in the center of the gap 12 and is larger than the end portion 13b of the storage capacitance line 13 by about 2 μm. The overlapping portion of the storage capacitance line 13 and the pixel electrode 43 forms a storage capacitance.

【0024】更に、タリウム(Ta)、モリブデン(M
o)、タングステン(W)、チタン(Ti)、クロム
(Cr)、アルミニウム(Al)、銅(Cu)等の金属
材料、あるいはその合金からなる単層膜や積層膜からな
り、画素電極43に接続されるソース電極37及び、信
号線38並びに、信号線38から枝別れして成るドレイ
ン電極39がパターン形成されている。
Furthermore, thallium (Ta), molybdenum (M
o), tungsten (W), titanium (Ti), chromium (Cr), aluminum (Al), copper (Cu), or other metal material, or a single layer film or a laminated film made of an alloy thereof. A source electrode 37, a signal line 38, and a drain electrode 39, which is branched from the signal line 38, are patterned.

【0025】そしてこれ等の上面には、窒化シリコン
(SiNx)からなる絶縁性保護膜41が被覆されてい
る。
The upper surfaces of these are covered with an insulating protective film 41 made of silicon nitride (SiNx).

【0026】一方対向基板23は、透明なガラスからな
る絶縁基板46上に遮光性材料であるクロム(Cr)か
らなり、各領域に赤(R)、緑(G)、青(B)の着色
層を有するブラックマトリクス47及び、ITOからな
る対向電極48を有している。
On the other hand, the counter substrate 23 is made of a light-shielding material such as chromium (Cr) on an insulating substrate 46 made of transparent glass, and each region is colored with red (R), green (G), and blue (B). It has a black matrix 47 having layers and a counter electrode 48 made of ITO.

【0027】次に液晶表示装置20の製造方法について
述べる。先ずアクティブマトリクス基板22は、絶縁基
板28上にスパッタ法によりタリウム(Ta)、モリブ
デン(Mo)、タングステン(W)、チタン(Ti)、
クロム(Cr)、アルミニウム(Al)等の金属材料、
あるいはその合金からなる単層膜や積層膜を成膜し、フ
ォトレジスト(図示せず)をマスクとしてエッチング加
工するフォトリソグラフィ技術を用い、走査線30及び
ゲート電極31並びに蓄積容量線13をパターン形成す
る。
Next, a method of manufacturing the liquid crystal display device 20 will be described. First, the active matrix substrate 22 is formed by sputtering thallium (Ta), molybdenum (Mo), tungsten (W), titanium (Ti) on the insulating substrate 28.
Metal materials such as chromium (Cr) and aluminum (Al),
Alternatively, a patterning of the scanning line 30, the gate electrode 31, and the storage capacitance line 13 is performed by using a photolithography technique in which a single layer film or a laminated film made of the alloy is formed and etching is performed using a photoresist (not shown) as a mask. To do.

【0028】次にプラズマCVD法によりゲート絶縁膜
32、(i型a−Si:H)膜、窒化シリコン(SiN
x)膜を積層形成した上に、ネガ型レジストを塗布し、
ゲート電極31をマスクにして絶縁基板28背面から露
光し、ネガ型レジストを露光部分を残してパターン形成
する。そしてこのネガ型レジストをマスクにして、窒化
シリコン(SiNx)膜をゲート電極31に対して自己
整合的に形状加工し、保護絶縁膜35を形成する。これ
により保護絶縁膜35は、裏面露光時の光の回析により
ゲート電極31より0〜3μm小さく形成される事とな
る。
Next, the gate insulating film 32, (i-type a-Si: H) film, and silicon nitride (SiN) are formed by the plasma CVD method.
x) A negative resist is applied on the laminated film,
Exposure is performed from the back surface of the insulating substrate 28 using the gate electrode 31 as a mask, and a negative resist is patterned to leave an exposed portion. Then, using this negative resist as a mask, the silicon nitride (SiNx) film is shaped in a self-aligning manner with respect to the gate electrode 31 to form the protective insulating film 35. As a result, the protective insulating film 35 is formed to be smaller than the gate electrode 31 by 0 to 3 μm due to the diffraction of light during the back surface exposure.

【0029】続いてプラズマCVD法を用いて(i型a
−Si:H)膜上に、(n型a−Si)膜を形成し、フ
ォトリソグラフィ技術により、(i型a−Si:H)膜
及び(n型a−Si)膜をフォトエッチングし半導体層
34及びオーミック層40をパターン形成する。
Subsequently, the plasma CVD method is used (i-type a
A (n-type a-Si) film is formed on the -Si: H) film, and the (i-type a-Si: H) film and the (n-type a-Si) film are photoetched by a photolithography technique to form a semiconductor. The layer 34 and ohmic layer 40 are patterned.

【0030】次にスパッタ法によりITO膜を成膜た上
に、レジストを塗布し、フォトリソグラフィ技術により
レジストをパターン形成し、このレジストをマスクにI
TO膜をフォトエッチングして画素電極43をパターン
形成する。
Next, an ITO film is formed by a sputtering method, a resist is applied on the ITO film, and the resist is patterned by a photolithography technique.
The TO film is photo-etched to form the pixel electrode 43 in a pattern.

【0031】更にスパッタ法によりタリウム(Ta)、
モリブデン(Mo)、タングステン(W)、チタン(T
i)、クロム(Cr)、アルミニウム(Al)等の金属
材料、あるいはその合金からなる単層膜や積層膜を成膜
し、フォトリソグラフィ技術によりソース電極37、信
号線38及びドレイン電極39をパターン形成した後、
窒化シリコン(SiNx)からなる絶縁性保護膜41を
成膜し、フォトリソグラフィ技術により所定の形状にパ
ターニングをし、アクティブマトリクス基板22を形成
する。
Further, thallium (Ta) is formed by the sputtering method.
Molybdenum (Mo), tungsten (W), titanium (T
i), a single layer film or a laminated film made of a metal material such as chromium (Cr), aluminum (Al), or an alloy thereof is formed, and the source electrode 37, the signal line 38, and the drain electrode 39 are patterned by the photolithography technique. After forming
An insulating protective film 41 made of silicon nitride (SiNx) is formed and patterned into a predetermined shape by a photolithography technique to form an active matrix substrate 22.

【0032】次に対向基板23にあっては、絶縁基板4
6上にスパッタ法によりクロム(Cr)を成膜し、フォ
トリソグラフィ技術により所定の形状にエッチングし、
ブラックマトリクス47を格子状に形成する。そしてブ
ラックマトリクス47に顔料を分散させた層を塗布後、
パターン露光、現像を繰り返し、ブラックマトリクス4
7上に赤、緑、青の3色のストライプ領域を形成した
後、スパッタ法によりITOからなる対向電極48を全
面に形成して対向基板23を形成する。
Next, in the counter substrate 23, the insulating substrate 4
A film of chromium (Cr) is formed on 6 by a sputtering method and etched into a predetermined shape by a photolithography technique.
The black matrix 47 is formed in a lattice shape. Then, after coating the layer in which the pigment is dispersed on the black matrix 47,
Repeat pattern exposure and development, and black matrix 4
After forming the stripe regions of three colors of red, green and blue on the counter electrode 7, the counter electrode 48 made of ITO is formed on the entire surface by the sputtering method to form the counter substrate 23.

【0033】続いて、アクティブマトリクス基板22及
び対向基板23の画素電極43側及び対向電極48側全
面に低温キュア型のポリイミドからなる配向膜24、2
6を印刷塗布し、両基板22、23の対向時に、配向軸
が90°と成るようにラビング処理をした後、両基板2
2、23を対向して組み立て、セル化し、その間隙にネ
マチック型液晶27を注入し封止する。そして両基板2
2、23の絶縁基板28、46側に偏光板53、54を
取着して液晶表示装置20とする。
Then, the alignment films 24 and 2 made of low temperature cure type polyimide are formed on the entire surfaces of the active matrix substrate 22 and the counter substrate 23 on the pixel electrode 43 side and the counter electrode 48 side.
6 is applied by printing, and when both substrates 22 and 23 face each other, a rubbing treatment is performed so that the orientation axis becomes 90 °, and then both substrates 2
2 and 23 are assembled to face each other to form a cell, and nematic liquid crystal 27 is injected into the gap and sealed. And both substrates 2
Polarizing plates 53 and 54 are attached to the insulating substrates 28 and 46 of Nos. 2 and 23 to complete the liquid crystal display device 20.

【0034】この様に構成すれば、走査線30幅を最小
加工寸法にパターン形成すると共に、走査線30及び蓄
積容量線13の間隙12が最小加工寸法となるよう、蓄
積容量線13を走査線30に近接パターン形成する事に
より、画素電極43の光透過部分の面積を拡大出来るの
で、アクティブマトリクス基板22の開口率を向上出
来、ひいては液晶表示装置20の画面輝度を向上出来
る。従って、バックライトの光量を低減出来、装置の省
エネルギー化を促進出来る。
According to this structure, the width of the scanning line 30 is patterned to the minimum processing size, and the storage capacity line 13 is scanned so that the gap 12 between the scanning line 30 and the storage capacity line 13 becomes the minimum processing size. Since the area of the light transmitting portion of the pixel electrode 43 can be enlarged by forming the proximity pattern on the pixel 30, the aperture ratio of the active matrix substrate 22 can be improved and the screen brightness of the liquid crystal display device 20 can be improved. Therefore, the light amount of the backlight can be reduced, and energy saving of the device can be promoted.

【0035】しかも走査線30幅を最小加工寸法にする
事により、断線を生じたとしても、接続部13aにて蓄
積容量線13に接続され、電気的に導通される事から、
走査信号の供給機能が損なわれる事がなく、製造時、走
査線30断線により歩留まりが低減される事もない。
Moreover, by setting the width of the scanning line 30 to the minimum processing size, even if a disconnection occurs, it is connected to the storage capacitance line 13 at the connection portion 13a and electrically connected,
The scanning signal supply function is not impaired, and the yield is not reduced due to the disconnection of the scanning line 30 during manufacturing.

【0036】更に製造時、蓄積容量線13上に重ねられ
る画素電極43のパターンがずれたとしても、実際に
は、蓄積容量線13及び走査線30の間隙12への画素
電極43の突出量が変動されるものの、蓄積容量線13
と画素電極43との重なり部分の面積が同じである事か
ら、蓄積容量の値が変化される事無く、ショットむらや
焼き付きによる表示欠陥を防止出来、高品位の表示画像
を得られる。
Further, even if the pattern of the pixel electrode 43 overlaid on the storage capacitor line 13 is displaced during manufacturing, the amount of protrusion of the pixel electrode 43 into the gap 12 between the storage capacitor line 13 and the scanning line 30 is actually. Although it varies, the storage capacitance line 13
Since the area of the overlapping portion between the pixel electrode 43 and the pixel electrode 43 is the same, it is possible to prevent display defects due to shot unevenness and image sticking without changing the value of the storage capacitance, and obtain a high-quality display image.

【0037】尚本発明は上記実施例に限られるものでな
く、その趣旨を変えない範囲での変更は可能であって、
例えばゲート電極や、走査線或いは信号線の材質或いは
ゲート絶縁膜や絶縁性保護膜の材料等任意である。
The present invention is not limited to the above-mentioned embodiments, and modifications can be made without departing from the spirit of the invention.
For example, the material of the gate electrode, the scanning line or the signal line, the material of the gate insulating film or the insulating protective film, and the like are arbitrary.

【0038】又走査線の幅や走査線及び蓄積容量線の間
隙の幅等も任意であるが、開口率を向上する為には、細
く加工される事が望ましく、より好ましくは、10μm
以下とされる。
The width of the scanning line and the width of the gap between the scanning line and the storage capacitor line are arbitrary, but in order to improve the aperture ratio, it is desirable to make them finer, more preferably 10 μm.
It is considered as follows.

【0039】但し、走査線及び蓄積容量線の間隙の幅
は、更に蓄積容量線及び走査線のパターンと画素電極パ
ターンとの重ね合わせ精度をも考慮する必要があり、例
えば、両パターンの重ね合わせ精度がaμmとすると、
間隙の幅を、少なくとも2a(μm)保持する様に設定
すれば、パターン形成時のずれを確実に補償出来、蓄積
容量のばらつきをより確実に防止出来る。
However, regarding the width of the gap between the scanning lines and the storage capacitor lines, it is necessary to further consider the overlay accuracy of the patterns of the storage capacitor lines and the scanning lines and the pixel electrode pattern. If the accuracy is aμm,
If the width of the gap is set to hold at least 2a (μm), it is possible to reliably compensate for the deviation at the time of pattern formation and to more reliably prevent the variation in the storage capacitance.

【0040】更に蓄積容量線も、走査線と細線状の間隙
を保持するよう近接されていればその形状は任意であ
り、例えば図3に示す他の変形例の様に、走査線57に
間隙58を保持して近接される蓄積容量線60を、線状
ではなく、π型にパターン形成し、接続部60aにて走
査線57と接続する様にしても良い。
Further, the storage capacitor line may have any shape as long as it is close to the scanning line so as to maintain a thin line-shaped gap. For example, as in another modification shown in FIG. It is also possible to form the storage capacitor line 60, which holds 58 and is close to it, in a π-type pattern instead of a linear shape and connect it to the scanning line 57 at the connection portion 60a.

【0041】この様に形成すれば、蓄積容量線60を遮
光体の一部を兼用出来ると共に、画素電極61の斜線で
示す領域(D)にも光が透過されることから、アクテイ
ブマトリクス基板62の開口率をより向上することが出
来る。
With this structure, the storage capacitor line 60 can be used also as a part of the light shield, and light can also be transmitted to the hatched area (D) of the pixel electrode 61, so that the active matrix substrate 62 is formed. The aperture ratio can be further improved.

【0042】又アクティブマトリクス基板の製造方法も
任意であり、例えば大面積液晶表示装置用等にあって
は、一画面を複数のブロックに分割して、ブロック毎に
露光、エッチングを行い蓄積容量線或いは画素電極等を
パターン形成しても良い。この様な製造方法において
も、従来のようにブロック毎に蓄積容量の値がばらつく
事が無いので、中間調表示を行ってもブロック毎の焼き
付きやショットむらによるショットブロックが視認され
る事もなく、表示品位の向上を図れる。
The method of manufacturing the active matrix substrate is also arbitrary. For example, for a large area liquid crystal display device, one screen is divided into a plurality of blocks, and each block is exposed and etched to carry out storage capacitance line. Alternatively, the pixel electrodes and the like may be patterned. Even in such a manufacturing method, since the value of the storage capacity does not vary from block to block as in the conventional case, a shot block due to image sticking or shot unevenness is not visually recognized even if halftone display is performed. The display quality can be improved.

【0043】[0043]

【発明の効果】以上説明したように本発明によれば、走
査線及び、走査線と蓄積容量線との間隙を細線状にパタ
ーン形成する事により、画素電極の光透過部分の面積を
拡大出来、アクティブマトリクス基板の開口率ひいては
液晶表示装置の画面輝度を向上出来る事から、バックラ
イトの光量低減による省エネルギー化促進が可能とな
る。
As described above, according to the present invention, the area of the light transmitting portion of the pixel electrode can be increased by patterning the scanning line and the gap between the scanning line and the storage capacitance line in a thin line pattern. Since the aperture ratio of the active matrix substrate and thus the screen brightness of the liquid crystal display device can be improved, energy saving can be promoted by reducing the light amount of the backlight.

【0044】しかも走査線を細線化したために断線を生
じたとしても、一部が蓄積容量線に接続され走査信号は
蓄積容量線にバイパスされるのでその信号伝達機能が損
なわれる事がなく、走査線断線により歩留まりが低減さ
れる事もない。
Moreover, even if a disconnection occurs due to the thinning of the scanning line, a part of the scanning line is connected to the storage capacitance line and the scanning signal is bypassed to the storage capacitance line, so that the signal transmission function is not impaired and scanning is performed. The yield will not be reduced due to the wire breakage.

【0045】更に製造時、蓄積容量線のパターンとその
上に重ねられる画素電極のパターンがずれたとしても、
間隙にてそのずれが補償され、蓄積容量線と画素電極と
の重なり部分の面積が常に一定に保持される事から、シ
ョットむらや焼き付き更にはショットブロックの視認等
による表示不良を防止出来、高品位の表示画像を得られ
る。
Further, even if the pattern of the storage capacitor line and the pattern of the pixel electrode overlaid thereon are deviated at the time of manufacturing,
The gap is compensated for, and the area of the overlapping portion of the storage capacitance line and the pixel electrode is always kept constant. Therefore, it is possible to prevent display defects due to shot unevenness, burn-in, and visual recognition of shot blocks. A display image of quality can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のアクティブマトリクス基板
を上面から見た一部概略説明図である。
FIG. 1 is a partial schematic explanatory view of an active matrix substrate of one embodiment of the present invention seen from above.

【図2】本発明の一実施例の液晶表示装置を示し、図1
のA−B線及びB−C線に相当する位置における概略断
面図である。
2 shows a liquid crystal display device according to an embodiment of the present invention, and FIG.
It is a schematic sectional drawing in the position corresponding to the AB line and BC line of FIG.

【図3】本発明の他の変型例のアクティブマトリクス基
板を上面から見た一部概略説明図である。
FIG. 3 is a partial schematic explanatory view of an active matrix substrate of another modified example of the present invention as viewed from above.

【図4】第1の従来例のアクティブマトリクス基板を上
面から見た一部概略説明図である。
FIG. 4 is a partial schematic explanatory view of an active matrix substrate of a first conventional example as viewed from above.

【図5】第2の従来例のアクティブマトリクス基板を上
面から見た一部概略説明図である。
FIG. 5 is a partial schematic explanatory view of an active matrix substrate of a second conventional example as viewed from above.

【図6】第2の従来例のアクティブマトリクス基板の蓄
積容量電極のパターンと画素電極のパターン形成がずれ
た場合を上面から見た一部概略説明図である。
FIG. 6 is a partial schematic explanatory view of the case where the pattern of the storage capacitor electrode and the pattern of the pixel electrode of the active matrix substrate of the second conventional example are deviated from the top view.

【符号の説明】[Explanation of symbols]

12…間隙 13…蓄積容量線 20…液晶表示装置 21…TFT 22…アクティブマトリクス基板 30…走査線 43…画素電極 12 ... Gap 13 ... Storage capacitance line 20 ... Liquid crystal display device 21 ... TFT 22 ... Active matrix substrate 30 ... Scan line 43 ... Pixel electrode

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 マトリクス状に配列される画素電極を有
するアクティブマトリクス基板及び、このアクティブマ
トリクス基板に対向され対向電極を有する対向基板並び
に、前記アクティブマトリクス基板及び前記対向基板の
間に封入される液晶組成物とを具備するアクテイブマト
リクス型液晶表示装置において、 前記アクティブマトリクス基板が、 透明な絶縁基板上に形成され、ゲート絶縁膜を介しゲー
ト電極上方に設けられる活性領域並びに、この活性領域
を挾みソース電極更にはドレイン電極を備え、マトリク
ス状に配列される複数の薄膜トランジスタと、 前記絶縁基板上にて形成され、前記ゲート電極に走査信
号を供給する細線状の複数の走査線と、 前記ドレイン電極に映像信号を供給する複数の信号線
と、 前記絶縁基板上にて前段の走査線に細線状の間隙を保持
して近接形成され、一部が前記前段の走査線に接続され
る蓄積容量線と、 マトリクス上に配列され前記ソース電極に接続される画
素電極とを具備する事を特徴とするアクティブマトリク
ス型液晶表示装置。
1. An active matrix substrate having pixel electrodes arranged in a matrix, a counter substrate having a counter electrode facing the active matrix substrate, and a liquid crystal sealed between the active matrix substrate and the counter substrate. An active matrix type liquid crystal display device comprising a composition, wherein the active matrix substrate is formed on a transparent insulating substrate, and an active region is provided above the gate electrode via a gate insulating film, and the active region is sandwiched. A plurality of thin film transistors that are arranged in a matrix and include a source electrode and a drain electrode; a plurality of thin line-shaped scanning lines that are formed on the insulating substrate and supply a scanning signal to the gate electrode; and the drain electrode A plurality of signal lines for supplying video signals to the The scanning line includes a storage capacitor line that is formed in proximity to the scanning line with a thin line-shaped gap, a part of which is connected to the preceding scanning line, and a pixel electrode that is arranged in a matrix and connected to the source electrode. An active matrix type liquid crystal display device characterized by the above.
【請求項2】 走査線の幅が最小加工限度寸法である事
を特徴とする請求項1に記載のアクティブマトリクス型
液晶表示装置。
2. The active matrix type liquid crystal display device according to claim 1, wherein the width of the scanning line is a minimum processing limit dimension.
【請求項3】 画素電極の一側が、細線状の間隙内に位
置し、前段の走査線に重ならない様形成される事を特徴
とする請求項1又は請求項2に記載のアクティブマトリ
クス型液晶表示装置。
3. The active matrix liquid crystal according to claim 1 or 2, wherein one side of the pixel electrode is located in the thin line-shaped gap and is formed so as not to overlap the scanning line of the preceding stage. Display device.
【請求項4】 細線状の間隙が10μm以下である事を
特徴とする請求項1又は請求項2に記載のアクティブマ
トリクス型液晶表示装置。
4. The active matrix type liquid crystal display device according to claim 1, wherein the thin line-shaped gap is 10 μm or less.
【請求項5】 走査線の幅が10μm以下である事を特
徴とする請求項1又は請求項2に記載のアクティブマト
リクス型液晶表示装置。
5. The active matrix type liquid crystal display device according to claim 1, wherein the width of the scanning line is 10 μm or less.
JP24910495A 1995-09-27 1995-09-27 Active matrix type liquid crystal display Expired - Fee Related JP3593391B2 (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24910495A JP3593391B2 (en) 1995-09-27 1995-09-27 Active matrix type liquid crystal display

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JPH0990420A true JPH0990420A (en) 1997-04-04
JP3593391B2 JP3593391B2 (en) 2004-11-24

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003075869A (en) * 2001-09-05 2003-03-12 Toshiba Corp Flat display device
WO2005116745A1 (en) * 2004-05-27 2005-12-08 Sharp Kabushiki Kaisha Active matrix substrate, method for correcting a pixel deffect therein and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003075869A (en) * 2001-09-05 2003-03-12 Toshiba Corp Flat display device
WO2005116745A1 (en) * 2004-05-27 2005-12-08 Sharp Kabushiki Kaisha Active matrix substrate, method for correcting a pixel deffect therein and manufacturing method thereof
US7973871B2 (en) 2004-05-27 2011-07-05 Sharp Kabushiki Kaisha Active matrix substrate, method for correcting a pixel deffect therein and manufacturing method thereof

Also Published As

Publication number Publication date
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