JPH0990921A - Image synthesizer and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily realize image synthesis between a digital image signal and an analog image signal. SOLUTION: This synthesizer is constituted of a selector 8 capable of synthesizing a digital graphics signal GD0-7 with the digital image signal MD0-7, a mixing circuit 10 capable of synthesizing two systems of analog video signals and a digital video encoder 9 provided with an operation circuit 11 converting a digital video signal into an analog video signal and a delay circuit 12 delaying a control signal S1 for synthesizing the image so as to be equivalent to an operation delay time occurring in the operation circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image synthesizing device and a receiving device, and is particularly suitable for controlling the synthesizing position when selecting and synthesizing image signals.

[0002]

2. Description of the Related Art In recent years, due to the development of digital signal technology, in a stationary receiver (eg, set-top box) placed on a monitor, for example, a graphic such as a character signal for realizing a digital image signal and a user interface. Image synthesis processing such as synthesis of a video signal into a digital image signal or synthesis of an analog video signal and a graphics signal is performed.

FIG. 5 shows an example of a block diagram of a conventional image synthesizing apparatus for performing the image synthesizing process as described above. In this figure, the graphics signal generator 5
1 is a digital graphics signal GD such as a menu screen when the user operates the operation unit 52.
0-7, and a control signal S ₁ for synthesizing the graphics signal GD 0-7 into a digital image signal or an analog video signal described later.

The image decompression device 53 decompresses an 8-bit digital image signal which is compressed and transmitted from cable television broadcasting or the like to generate a digital image signal MD0-7.
Is output. The selector 54 selects the image data of the graphics signal GD0-7 or the image data of the digital image signal MD0-7 at a predetermined timing based on the control signal S ₁ and synthesizes and outputs the digital image signal D0-7. It is done like this.

The digital video encoder 55 is, for example, 1
The digital image signal D0-7 supplied from the selector 54 is arithmetically processed, converted into an analog video signal A, and output. Is being done.

Although not shown, the mixing circuit 57 receives an analog video signal B from the outside via a television tuner and an analog video signal A from the digital video encoder 55, and selects one of the video signals. In addition to being able to output, image data of the analog video signal A and the analog video signal B can be combined and output based on the control signal S ₁ supplied from the graphics signal generator 51. In addition,
Vertical / horizontal sync signal (VSYNC / HS) of analog video signal B
YNC) is supplied to the graphics signal generator 51, the image decompressor 53, and the digital video encoder 55.

In the conventional image synthesizing apparatus thus constructed, the analog video signal B and the graphics signal G
The case of combining D0-7 will be described with reference to the timing chart of FIG. First, the digital image signal MD in which the image data output from the image expansion device 53 is M
0-7 and the graphics signal GD0-7 in which the image data output from the graphics signal generator 51 is G
Is selected by the selector 54 according to the timing of the control signal S ₁ and the image data M of the digital image signal MD 0-7 is selected.
Then, the digital image signal D0-7 in which the image data G of the graphics signal is combined is output.

This digital image signal D0-7 is converted into an analog video signal A by an arithmetic circuit 56 of a digital video encoder 55 and supplied to a mixing circuit 57. Further, the mixing circuit 57 converts the analog video signal A from the analog video signal A, for example, a control signal S _The image data is extracted at the timing of ₁ and combined with the image data of the analog video signal B. That is, in the mixing circuit 57, the image data G portion of the graphics signal can be extracted from the analog video signal A, combined with the image data B of the analog video signal B, and output.

Such an image synthesizing device realizes an interface with a user by a digital signal by being provided in a receiving device in which an analog video signal and a digital image signal are mixed, and further, this user interface is provided with both analog and digital images. It is effective when shared with the source.

[0010]

In the image synthesizing apparatus as described above, the arithmetic circuit 56 of the digital video encoder 55 arithmetically processes the digital image signal D0-7, converts it into the analog video signal A, and outputs it. If you do
Since an arithmetic delay occurs in the arithmetic circuit 56, the analog video signal A output from the digital video encoder 55 becomes a signal delayed by, for example, α with respect to the digital image signal D0-7.

Therefore, for example, as shown by the signal OUT in FIG. 6, in the mixing circuit 57, the image data G is extracted from the analog video signal A at the timing of the control signal S ₁ and is combined with the image data B of the analog video signal B. In this case, the image data extracted from the analog video signal A has the arithmetic circuit 5 with respect to the image data G of graphics.
The image data is deviated by the operation delay α generated in 6.

The arithmetic delay α generated in the arithmetic circuit 56 as described above is usually several tens of clocks, and therefore the mixing circuit 5
When the image data B of the analog video signal B and the image data G of the graphics of the analog video signal A are combined in 7 and the combined image data is displayed as an analog video signal C on a monitor device or the like, the graphics image G part Was not displayed accurately, and the image quality was degraded.

Therefore, in order to solve such a problem, an image synthesizing apparatus as shown in FIG. 7 has been proposed. In addition,
The same parts as those in FIG. 5 are designated by the same reference numerals and the description thereof is omitted. In this case, the control signal S ₁ output from the graphics signal generator 51 is supplied to the selector 54 and the delay circuit 60, and the mixing circuit 57 is supplied with the control signal S ₂ via the delay circuit 60. ing.

That is, the delay circuit 60 delays the control signal S ₁ by a time corresponding to the calculation delay α generated in the calculation circuit 56 of the digital video encoder 55, and outputs the delayed control signal S _2. I have to.

Therefore, if such a control signal S ₂ is supplied to the mixing circuit 57 and the image data is extracted from the analog video signal A at the timing of this control signal S ₂ , the graphic image from the analog image signal A is generated. A portion of the image data G corresponding to the analog image data B is extracted and synthesized with the analog image signal B.
A predetermined graphics image G can be displayed on top.

However, when the image synthesizing apparatus is configured as shown in FIG. 7, it is necessary to newly provide the delay circuit 60 in the apparatus, which has a disadvantage of increasing cost. Further, the delay time generated in the delay circuit 60 needs to be set so as to correspond to the calculation delay α generated in the calculation circuit 56 of the digital video encoder 55, but the digital video encoder 5 including an integrated circuit or the like is used.
Since 5 is generally a black box, the delay time of the arithmetic circuit 56 cannot be accurately known, and it is difficult to set the delay time of the delay circuit 60.

Furthermore, when the digital video encoder 55 of the image synthesizing device is replaced with another type of digital video encoder, the delay time of the arithmetic circuit generally differs depending on the type of digital video encoder. There were also problems such as the need to set the time.

[0018]

The present invention has been made in order to solve such a problem, and as an image synthesizing device, it is possible to synthesize digital image signals of two systems by switching at a predetermined timing. Digital signal synthesizing means,
It is possible to select and combine the converting means for performing arithmetic processing on the output of the digital signal combining means to convert it into an analog image signal, the analog image signal output from this converting means, and the analog image signal input from the outside. An analog signal synthesizing means is provided, and a converting means is provided for the converting means to convert a digital image signal into an analog image signal. And a delay means for delaying.

Further, as a receiving device, a digital signal synthesizing means capable of switching and synthesizing two systems of digital image signals at a predetermined timing, and a conversion for arithmetically processing the output of the digital signal synthesizing means to convert it into an analog image signal. Means, and an analog image signal output from the converting means and an analog signal synthesizing means capable of selecting and synthesizing an analog image signal input from the outside, and the converting means converts the digital image signal into the analog image signal. And a delay unit for delaying the control signal supplied to the analog signal synthesizing unit so as to correspond to the calculation delay time generated in the calculating unit.

According to the present invention, the converting means is provided with the calculating means and the delaying means, and the control signal for controlling the position of the image to be synthesized by the delaying means is delayed so as to correspond to the calculation delay time generated in the calculating means. Therefore, even when the analog image signal and the digital image signal are combined, it is possible to improve the image quality of the display image. Further, since the calculation delay time generated in the calculation means can be easily grasped at the design stage of the conversion means, it becomes possible to easily set the delay time of the delay means.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 shows an example of a block diagram of a receiving device including an image synthesizing device according to an embodiment of the present invention. In this figure, the antenna 1 is, for example, UHF /
An antenna for receiving a VHF broadcast and a television tuner 2 are tuners for selecting a reception radio wave received by the antenna 1, respectively. An analog video signal B selected by the television tuner 2 is an image composition surrounded by a dashed line. It is supplied to the device 3.

The graphics signal generator 4 outputs a digital graphics signal GD0-7 such as a menu screen when the user operates the operation unit 5, and the graphics signal GD0-7 is supplied to a digital image to be described later. The signal or the control signal S ₁ for synthesizing the analog image signal at a predetermined position is output to the image synthesizing device 3 surrounded by the one-dot chain line.

The cable television tuner 6 is a tuner for selecting a compressed digital signal transmitted as cable television broadcasting, for example. The digital image signal selected by the tuner 6 is sent to the image decompressing device 7. It is designed to be supplied. Image decompressor 7
Is designed to decompress, for example, a compressed 8-bit digital image signal supplied from the cable television tuner 6 and output it to the image synthesizing device 3 as a digital image signal MD0-7.

The image synthesizing device 3 surrounded by the alternate long and short dash line is composed of a selector 8, a digital video encoder 9 and a mixing circuit 10. The selector 8 supplies the graphics signal GD supplied from the graphics signal generating device 4.
0-7 or one of the digital image signals MD0-7 supplied from the image decompression device 7 can be selected and output as the digital image signal D0-7, and supplied from the graphics signal generation device 4. Control signal S ₁
It is possible to select the graphics signal GD0-7 and the digital image signal MD0-7 at the timing of and output the digital image signal D0-7 in which these image data are combined.

The digital video encoder 9 is composed of, for example, a one-chip IC or the like, and has an arithmetic circuit 1 inside.
1 and a delay circuit 12 are provided. This arithmetic circuit 1
1 is a digital image signal D0- supplied from the selector 8
7 is arithmetically processed, converted into an analog video signal A, and output. On the other hand, the delay circuit 12 delays the control signal S ₁ supplied from the graphics signal generator 4 by a time corresponding to the delay time generated in the arithmetic circuit 11, and outputs it as the control signal S ₂ .

The analog video signal B supplied from the television tuner 2 and the analog video signal A from the digital video encoder 9 are input to the mixing circuit 10, and one of the video signals is selected and output. At the same time, the analog video signal A or the analog video signal B can be selected at the timing of the control signal S ₂ supplied from the delay circuit 12 of the digital video encoder 9, and these image data can be combined and output. It is done like this. The vertical / horizontal synchronizing signals (VSYNC / HSYNC) of the analog video signal B are supplied to the graphics signal generating device 4, the image decompressing device 7 and the digital video encoder 9.

A case of synthesizing the analog video signal B and the graphics signal GD0-7 in the receiving apparatus of the present embodiment configured as described above will be described with reference to the timing chart shown in FIG. Digital image signal MD0 to be image data M output from the image decompressing device 7
7 and the graphics signal GD0-7, which is the image data G output from the graphics signal generator 4, is selected by the selector 8 according to the timing of the control signal S ₁ , and the selector 8 outputs the digital image signal MD0-7. Image data M and the image data G of the graphics signal GD0-7 are combined to output a digital image signal D0-7.

The digital image signal D0-7 output from the selector 8 is converted into, for example, a composite analog video signal A by the arithmetic circuit 11 provided in the digital video encoder 9, and the mixing circuit 10 will be described later.
Is supplied to. In addition, the control signal S ₁ output from the graphics signal generator 4 is supplied to the arithmetic circuit 1 by the delay circuit 12.
It is delayed by a time corresponding to the operation delay time of 1 and supplied to the mixing circuit 10 as the control signal S ₂ .

The analog video signal A input to the mixing circuit 10 is the analog video signal B supplied from the television tuner 2 after the image data G portion of the graphics signal is extracted at the timing of the control signal S ₂ . It will be combined with the image data B.

As described above, when the mixing circuit 10 synthesizes the image data G of the analog video signal A with the image data B of the analog video signal B, a calculation delay time corresponding to a calculation delay generated in the calculation circuit 11 of the digital video encoder 9. The video signal is selected by the control signal S _{2 in} consideration of the above. Therefore, by displaying the analog television signal C output from the mixing circuit 10 on, for example, a monitor device, the analog image B and the graphics image G are combined and displayed as shown in FIG. .

Further, when the digital expanded image M and the graphics image G as shown in FIG. 3B are combined and displayed on the monitor device, the mixing circuit 1 has been described above.
An analog video signal A in which the image data M of the digital image signal MD0-7 supplied to 0 and the image data G of the graphics signal are combined is selected by a control signal (not shown) input to the mixing circuit 10. It can be realized by outputting as the analog video signal C.

When only the image of the digital image signal MD0-7 or the graphics signal GD0-7 is displayed on the monitor device, an analog image in which only the image data of the digital image signal or the graphics signal is selected by the selector 8 The signal A may be selected by the mixing circuit 10 and output as the analog video signal C. Further, it is also possible to select only the analog video signal B by the mixing circuit 10 and output it as the analog video signal C.

FIG. 4 shows the configuration of the digital video encoder 9 provided in the image synthesizing device 3 of the receiving device shown in FIG. As shown in this figure, the digital video encoder 9 includes an arithmetic circuit 11, a delay circuit 12, and a synchronization signal generator 21, and the synchronization signal generator 2
1, a horizontal / vertical synchronizing signal is generated based on the horizontal / vertical synchronizing signal (HSYNC / VSYNC) supplied from the mixing circuit 10 shown in FIG.

The arithmetic circuit 11 includes a demultiplexer 22, a low-pass filter (hereinafter referred to as "LPF") 23,2.
4, modulator 25, adders 26 and 27, and digital / analog converter (hereinafter referred to as "D / A converter")
The demultiplexer 22 demultiplexes the 8-bit digital image signal D0-7 supplied from the preceding selector 8 into a YUV signal.
Further, the U and V signals are converted into I and Q signals and output. The Y signal of the YUV signal is a luminance signal, the U signal is a color difference signal (RY), and the V signal is a color difference signal (BY).

The I signal and the Q signal are the LPF.
Filtered by 23 and 24 respectively, modulator 25
Is supplied to. The I signal and the Q signal supplied to the modulator 25 are subjected to quadrature modulation here and converted into a chroma signal, and the converted chroma signal is supplied to the adder 27.

The luminance signal Y output from the demultiplexer 22 is supplied to the adder 26, where it is added to the horizontal / vertical synchronization signal output from the synchronization signal generator 21 and supplied to the adder 27. . Modulator 2 in adder 27
The chroma signal supplied from No. 5 and the signal obtained by adding the luminance signal Y and the vertical / horizontal synchronizing signal supplied from the adder 26 are added, and a composite video signal is output. The composite video signal output from the adder 27 is digital-to-analog converted by the D / A converter 28 and output as the analog video signal A.

By the way, in such an arithmetic circuit 11, it is assumed that an arithmetic time of 4 clocks is required until the digital image signal D0-7 is converted into the analog video signal A, for example. In this case, in the present embodiment, the arithmetic circuit 11
In the delay circuit 12, a 4-bit shift register 29 for delaying a time equivalent to the arithmetic processing time of 4 clocks generated in
The control signal S ₁ is delayed and the control signal S ₂ is output.

When the arithmetic circuit 11 and the delay circuit 12 are provided in the digital video encoder 9 as described above, the arithmetic delay time generated in the arithmetic circuit 11 can be grasped at the design stage of the digital video encoder 9 and can be easily understood. The delay time of the delay circuit 12 can be set.

Therefore, if an image synthesizing device is constructed by using such a digital video encoder 9 and a receiving device is constructed by using this image synthesizing device, the design of the receiving device can be performed without considering the calculation delay time. This makes it possible to reduce the design man-hours.

Although the case where only one delay circuit 12 is provided in the digital video encoder 9 has been described in the present embodiment, the present invention is not limited to this, and a plurality of delay circuits 12 may be provided. . Also, the delay circuit 1
In the present embodiment, the number 2 is a 4-bit shift register 29.
However, the present invention is not limited to this.

[0041]

As described above, in the image synthesizing apparatus of the present invention, the conversion means (digital video encoder) calculates the digital video signal into an analog video signal and the calculation delay time generated in the calculation means. Since the delay means for providing a corresponding delay is provided and the control signal is delayed for synthesizing the image by this delay means, the image quality of the image can be improved even when the analog image signal and the digital image signal are synthesized. . Further, since the conversion means is provided with the delay means, it becomes possible to grasp the calculation delay time generated in the calculation means when designing the conversion means,
The delay time of the delay means can be easily set. Further, it is not necessary to provide a delay circuit in the image synthesizing device, and there is an advantage that the number of parts can be reduced and the parts cost can be reduced.

Further, since the receiving device is constructed by using the image synthesizing device in which such a calculation delay time is taken into consideration,
The receiver can be designed without considering the calculation delay time, and the number of design steps can be reduced as compared with the conventional case. Furthermore, when the conversion means is changed due to a design change or the like, the conversion means is provided with a delay means in the conversion means, so that there is an advantage that the design can be changed without considering the delay time.

[Brief description of drawings]

FIG. 1 is a block diagram of a receiving device including an image synthesizing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart in the case of synthesizing an analog video signal and a graphics signal.

FIG. 3 is a diagram showing a display example of a video signal combined by the image combining device of the present embodiment.

FIG. 4 is a diagram showing a configuration of a digital video encoder provided in the image synthesizing device according to the present embodiment.

FIG. 5 is a block diagram showing an example of a conventional image synthesizing apparatus.

FIG. 6 is a diagram showing a timing chart in the case of synthesizing an analog video signal and a graphics signal in a conventional image synthesizing device.

FIG. 7 is a block diagram showing an example of an image synthesizing apparatus provided with a conventional delay circuit.

[Explanation of symbols]

 1 Antenna 2 Television Tuner 3 Image Synthesizer 4 Graphics Signal Generator 5 Operating Unit 6 Cable TV Tuner 7 Image Decompressor 8 Selector 9 Digital Video Encoder 10 Mixing Circuit 11 Arithmetic Circuit 12 Delay Circuit 21 Synchronous Signal Generator 22 Demultiplexer 23, 24 low-pass filter 25 modulator 26, 27 adder 28 D / A converter 29 4-bit shift register

Claims (6)

[Claims] 1. A digital signal synthesizing means capable of switching and synthesizing two systems of digital image signals at a predetermined timing, and a converting means for arithmetically processing the output of the digital signal synthesizing means to convert into an analog image signal. An analog signal synthesizing unit capable of selecting and synthesizing an analog image signal output from the converting unit and an analog image signal input from the outside, wherein the converting unit converts the digital image signal into an analog image signal. And a delay unit for delaying a control signal supplied to the analog signal synthesizing unit so as to correspond to a calculation delay time generated in the calculating unit. Image synthesizer. 2. The image synthesizing apparatus according to claim 1, wherein one of the two systems of digital image signals is graphics data output from a user interface. 3. The image synthesizing apparatus according to claim 1, wherein one or more delay units are provided. 4. A receiving device to which a digital image signal and an analog image signal are input, a digital signal synthesizing unit capable of switching and synthesizing two systems of digital image signals at a predetermined timing, and the digital signal synthesizing unit. Conversion means for performing arithmetic processing on the output to convert into an analog image signal; and analog signal synthesizing means capable of selecting and synthesizing the analog image signal output from the conversion means and the analog image signal input from the outside. The converting means includes a calculating means for converting a digital image signal into an analog image signal, and a control signal supplied to the analog signal synthesizing means is equivalent to the calculating delay time generated in the calculating means. A receiving device comprising: a delay unit that delays. 5. The receiving apparatus according to claim 4, wherein one of the two systems of digital image signals is graphics data output from a user interface. 6. The receiving apparatus according to claim 4, wherein one or more delay units are provided.