JPH0993233A - Data signal transmission reception system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate manual operation by deciding the phase of a data identification clock signal automatically caused by the delay in a transmission line in the transmission reception system where data are sent synchronously with a clock signal from a receiver side and received data are identified and latched by the clock signal of its own equipment at the receiver side. SOLUTION: A counter 1 counts a prescribed time just after the system is started, a clock signal from a transmitter side 100 is looped back for that time and sent to a receiver side 200. A phase difference detection circuit 11 at the receiver side detects a phase difference between the looped-back clock signal and the clock signal in its own equipment to detect the delay in a transmission line 300. A selector 16 selects automatically whether the output of a latch FF12 by the noninverting clock signal or outputs of latches FF13, 15 by an inverted clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data signal transmitting / receiving system, and more particularly, a transmitting device transmits transmitting data in synchronism with a clock signal from the receiving device side, and a receiving device transmits this transmitting data to the clock in its own device. The present invention relates to a data signal transmitting / receiving system which is taken in in synchronization with a signal.

[0002]

2. Description of the Related Art An example of a conventional data transmission / reception system of this type will be described with reference to FIG. In FIG. 4, the transmitter 100 has a D-type flip-flop (hereinafter simply referred to as FF) 4 having a latch function.
Reference numeral 4 is for transmitting to the transmission line 300 while latching the transmission data in synchronization with the clock signal supplied from the receiving device 200 side via the transmission line 300.

In the receiving device 200, the transmission data from the transmission line 300 is latched by the FF 12 in synchronization with the clock signal and becomes one input of the selector 16 and the FF 13
Is latched in synchronism with the inverted signal of the clock signal by the inverter 14, and is further latched in synchronism with the clock signal by the FF 15 to be the other input of the selector 16.

FIG. 5 shows an example of waveforms of signals at respective parts of the block of FIG. 4. The waveforms of FIGS. 5A to 5D correspond to the waveforms of signals a to d of respective parts of the block of FIG. 4, respectively. And shows it.

The clock signal of the receiver 200 is shown in FIG.
In the case of (a), the clock signal delayed by the delay time t by the transmission path 300 is supplied to the clock input of the FF4 of the transmitter 100 as shown in FIG. 5 (b). Transmission data is identified by the FF4 by this clock signal and is latched and transmitted as transmission data as shown in FIG. 5C.

Since this transmission data is also delayed by the delay time t of the transmission path 300 and supplied to the receiving device 200, there is a phase difference of 2t from the clock signal in the receiving device 200, as shown in FIG. 5 (d). It becomes such a data signal.

In the receiving device 200, two kinds of clock signals of positive phase and negative phase are provided by the inverter 14 so that the rising edge (latch timing) of the clock signal does not approach near the change point (level transition point) of the received data signal d. Is prepared, and the received data is identified and latched by the FF12 and the FF13 and 15 respectively, and which latch output is suitable is observed with an oscilloscope or the like in consideration of the phase difference of the 2t. Meanwhile, the selector 16 is manually switched.

[0008]

In such a conventional data signal transmitting / receiving system, selection of a clock signal capable of identifying the data signal in the receiving device is measured by a measuring instrument such as an oscilloscope, and the clock signal is switched by manual operation. Has the disadvantage of being complicated.

An object of the present invention is to provide a data signal transmitting / receiving system which automatically selects a clock signal for data identification, thereby eliminating the complexity of manual operation.

[0010]

According to the present invention, a receiver for generating a clock signal and taking in received data in synchronization with the clock signal, and the supply of the clock signal from the receiver. A data signal transmission / reception system including a transmission device that receives the transmission data and transmits the transmission data to the reception device in synchronization with the clock signal, wherein the transmission device responds to power-on for a certain period of time. A clock signal supplied from the device is loop-transmitted to the receiving device, and thereafter, there is a transmitting means for transmitting the transmission data synchronized with the clock signal to the receiving device, and the receiving device is from the transmitting device during the certain period. Phase difference detection means for detecting the phase difference between the transmitted clock signal and the generated clock signal in the device itself, and the transmission data from the transmitter device to the generation clock. Clock signal, a first latch means for synchronizing with the clock signal, a second latch means for synchronizing with a reverse phase clock signal of the generated clock signal, and the first latch means according to the detection result of the phase difference detecting means. And a selecting means for selectively deriving the output of the second latch means, thereby providing a data signal transmitting / receiving system.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The operation of the present invention will be described. When the system is started, for example, when the power is turned on, the transmitting side loops back the supplied clock signal from the receiving side for a certain period of time and transmits it to the receiving side. Detects the phase difference between the transmitted clock signal and the clock signal in the device itself, and selects the data signal latched and discriminated as either the positive phase clock signal or the negative phase clock signal according to this phase difference. Therefore, the manual selection of the data signal is eliminated.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention, and the same parts as in FIG. 4 are designated by the same reference numerals. In FIG. 1, the transmitter 100 is provided with a selector 2, and the latch output of the FF 4 or the receiver 200 is provided.
Any of the clock signals supplied from the selector 2
And is transmitted to the transmission path 300.

A counter 1 is provided for the selection control of the selector 2, and the counter 1 counts the supplied clock signals and generates a switching signal when it reaches a constant value. In response to power-on at system startup, the selector 2 counts the clock signal supplied from the receiving device, and when the counter 1 reaches a predetermined value, it generates a switching signal so that the selector 2 selects the latch output of the FF 4. To control.

Further, a signal disconnection detection circuit 3 is provided so that the counter 1 is reset to return to the initial state when the clock signal supplied from the receiving device is disconnected.

In the receiving device 200, the FFs 12, 13, 1
5, a clock signal detection circuit 10 and a phase difference detection circuit 11 are provided in addition to the inverter 14 and the selector 16. The phase difference detection circuit 11 detects the phase difference between the clock signal of its own device and the clock signal returned from the transmitter 100, that is, the round trip delay time 2t of the transmission path 300.

The clock signal detection circuit 10 is a transmitter 10.
When the supply clock signal from 0 is no longer detected, the phase difference detection function of the phase difference detection circuit 11 is stopped. The other structure is the same as that of FIG. 4, and the description thereof is omitted.

FIG. 2 shows an example of a waveform of a signal transmitted from the transmission device 100 for explaining the operation of FIG. When the system is activated and the power is turned on, the transmitter 10
When 0 rises, the selector 2 first selects the clock signal supplied from the receiving device and transmits it to the transmission path 300, and the counter 1 starts counting the clock signal.
Since this state is maintained until this count value reaches the constant value A, the phase difference detection circuit 11
Operates to detect the phase difference between the clock signal of the device itself and the clock signal from the transmitter.

When the content of the counter 1 reaches a constant value A, the selector 2 selects the latch output of the FF 4 and transmits it to the transmission path 300. Phase difference or transmission line 30
The delay time 2t of 0 is detected, and this delay time 2t
Accordingly, the selection control of the selector 16 is performed.

When the count content of the counter 1 reaches the constant value A, the transmission of the clock signal from the transmitter is stopped, so that the clock signal detection circuit 10 detects this and the function of the phase difference detection circuit 11 is stopped. It

FIG. 3 shows the relationship between the timing of the received data DATA transmitted from the transmitter 100 and the timing of the identification clock signal in the receiver (A).
It is shown by three types of (C). (A) shows that the received data is latched to identify it at the rising timing of the clock signal.

(B) shows that due to the delay 2t of the transmission line 300, the rising timing of the clock signal is near the change point of the received data and the data identification is not performed correctly. Therefore, in this case, as shown in (C), the FF1 using the inverted clock signal as the latch timing.
If the selector 16 controls the data of the route 3 to be selected, the change point of the received data is separated from the rising timing of the inverted clock signal, and the received data can be correctly identified in the state close to (A). It will be.

The FF1 latched by the positive-phase clock signal
The reason why 5 is provided after the FF 13 is to align the data with the normal phase timing of the clock signal.

The phase difference 2t (t
Is a variable that varies depending on the distance of the transmission path 300), it is obvious that which latch output is selected may be determined in advance according to the phase difference.

Since the disconnection detection circuit 3 resets the counter 1 when the clock signal is disconnected, the phase difference detection circuit 11 can operate again when the clock signal is restored.

[0026]

As described above, according to the present invention, even if the changing point of the day signal and the rising point of the clock signal are close to each other in the receiving device due to the delay state of the transmission line, the phase difference is detected. Since the optimum one is automatically selected as the phase of the latch clock signal, the manual operation is not required. Further, since the clock signal is folded back from the transmitter for detecting the phase difference, it is placed on the head portion of the data signal, so that it is not necessary to specially provide a transmission path for folding the clock signal.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a waveform of a transmission signal from a transmission side to a reception side in the block of FIG.

FIG. 3 is a timing chart of waveforms showing the operation of the embodiment of the present invention.

FIG. 4 is a block diagram of a conventional data signal transmitting / receiving system.

FIG. 5 is a waveform chart of each part showing the operation of the block of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 counter 2, 16 selector 3 disconnection detection circuit 4, 12, 13, 15 FF 10 clock signal detection circuit 11 phase difference detection circuit 14 inverter 100 transmitter 200 receiver 300 transmission line

Claims (4)

[Claims] 1. A receiving device which generates a clock signal and takes in received data in synchronization with this clock signal; and a receiving device which receives the clock signal from the receiving device and synchronizes with this clock signal. A data signal transmission / reception system including a transmission device that transmits transmission data to the reception device, wherein the transmission device receives the clock signal supplied from the reception device for a certain period in response to system activation. To the receiving device, and then the receiving device has a clock signal transmitted from the transmitting device during the certain period of time and its own device. Phase difference detecting means for detecting a phase difference from the generated clock signal, and the transmission data from the transmitter is taken in in synchronization with the generated clock signal. A first latch means, said generated clock signal and the second latch means for taking in synchronization with the inverted clock signal, the phase difference of the first and second according to the detection result of the detecting means
And a selection means for selectively deriving an output of the latch means of the above. 2. The transmission means of the transmission device has a transmission selection means for transmitting the clock signal for the certain period of time and thereafter transmission data synchronized with the clock signal, respectively. Data signal transmission and reception system. 3. The transmitting means has a counting means for counting the clock signal in response to system activation, and when the counted value reaches a preset value, the transmission selecting means indicates the selected state. 3. The data signal transmitting / receiving system according to claim 2, wherein the switching is performed. 4. The data according to claim 2, wherein the transmitting means has a disconnection detecting means for resetting the counting means in response to the disconnection detection of the clock signal supplied from the receiving device. Signal transmission / reception system.