JPH01106620A - Differential signal receiver - Google Patents

Abstract

PURPOSE:To save power by acting ECL series gates like two comparators and an EOR circuit integrally so as to simplify the circuit constitution of the titled differential signal. CONSTITUTION:Signals of dual polarities (+ and -) are inputted to input terminals A, B of the differential signal receiver and fed to bases of transistors(TRs) Q1, Q2. A resistor R2 as a voltage drop setting means and a diode D2 as a level shift means are connected to the emitter of the TR Q2. Moreover, a resistor R1 and a diode D1 are connected to the emitter of the TR Q1, a prescribed reference voltage VCS is fed to bases of TRs Q10-Q12 to cause constant currents I1-I3 to flow through them respectively. The output of the TRs Q1, Q2 is fed to the base of the TRs Q3-Q8. Then whether or not the input signal exceeds negative and positive threshold values I2R1 and I3R2 being of dual polarity is discriminated to simplify the constitution of the differential signal receiver, thereby saving the power.

Description

[Detailed Description of the Invention] [Summary] Regarding a differential signal receiving device that receives a bipolar signal and outputs a unipolar signal, the present invention particularly aims to simplify the circuit and save power by reducing the number of transistors. two input terminals, each supplied with a differential input signal, for the purpose of measurement;
A voltage drop setting means for setting voltage drops corresponding to the positive and negative thresholds, respectively, and a level shifting means are connected to each base, and the emitters are commonly connected, and differentially applied to each base. a first transistor pair that determines whether the differential input signal exceeds the positive threshold based on an input voltage; and a common emitter is connected to the collector side of the first transistor pair, respectively; The two input terminals are connected to the respective base pairs via the voltage drop setting means, and are differentially input to each base, so that the differential input signal exceeds the negative threshold due to the voltage. and an ECL series gate consisting of a second and third transistor pair for determining whether or not the current is present.

[Industrial application field]

The present invention relates to a differential signal receiving device that receives a bipolar signal and outputs a unipolar signal, and the present invention relates to a differential signal receiving device that receives a bipolar signal and outputs a unipolar signal. It is used as a signal receiving device for a line in which signals encoded with bipolar codes are transmitted.

[Prior Art] A bipolar signal in -i is a signal in which the polarity of a pulse corresponding to data "1" is alternately inverted, as shown in FIG. 10(a), and a unipolar signal What is Figure 10(b)
As shown in FIG. 2, the pulses corresponding to data "1" have the same polarity. Note that such unipolar signals include a so-called binary code (a signal that holds a predetermined positive level as long as data "1" continues, and holds an O level as long as data "0" continues).

By the way, in a receiving device that converts such a bipolar signal into a unipolar signal, predetermined threshold values are set respectively on the positive side and reverse side of the bipolar signal, as shown in FIG. , it is necessary to configure the receiver to output data "1" when the received bipolar signal level exceeds the positive or negative threshold.

FIG. 12 shows an example of this type of receiving device in the prior art, in which a constant voltage source B corresponding to the above-mentioned positive threshold is connected to the B input terminal (- input terminals) side, and this is inverted. Comparator C5 to which voltage is input and A input terminal (
a comparator C2 to which a voltage connected to a constant voltage source B2 corresponding to the negative threshold value is input to the + side input terminal) side;
It is determined by these comparators C1 and C whether or not the bipolar signal input from the g5 A and B input terminals exceeds the positive or negative threshold.
Each output signal of 2 is subjected to a predetermined logic by an E-NOR (exclusive NOR) circuit G1, and the
The circuit is configured to receive a predetermined unipolar signal from the output side of the circuit.

[Problem that the invention seeks to solve]

However, in the circuit described above, two comparator circuits and a separate E-NO
Since an R circuit (or an E-OR circuit) is required, there is a problem that the number of circuits increases and the number of elements such as transistors and resistors increases, which is a big disadvantage especially when integrated into an IC.

The present invention was made to solve this problem, and aims to simplify the circuit and save power by reducing the number of elements such as transistors.

[Means for solving problems]

In order to solve this problem, the present invention provides two input terminals to which differential input signals are respectively supplied;
Voltage drop setting means (first
resistors RI, R2 in the embodiment shown, and level shift means (diodes DI, DI in the embodiment shown in FIG.
It is determined whether or not the differential input signal exceeds the positive threshold based on the voltage that is differentially input to each base with the emitters connected to each base via DZ) and commonly connected. A common emitter is connected to the collector side of the first transistor pair (Qff, C4 in the embodiment of FIG. 1) and the first transistor pair, respectively, and the two input terminals are connected to each other through the voltage drop setting means. second and third transistors connected to each pair of bases and determining whether or not the differential input signal exceeds the negative threshold based on a voltage differentially input to each base; Pair (first
Q, , Q, and Qt , Qs in the illustrated embodiment)
Provided is a differential signal receiving device comprising an ECL series gate consisting of.

[For production]

According to the above configuration, the ECL series gate has two comparator circuits and an E-OR circuit in the prior art.
Since it functions as an integrated circuit, it is possible to simplify the entire circuit and save power.

〔Example〕

FIG. 1 is a circuit diagram showing a differential signal receiving device as a first embodiment of the present invention, in which the A input terminal (
The above bipolar signals are input from the + side input terminal) and the B input terminal (- input terminals).

A resistor R2 as the voltage drop setting means and a diode D2 as a level shift means are connected in series to the emitter side of the emitter follower transistor Q2, and the voltage drop is connected to the emitter side of the emitter follower transistor Q, respectively. A resistor R8 as a setting means and a diode D+ as a level shift means are connected.

QIOIQll and Qlt are transistors each having a base supplied with a predetermined reference voltage ves and forming a predetermined constant current source, and each transistor Q. I
A constant current 1 . ．． 1. , and ■1 are flushed. Furthermore, each transistor Q1°.

Resistors R6, R, and R in series with Ql and Qlg.
8 is connected. Note that is a group of diodes (in the case shown, it consists of four diodes connected in antiparallel to each other) for clamping a large amplitude input signal when it is input. For example, there is an A input. When the voltage exceeds the level, the diode D is connected from the emitter side of the transistor Q2.

A predetermined current is supplied to the emitter side of the transistor Q+ through the transistor Q+, thereby ensuring that a predetermined constant current flows through each voltage drop setting means.

Next, each pair of transistors Q3 whose emitters are coupled to each other. Qh, Qt, and QI are provided, and the emitter potential of the emitter follower transistor Q2 is supplied to the bases of the transistors Q, QI, and the resistor R1 and the transistor Q are supplied to the bases of the transistors Qb and Qt. , the potential at the connection point with , is supplied. On the other hand, each of the bases of a pair of transistors Qs and Qa, which are emitter-coupled to each other and form a series gate with each transistor pair Q, Q, and Qt, is connected to the resistor R2 and the transistor Q1°, respectively. The potential at the connection point and the potential at the connection point between the diode D1 and the transistor Q1□ are supplied. Q is a transistor for flowing a predetermined constant current ■4 to the series gate,
A resistor R2 is connected in series with the transistor Q.

Furthermore, the collector sides of the transistors Q and Q7 and the resistor R
The potential at the connection point with 5 is supplied to the base of the transistor Ql3 (A), and an output Y is taken out from the emitter side of the transistor (ILs).On the other hand, the transistor Q,
The potential at the connection point between the collector sides of and Q and the resistor R1 is supplied to the base of the transistor Q14, and the transistor (
Output X is taken out from the emitter side of lLa.

Now, the base potential of each transistor Q to Q constituting the series gate is . , to V,. Then, the following equations (1) to (4) hold true.

V@31 ”Vin(A) -Vat(Qz)-Vat
(Di)-Rzl,・”(1)V@4m=Vin(
B) -VIE(Ql)-VIIE(DI)=
(2) Vosw=Voss=Vin(A) Vsi(
Qz) ...'(3) V@Bl= V(1?l
= Vin(B) Vat(Qt) −R+Iz
(4) Therefore, the following equations (5) to (7) are further established from the above equations (1) to (4). However, VIE (
Ql) = Vat(Qt), Vat(DI) =
Let V at(Ih).

V@31 VO4m = Vin(A) Vi
n(B) RzIs =・(5) VaslI-V
ois+ = Vin(A) Vin(B) +
R+Iz...(6) VOIII VO? l
=Vin(A) Vin(B) +R+I
g...(7) Here Vin(^), Vin
(B) are the A input voltage and the B input voltage, respectively,
VBE(Ql) and Vllt(Qz) are the base-emitter voltages of transistors Q+ and Qz, respectively, VBE(Dυ, ■1lE(D2) are the voltage drops occurring in diodes D, D, respectively, and RzIs
and R, I2 are voltage drops occurring across resistors R2 and R8, respectively, and correspond to a positive threshold value and a negative threshold value, as will be described later.

Therefore, the amplitude value (Vin(A)
-Vin(B)) does not reach the positive or negative threshold, that is, R+Iz<Vin(A)
When Vin (B) < Rzls, the above (5)
From the formula, VOIII < Vaaa, and the above (7
) formula, V(1?l<V..), and Q4 and Q of each emitter-coupled transistor pair turn on, and current flows through the path shown by ■ in Figure 1, increasing the resistance. The voltage drop across R4 causes transistor Q1 to
The base potential of transistor Qlff, and therefore the X output on its emitter side, becomes low level, while the base potential of transistor Qlff, and therefore the X output on its emitter side, becomes high level.

Next, the above V 1n(A) −V 1n(B) is the threshold value R1 on the positive side! When it exceeds , that is, Vin(A) −Vin(B) > Rzl, from the above equation (5), ■. 311 >VO4! It becomes l,
Also, from the above equation (6), ■. 8m>V. 4. Q3 and Q of each emitter-coupled transistor pair.

is turned on, current flows through the path shown in (■) in FIG. 1, and the voltage drop generated across the resistor R1 causes the transistor Q1. The base potential of transistors Q and 4, and therefore the X output on the emitter side thereof, are at a low level, while the base potential of the transistors Q and 4, and therefore the X output on their emitter side, are at a high level.

Further, when the above V 1n(A) −V 1n(B) exceeds the negative threshold value −R,1, that is, when Vin(A) −Vin(B) <−RII2, the above (5) is applied. Therefore, VQ31 < Vaaa, and from the above equation (7), ■. □〉v, lll, and Q of each emitter-coupled transistor pair
, and Q7 are turned on, current flows through the path shown by becomes low level, and the X output becomes high level.

Figure 2 shows the operating characteristics of the circuit shown in Figure 1 above, where the differential input voltage (V 1n(A) -V 1n(B))
This indicates that the X output is at a low level when it is within the range of the positive and negative side thresholds, and the X output is at a high level when it exceeds the positive or negative side thresholds. FIG. 3 shows how the differential input signal (a bipolar signal) is converted into a unipolar X output. Note that the current paths (1) to (2) at each point in time shown in FIG. 3 correspond to the current paths (1) to (2) shown in FIG. 1 above.

4 to 8 show other embodiments of the differential signal receiving device according to the present invention. In the circuit shown in FIG. 4, the differential threshold shown in FIG. 1 is determined. A diode D with a constant voltage drop instead of the resistor RI, Rt
In the circuit shown in FIG. 5, level shift diodes D, Ds are used to prevent saturation of the transistor pair below the series gate shown in FIG. Instead, resistors RA and RB are used, and in the circuit shown in FIG. By providing this, the circuit through which the constant current (1) flows can be omitted.

The operating characteristics of the circuits shown in FIGS. 4 to 6 are the same as those of the circuit shown in FIG.

Further, in the circuit shown in FIG. 7, a current mirror circuit consisting of transistors TP1 to TP3 is provided on the collector side of transistors Q and Q7, and when the X output is at a high level, the transistors TPI and T
Currents IH1 and IH2 flow through the respective transistors TPI and TP2 according to the values of the resistors R, l and R3'' connected to P2. Note that when the values of the resistors R% and R3'' are equal, IH1 =IH2. Therefore, when the X output is at a high level, the current flowing through each resistor R3 and R2 is I
HI and IH2 are decreased to become (I, -IHI) and (L-IH2), and a hysteresis characteristic as shown in FIG. 9 can be provided. In other words, when the X output is at a high level, the positive and negative thresholds are
They are decreased by IH2XR2 and IHIXR+, respectively, compared to when the output is at a low level. Note that in this case, one of the transistors TPI and TP2 may be omitted.

Further, the circuit shown in FIG. 8 shows another embodiment for providing such a hysteresis characteristic, in which currents IHI and IH2 flowing through the transistors TP1 and TP2 are connected to resistors R7 and Rh, respectively, when the X output is at a high level. The current flowing through the resistors R1 and R6 is increased by IHI and IH2 compared to the case of FIG. The voltage VCS is constant) is decreased, and as a result, the current value flowing through the resistors R1 and R2 when the X output is at a high level is decreased compared to when the X output is at a low level. It is possible to provide the same hysteresis characteristic (shown in FIG. 9) as in the case of .

〔Effect of the invention〕

According to the present invention, two comparator circuits and an E
The -OR circuit (or E-NOR circuit) can be integrally configured with ECL series gates, and the number of elements such as transistors can be reduced to simplify the entire circuit and save power.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a differential signal receiving device as a first embodiment of the present invention, FIG. 2 is a diagram showing operating characteristics of the circuit in FIG. 1, and FIG. 3 is a diagram showing the operating characteristics of the circuit in FIG. 4 to 8 are circuit diagrams showing differential signal receiving devices as second to sixth embodiments of the present invention, and FIG. 9 is a diagram showing the relationship between input and output signals of the circuit. Figures 7 and 8 show the operating characteristics of the circuits; Figures 10 (a) and (b) are diagrams showing the waveforms of a bipolar signal and a unipolar signal; and Figure 11 shows the bipolar signal and reception. FIG. 12 is a block diagram illustrating a differential signal receiving device in the prior art. (Explanation of symbols) B,, Bz...Battery that determines the positive and negative thresholds, C,, C! ...Comparator, G1...E-NOR circuit, D3...Diode for large amplitude input signal clamp, VC
S... Voltage for constant current source, TPI to TP3... Current mirror circuit.

Claims (1)

[Claims] 1. Two input terminals to which differential input signals are respectively supplied, and voltage drops between the two input terminals corresponding to positive and negative thresholds, respectively, are set. The differential input signal is connected to each base through a voltage drop setting means and a level shift means, and whose emitters are connected in common, and which is differentially input to each base to cause the differential input signal to change to the positive threshold value. A common emitter is connected to the collector side of the first transistor pair and the collector side of the first transistor pair, respectively, and the two input terminals are connected to the respective bases through the voltage drop setting means. second and third circuits connected in a pair and determining whether or not the differential input signal exceeds the negative threshold based on the voltage differentially input to each base;
1. A differential signal receiving device comprising: a pair of transistors; and an ECL series gate consisting of a pair of transistors. 2. The voltage drop setting means consists of a resistor and a current source, and by changing the current value of the current source flowing through the resistor depending on the output state of the ECL series gate, the positive side and negative side thresholds are set. The differential signal receiving device according to claim 1, wherein the differential signal receiving device has a hysteresis characteristic. 3. The differential signal receiving device according to claim 1, wherein the differential input signal is a bipolar signal, and a unipolar signal is output from the output side of the ECL series gate.