JPH01123470A - Semiconductor device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, to a semiconductor device suitable for application to a transistor having a structure in which an electrode is taken out from the side wall of a convex semiconductor region. The present invention relates to a device and its manufacturing method.

[Conventional technology]

The operating speed and power consumption, which are the basic indicators for expressing the performance of semiconductor integrated circuits, are based on the current value of the transistor used and the capacitance of the element, including the parasitic elements that need to be charged and discharged by this current. Determined by For a given current value, the power required to operate the transistor is proportional to this capacitance value, so the smaller the capacitance value, the better the performance.

A first example of a conventional semiconductor device will be described below with reference to FIG.

In bipolar transistors, in order to reduce the parasitic capacitance between the base and collector and increase the operating speed, a structure is known in which the lead electrode is taken out from the sidewall of the base and the base and collector are separated using an insulating film, which was previously redundant. It is. Examples of this type of device include, for example, JP-A-56-1
No. 556, Japanese Patent Application Laid-open No. 161867/1983, Japanese Patent Application No. 211568/1982, and Japanese Patent Application No. 308374/1984. An example of a conventional bipolar transistor having such a structure is shown in FIG.

In FIG. 2, 1 is a P-type Si single crystal substrate whose main surface is a (100) plane, 100 is a lateral PNP transistor, 1
01 is a vertical NPN transistor, 2 is an N+ type buried layer,
61 is a buried insulating film made of a SiO2 film, and 8.9 and 10 are P+ type diffusion layers, which are the emitter region and collector region of the horizontal PN and P transistors 100, and the graft base region of the vertical NPN transistor 101, respectively.

11 is a P-type diffusion layer region, and a vertical NPN transistor 10
1 is an intrinsic base region, 12 and 15 are an N+ type emitter region and an N+ type collector region, respectively, of the vertical PNP transistor 101. 71 is an emitter extraction electrode of a lateral PNP transistor 100 made of polycrystalline Si;
7 is a collector lead-out electrode of the horizontal PNP transistor 100, and also serves as a base lead-out electrode of the vertical NPN transistor 101. 13 is vertical NPN transistor 1
01 is an emitter extraction electrode, and 14 is an insulating film. 16
．． 17. 1-8 and 19 are composed of metal films mainly made of A material, and each has a horizontal PNP transistor 1oo
Emitter electrode, collector electrode.

These are the emitter electrode and collector electrode of the vertical NPN transistor 101. In addition, horizontal PNP transistor 1
The collector electrode 17 of 00 is the vertical NPN transistor 1
It also serves as the base electrode of 01.

In a known bipolar transistor having a structure as shown in FIG.
The base-collector junctions other than the active region of the lateral PNP transistor 100 and the base-collector and base-emitter junctions of the lateral PNP transistor 100 are all thick insulating films 61.
The parasitic capacitance is extremely reduced.

Furthermore, a graft base 10 composed of a P+ type diffusion layer
Since the N+ type buried layer 2 is also formed on the buried insulating film 61, the shortest path between the N+ type buried layer 2 acting as a collector is increased, and the base-collector breakdown voltage is improved. Therefore, the transistor having the structure shown in FIG. 2 has the advantage of achieving high breakdown voltage and high speed operation.

Next, a second example of a conventional semiconductor device will be described with reference to FIG.

The second conventional example is a MOS transistor having source/drain extraction electrodes on an insulating film, for example,
It is described in Japanese Patent No. 237471, etc., and has a cross-sectional structure as shown in FIG.

In FIG. 7, reference numeral 1 denotes a P-type Si single crystal substrate, the main surface of which is usually a (100) plane from the viewpoint of reducing surface states. 200 is an element isolation insulating film, 30 is a gate insulating film, 40 is a gate electrode, 50 is a gate protection insulating film, and 80 is a gate sidewall insulating film. 91 is a source extraction electrode, 92 is a drain extraction electrode, 710 is a buried insulating film, and 110 and 111 are source expansion rp!
lJI, bell rain diffusion layer; 130 and 140 are a source electrode and a drain electrode, respectively. In the conventional structure MOS transistor shown in FIG. 7, the buried insulating film 710 can be made sufficiently thick.

It has the feature that the parasitic capacitance component based on the source-drain junction capacitance can be sufficiently reduced compared to a normal structure MOS transistor, and high speed operation is possible.

[Problem that the invention seeks to solve]

In the first conventional bipolar transistor having the structure shown in FIG. 2, the thick buried insulating film 61 is
■Selective oxidation of the groove bottom portion etched in the direction perpendicular to the main surface of the semiconductor substrate 1 by sputter ion etching;
■Selective oxidation of the groove bottom surface that is further isotropically etched, ■
It was formed by selectively implanting ions into the groove bottom to make the single crystal region amorphous in the shape of a water drop, and then selectively oxidizing the surface from which this amorphous region was selectively removed. Above ■
In any of the methods described in (1) to (2), it is not possible to extend the buried insulating film 61 sufficiently in the lateral direction so as to position it under the graft base 10, and thus the method has not been put to practical use. Above■
In the above method, the growth rate of the oxide film of the buried insulating film 61 is much faster than the growth rate of the oxide film of the buried insulating film 61, so that the growth rate of the graft base 1o, which is formed using the base extraction electrode 7 as a diffusion source, during the manufacturing process is much faster. With the current technology, it is almost impossible to form a buried insulating film 61 in the lower part. Based on the method (2) above, by increasing the amount of isotropic etching, it is possible to sufficiently extend the region in which the buried insulating film 61 is formed in the lateral direction. However, since the openings also grow in the vertical direction, there are problems such as needlessly corroding the N+ type buried layer 2, increasing collector resistance, and impairing miniaturization. In the above method (2) in which the buried insulating film 61 is laterally extended in the single crystal substrate 1, the degree of lateral extension is based on the lateral spread characteristics of the amorphous layer due to ion implantation, and is unique depending on the ion implantation conditions. determined. However, the lateral extent of the desired dimensions, especially the number 1
In order to achieve a lateral spread of 100 nm or more, it is necessary to use a high-energy, high-current ion implanter with an acceleration energy of several hundred keV to several megaeV, which has the disadvantage of being cheap and not easy to manufacture. there were. Further, secondary defects caused by high-energy, large-current ion implantation are induced in the single crystal substrate 1 from which the amorphous layer has been selectively removed, which tends to cause problems such as increased leakage current and deterioration of electrical characteristics.

Furthermore, in the second conventional MOS transistor shown in FIG. 7, the buried insulating film 710 is based on selective oxidation of the etched region of the Si substrate 1 using the gate electrode 4 as a mask.

Therefore, in the Si substrate region below the gate electrode 4, a buried insulating film is not disposed up to the sidewalls of the source/drain junction, and it has been impossible to realize such a structure.

The structure of the buried insulating film 710 was evaluated based on a numerical analysis method from the viewpoint of improving the performance of ultra-fine MoS transistors, particularly high breakdown voltage and large current, and the results found will be described. That is, in the structure of the buried insulating film 710 at the bottom of the source/drain junction as in the conventional structure, although the effect of reducing the parasitic capacitance is produced, the effect of alleviating the strong drain electric field is not obtained at all. Therefore, M of the very short channel
In an oS transistor, conventional structures are not effective at all in improving short channel effects and punch-through breakdown voltage reduction phenomena caused by strong drain electric fields. Ultra short channel M
From the viewpoint of improving the short channel effect of the OS transistor and the punch-through breakdown voltage, it is desirable to form a thick insulating film on the side surface of the drain junction to absorb a strong drain electric field.

In the conventional technique shown in FIG. 7, the region where the drain junction side surface is to be formed is selectively removed by etching using a fluoro-nitric acid mixture or microwave etching, and then an insulating film is buried in the same region by thermal oxidation or deposition. can also be considered. However, in the above method, etching progresses in the same direction and there are problems with controllability, so there are inherent drawbacks such as etching up to the semiconductor substrate portion corresponding to the channel region or insulating the same region. This is not practical.

An object of the present invention is to provide a convex semiconductor region formed on a surface region of a semiconductor substrate, a buried insulating film formed on the surface of the semiconductor substrate on at least both sides of the bottom of the convex semiconductor region, and a convex semiconductor region formed on the surface of the semiconductor substrate. A semiconductor device comprising: an extraction electrode layer formed on the buried insulating film and in contact with a sidewall of the region; and an impurity doped region formed on the sidewall of the convex semiconductor region in contact with the extraction electrode layer. , a structure in which the end of the buried insulating film formed at the bottom of the side wall of the convex semiconductor region extends sufficiently toward the center of the convex semiconductor region from the end of the impurity doped region. It is about realization.

Furthermore, to describe the purpose of the present invention in more detail, in a bipolar transistor, a buried insulating film separating a graft base and a heavily doped buried collector diffusion layer can be formed in a desired region in a desired lateral direction without impairing miniaturization. The object of the present invention is to provide an ultra-fine, ultra-high-speed bipolar transistor that expands inward, has good controllability, and can be constructed using a simple manufacturing method.

Furthermore, in a MOS transistor having source/drain extraction electrodes on an insulating film, a thick insulating film with good controllability is formed on the side surface of the drain junction in the semiconductor substrate directly under the gate electrode in a self-aligned relationship with the gate electrode. .

[Means for solving problems]

In order to achieve the above object, the semiconductor device of the present invention includes a convex semiconductor region formed on a surface region of a semiconductor substrate, and a convex semiconductor region formed on the surface of the semiconductor substrate on at least both sides of the bottom of the convex semiconductor region. A buried insulating film, an extraction electrode layer that is in contact with a sidewall of the convex semiconductor region and formed on the buried insulating film, and an impurity formed on a sidewall of the convex semiconductor region that is in contact with the extraction electrode layer. doped region, and the surface of the semiconductor substrate at the bottom of the buried insulating film has a (111) plane.

The method for manufacturing a semiconductor device of the present invention also includes a step of performing first vertical etching on a semiconductor substrate to form a groove to form a convex semiconductor region, and a step of forming a side wall of the convex semiconductor region with oxidation-resistant etching. A step of selectively forming a film, a step of performing a second vertical etching on the semiconductor substrate to deepen the groove, and an anisotropic etching step, in which the etching progresses in the (110> axial direction to form the convex portion). forming a groove that bites into the bottom of the side wall of the shaped semiconductor region and whose bottom semiconductor substrate surface has a (111) plane; and forming a buried insulating film on the surface of the groove on at least both sides of the convex semiconductor region. It is characterized by including a process.

Furthermore, the means of the present invention will be described in detail in a semiconductor device having a bipolar transistor.

Using a semiconductor substrate with a (111) main surface, a graft base is constructed in the 110>axis direction, not perpendicular to (111). A buried insulating film is formed in the lower part of the graft base having the above structure in self-alignment with the region where the emitter is to be formed. Also, (11
1), and the active region in the 211> axis direction that is not perpendicular to the (110) plane is defined by the element isolation region.

In the structure of the buried insulating film described above, the first vertical etching is performed using the area where the emitter is to be formed as an etching mask (
111) Apply to the main surface of the semiconductor substrate to form a groove. After selectively leaving the oxidation-resistant coating only on the side walls of the groove,
After performing a second vertical etching on the bottom of the groove, dorazine (N 2 H4) or potassium hydroxide (KO
H) Perform anisotropic etching using an aqueous solution or the like. In the above anisotropic etching, etching hardly progresses in the <111> axis direction, and etching progresses in the (110> axis direction perpendicular to [111], so the bottom surfaces of the first and second grooves are connected to the ceiling, In the back wall as a floor, horizontal holes having a (110) plane perpendicular to the main surface of the semiconductor substrate are formed in the semiconductor substrate below the emitter formation area in a self-aligned manner with the edges of the emitter formation area, that is, at regular intervals. Although the side wall of the horizontal hole is in the <211) axial direction, the progress of etching in the side wall direction stops at the stage where the (111) plane is exposed.
It does not advance to about 1/3 of the horizontal hole height. After forming a horizontal hole of a desired depth, the area where the surface of the semiconductor substrate is exposed other than the portion where the oxidation-resistant film remains is oxidized to form a thick insulating film on each surface of the horizontal hole. After selectively removing the oxidation-resistant film remaining on the groove sidewalls, a semiconductor device is manufactured by a conventionally known method such as forming a base lead-out electrode.

Further, in a semiconductor device having a MOS transistor, a semiconductor substrate with a (111) main surface is used, and a gate electrode is formed in a direction such that the source/drain direction is (110> perpendicular to the l:111) direction.Train region In this step, a first vertical etching process is performed on the semiconductor substrate using the gate electrode as the edge of the etching mask to form a groove.After selectively leaving an oxidation-resistant film only on the sidewalls of the groove, a second vertical etching process is performed on the semiconductor substrate in the groove part. After vertical etching of hydrazine (N 2 H4) - or potassium hydroxide (
KOH) using an anisotropic etching solution such as an aqueous solution (11
Etching is selectively progressed only in the 110> direction, not perpendicular to 1). In the above etching, the etching speed of the (111) plane is extremely slow, and the first groove bottom surface and the second groove bottom surface are used as the ceiling and the floor, respectively, and the back wall is a horizontal hole made of the (110) plane perpendicular to the main surface of the semiconductor substrate. is formed.

The side wall of the above-mentioned horizontal hole is not perpendicular to the (111) direction but in the 211〉 direction, but the etching in the side wall direction is approximately 17 mm above the horizontal hole height.
It does not progress beyond 3. After forming a horizontal hole of a desired depth, oxidize the semiconductor substrate portion other than the portion where the oxidation-resistant film remains,
A thick insulating film is formed on the wall of the side hole, and the insulating film is embedded in the side wall of the drain junction. After removing the oxidation-resistant film left on the trench sidewalls, a polycrystalline or amorphous semiconductor thin film is selectively left in the drain region to serve as a drain extraction electrode. The train lead-out electrode is connected to the semiconductor substrate at the sidewall of the groove near the surface of the semiconductor substrate where the oxidation-resistant film remains, and the lower sidewall and bottom of the groove are provided in contact with the buried insulating film. Based on the above method, the drain junction sidewall portion formed inside the semiconductor substrate directly under the gate electrode, excluding the channel region, can be replaced with a thick insulating film with good controllability.

In particular, in the case of a MOS transistor, the (100) plane is better as the main surface of the semiconductor substrate because the surface wall density is low and carrier mobility is high. However, as the gate length becomes shorter (gate length less than 1), due to the strong drain electric field, the operating speed of the MO8 element is determined by carrier mobility and velocity saturation, taking carrier mobility into account. There's no need to. In addition, the conventional method for processing semiconductor substrates into chips was mechanical scribing, so the (100) plane was convenient for the main surface of the semiconductor substrate, but now it has been changed to dicing. ,(
111) There are no problems at all in terms of surface or processing.

[Effect]

In the above method, the essence of the present invention is to use a (111) wafer as the semiconductor substrate (not limited thereto, as will be described later) and to use the surface orientation dependence of the etching rate by the anisotropic etching method. In the anisotropic etching method, (111
) The etching speed of the surface is extremely slow. Therefore, when selectively forming horizontal holes in a semiconductor substrate,
After forming holes perpendicularly from the surface of the (111)-plane wafer to a desired depth from the wafer surface by sputter ion etching, etc., the holes are formed on the wall surface of the hole except for the desired depth of the hole, that is, the area where the horizontal hole is to be formed. What is necessary is to form a protective film such as an insulating film and perform anisotropic etching. As a result of the above, the bottom and ceiling surfaces of the horizontal hole formed are parallel to the main surface of the board (11
1) The surface is exposed and preserved with extremely high precision in the depth direction of the side hole, and the ceiling height is maintained throughout the side hole at the height of the entrance of the side hole at the start of etching. By using the above characteristics, it becomes possible to leave an extremely thin single crystal layer of 0.1 p or less from the main surface of the semiconductor substrate or plate with good controllability. The above anisotropic etching does not cause any defects such as defects in the single crystal thin layer.

Therefore, by forming an insulating film so as to fill the opening of the side hole, a silicon-on-insulator (SOI) structure in which a single crystal thin film without crystal defects is formed on the insulating film can be easily realized with high precision.

In the conventional method, which is based on the epitaxial formation of a semiconductor thin film on an insulating film, the occurrence of crystal defects has always been a problem in the <SOR structure, but based on this method, various problems related to crystal defects can be fundamentally solved. be done.

If the above method is applied to a bipolar transistor, particularly a transistor having the structure shown in FIG. 2 and capable of operating at an ultra-high speed, the withstand voltage between the base and the collector can be greatly improved, and therefore the operating speed can be further increased. In other words, it is possible to arbitrarily increase the shortest path between the P1 type graft base and the N+ type buried diffusion layer by extending the buried insulating film of the desired shape to the desired location based on this method, and the withstand voltage can be improved. easily realized.

In addition, if the above characteristics are used, 0.1
- It is possible to form a horizontal hole while leaving a thin semiconductor substrate layer with a uniform thickness on top within the semiconductor substrate in the following depth region with good controllability. By combining the formation of an insulating film, the semiconductor substrate region except for the thickness component of the channel region of the MO3 field transistor can be replaced with an insulating film. In the MO8 field effect transistor having the above structure, a material having a dielectric constant smaller than that of the semiconductor substrate can be used as the insulating film on the drain sidewall, so that the phenomenon in which a strong drain electric field is applied to the semiconductor substrate can be avoided. It can be relaxed. In addition, modulation of the gate electric field by the strong drain electric field,
That is, since the short channel effect can be alleviated, it is possible to realize an ultrafine transistor that has a high punch-through breakdown voltage and has a threshold voltage that is less dependent on the gate length.

According to the present invention, the bottom and ceiling surfaces of the horizontal hole are constructed parallel to the main surface, but if the direction of the horizontal hole is set to 110> instead of perpendicular to [111], the inner surface can be constructed perpendicular to the main surface. Therefore, in the formation of a horizontal hole that is self-aligned with the end of the gate electrode, the above characteristics are particularly advantageous when applied to an MO8 type transistor having an ultra-fine gate length.

That is, since the inner surface of the horizontal hole or its oxidized surface can be formed uniformly in the depth direction of the substrate, the position of the drain sidewall insulating film can be set and controlled with high precision. In the above settings, the side wall surface of the horizontal hole is (211). If an element isolation insulating film is formed on the side wall surface of the side hole in advance, the side wall portion of the side hole is determined by the above insulating film.

According to the present invention, the bottom and ceiling surfaces of the horizontal hole to be formed are configured parallel to the main surface, but if the depth direction of the horizontal hole is set not perpendicular to (111) in advance but in the 110>axis direction, the back wall can be configured perpendicular to the main surface.

In the above settings, the (211) plane becomes a vertical plane in the side wall of the side hole, but the (211) plane is not preserved and the (111) plane is exposed, so that the cross section of the side hole has an enviable shape. If an inter-element isolation insulating film or the like is installed on the side surface of the side hole in advance, the side wall of the side hole can be determined by the above-mentioned insulating film.

In the above-mentioned horizontal hole formation, the ceiling and bottom surfaces are arranged parallel to the main surface while maintaining the predetermined depth. This is the basis for leaving it in place with good controllability. The present inventors focused on the relationship between the above-mentioned anisotropic etching mechanism and the surface energy of crystal planes, and conducted further detailed studies on various crystal planes centered on the (111) plane. The surface energy was calculated as the product of the bond energy and the number of bonds (dangling bonds) on the crystal plane. The calculated surface energy is (ill) plane is 1.45 x 10
13e r g/cr&, from the <111> axis (110
> Approximately 1.5X1 on the (332) plane tilted approximately 10° in the axial direction
013e rg/aK, also 16 @ tilted (221)
1.6 x 1013e r gal, also 2
1.75X10" e r on (331) plane tilted 2 degrees
gral, 11° from the <111> axis to the <001> axis direction
Tilt (1.55X10"erg/aJ on 2233 sides,
2 on the (113) plane also tilted by 30°. I x 10”
It's er glal. In addition, 90° with the 111〉 axis
1.80XIO13erg/cn on inclined (110) surface
f, (1oO) plane 2.55X 10"e r gla
l, the surface energy is <111> from the above calculation results.
When expressed as a function of the slope O from the axis, 1θ1 × 20
It was revealed that the temperature showed a pot bottom tendency at °, and the relationship was almost proportional to θ at l 01>20'. Furthermore, the dependence of the etching rate by hydrazine on crystal plane orientation and its relationship with surface energy were investigated.

The etching speed for (332), (223) planes, etc. is (11
1) Like the surface etching speed, it was extremely slow. On the other hand, the etching speed for (331) and (113) planes is approximately 1/2 of that for (110) planes, and for (100) planes.
The etching progresses in the same way as the surface! It was noticed.

From the above results, the anisotropic etching mechanism has a correlation with the surface energy of the crystal plane, and the (111) surface energy is the lowest, and the inclination from the (111) plane is 20.
It was found that the anisotropic etching rate becomes extremely slow for each crystal plane whose surface energy is as low as the (111) plane.

That is, the spirit of the present invention is that (11
1) The present invention is not limited to planes, but the present invention applies to semiconductor substrates whose main surface is a (111) plane, that is, a crystal plane (h, , Q) with an inclination of 20″ or less with respect to the <111> axis. Based on this, the ceiling surface and the bottom surface can be configured to be parallel to the main surface in a predetermined depth region.

In other words, an extremely thin single crystal layer can be left on the buried insulating film with good reproducibility and controllability if the single crystal semiconductor substrate has the (h, ni, fi) plane having the following relationship.

〔Example〕

Hereinafter, the present invention will be explained in more detail with reference to Examples.

For convenience of explanation, the explanation will be made using one drawing, but please note that important parts are shown enlarged.

In addition, in order to simplify the explanation, the materials of each part, the conductivity type of the semiconductor layer, and the manufacturing conditions will be specified, but the materials, the conductivity type of the semiconductor layer, and the manufacturing conditions are not limited to these. Needless to say.

Example 1 FIGS. 3A to 3H are cross-sectional views showing a first example of a semiconductor device according to the present invention in the order of manufacturing steps.

First, as shown in FIG. 3(A), P conductivity type, resistivity 1
0Ω・1, a known s on the Si substrate 1 whose main surface is (111)
Depth 1p, impurity concentration 3X I by thermal diffusion method of b
An N+ type buried layer 2 of "O19e1m-" is selectively formed. Next, an epitaxial layer 3 with a thickness of 0.84 mm is grown on the entire surface. After that, a 50 nm thick layer is formed on the surface of the epitaxial layer 3 by thermal oxidation. S i O, film 2o, thickness 120n by chemical vapor phase reaction (hereinafter referred to as CVD) method
Si of m.

N4 film 21 and S with a thickness of 900 nm by CVD method.
In, the film 22 was sequentially formed (FIG. 3(A)).

From the state shown in FIG. 3(A), the laminated insulating films 20 to 22 were patterned by a known photoetching method, and then the epitaxial layer 3 was also etched to a depth of 0.3p at the same time.

Etching of the epitaxial layer 3 was performed by reactive ion etching only in the direction perpendicular to the main surface of the Si substrate 1 (FIG. 3(B)).

From the state shown in Figure 3(B), a 30 nm thick 5in2 film made by thermal oxidation method, a 120 nm thick Si, N film made by CVD method,
A polymerized film 23 of the film was formed on the entire surface.

Thereafter, the overlapping film 23 formed on the plane parallel to the main surface of the substrate 1 is selectively etched by reactive ion etching (hereinafter referred to as RrE), leaving only the sidewalls of the pattern. Subsequently, using the patterned laminated insulating films 20 to 22 as a mask, the exposed epitaxial layer 3 was vertically etched to a depth of 0.3 - by RIE (FIG. 3(C)).

From the state shown in Figure 3 (C), an etching solution containing 80% hydrazine hydrate, isopropa, tolu, and 1% Triton X (trade name: surfactant) mixed in a ratio of 200:20:1 was used. The solution was treated at a temperature of 60° C. for 25 minutes to form a horizontal hole having a depth of 0.3 − as shown in FIG. 3(D). The depth direction of the horizontal hole, that is, the direction parallel to the paper surface of the drawing, is the (01T1 plane direction). In the above etching, almost no etching progressed in the (111) plane direction perpendicular to the main surface.
22 in the O2 film 22. The N4 film 23 was also not corroded at all. (211) In the axial direction, that is, in the direction perpendicular to the plane of the drawing, etching progresses to 1/3 of the height of the horizontal hole, approximately 1-etching, and stops at a (Tll) plane inclined from the main surface. Note that this etching does not need to be performed using the hydrazine aqueous solution (1).
For example, it may be based on an anisotropic etching solution such as an aqueous potassium hydroxide (KOH) solution, or a gas phase dry etching method. After forming a side hole using the hydrazine aqueous solution, the Si and N4 films 23 remaining on the side walls of the region where the collector was to be formed were selectively removed by microwave dry etching (FIG. 3(D)).

From the state shown in FIG. 3(D), in order to make the edges of the side holes smooth, the exposed surface of the Si substrate 1 was heated with a mixture of hydrofluoric acid and nitric acid in a ratio of 1:1.
Etching was carried out in the same direction by about 0.1//1 m using a solution of No. 00. Thereafter, a 0.3-thick Sin film was formed on the exposed Si substrate by selective thermal oxidation using the single overlapping film 23 as an oxidation prevention film to form the buried insulating film 6. Next, the polymer film 23 used as an oxidation-inhibiting film was selectively removed using a phosphoric acid solution heated to 180°C. Here, Si, N4
The film 21 was also etched at 0.37/In from the edge. Subsequently, a polycrystalline (or amorphous) Si film 70 with a thickness of 1.5 mounds is deposited on the entire surface by CVD, and then the implantation amount I
Boron (B) ion implantation was performed under the conditions of 10"cm-" and acceleration energy of 30keV (FIG. 3(E)).

From the state shown in FIG. 3(E), a photoresist film pattern is formed and left only in the area where the recess extends over 11M, and a resist film (not shown) with a thickness of 1/ffi is applied to fill the recess. The surface was then flattened.

From this state, these resist films were uniformly dry-etched to expose the surface of the polycrystalline Si film 70 in the convex portions. Thereafter, microwave dry etching was performed from the exposed surface of the polycrystalline Si film 70 to selectively remove the polycrystalline Si film 70 on the S, i02 film 22. Next, the exposed 5i0
2 film 22 was removed with a hydrofluoric acid aqueous solution (FIG. 3(F)).

After the resist film 24 is removed from the state shown in FIG. Formed.

Thereafter, the polycrystalline Si film 70 was patterned according to a desired circuit configuration to form the base lead-out electrode 7.

Next, high-pressure wet oxidation was performed under conditions of 7 atmospheres and 900°C, and 0.25, 1
A 5in2 film 14 having a thickness of 7I11 was formed. Next, Si
After removing the 3N4 film 21 with a hot phosphoric acid solution at 180° C., a Si and N4 film (not shown) is again deposited on the entire surface by the CVD method, and the Si and N4 films on the region where the collector is to be formed are selectively removed. N+ type scattered layer 1 by thermally diffusing phosphorus (P)
5 was formed. From this state, wet oxidation is performed again to form a SiO2 film 140 on the N+ type diffusion store 15, and then P
The 5iJN4 film used as a selection mask for diffusion was removed. Next, cover the area other than the area where the base will be formed with a resist film,
10e boron ion implantation using the resist film as a mask
Implanting with acceleration energy of V 1lX1014Cl11-
After removing the resist film, activation heat treatment was performed at 900° C. to form the intrinsic base region 11 (FIG. 3(G)).

From the state (7) in FIG. 3(G), the SiO2 film 20 is selectively removed to expose the main surface of the Si substrate 1, and then a polycrystalline (or amorphous) Si film is deposited again.

The emitter diffusion layer 12 was formed by arsenic (As) ion implantation and activation heat treatment. As ion implantation is 80k
eV, heat treatment at 95% under the conditions of 2 x 10” an-2
It was carried out at 0°C. Next, the above-mentioned polycrystalline Si film was patterned to form a pointed emitter lead-out electrode 13. Subsequently, 0, 4. Thick SiO2 film and 0,12- Si○2 film 1 by coating method
It was deposited on a 4-layer film 41 to stabilize and flatten the surface.

Thereafter, electrodes and wiring including a base electrode 17, an emitter electrode 18, and a collector electrode 19 were formed based on a desired circuit configuration by depositing an AEI film with a thickness of 0.9 M by vacuum evaporation and patterning it. (Figure 3 (H)).

The semiconductor device of this example is manufactured through the above-mentioned manufacturing process, and when the cross section of the vertical NPN transistor according to this example was observed using a transmission electron microscope, it was found that the edge of the buried insulating film 6 was a single crystal. A P+ type graft base region 10 extending 0.4 degrees laterally from the side surface of the Si substrate 1 and having a junction depth of 0.3#II+ is connected to an N1 type buried diffusion layer 2.
It was confirmed that they were completely separated from each other. In this example, an example was described in which the main surface of the semiconductor was etched by 0.3-degrees in the parallel direction by anisotropic etching.
The amount of etching may be increased or decreased as desired, and therefore the degree of lateral embedding of the buried insulating film 6 into the single crystal region can be set to a desired value independently of the thickness of the buried insulating film 6. The buried insulating film 6 is made of Si formed by thermal oxidation.
Although an example of an O2 film has been described, the insulating film 6 may be based on other formation methods such as a deposition method, or may be a different type of insulating film such as Si or N4 film, or a superimposed insulating film.

As a result of the above-mentioned structural improvements, this embodiment has a base-collector breakdown voltage of 13V and 8V compared to the conventional (5V).
v was also able to improve. Based on the above improvement in breakdown voltage, the thickness of the epitaxial layer 3 was reduced from 0.8 to 0.5, which is 172 times the thickness of the conventional structure, and a vertical NPN transistor was fabricated based on this example.・The withstand voltage between the collectors is 7V, and the current value is 2V compared to the conventional structure.
．． We were able to increase it by 5 times. In addition, ECL (emitter collector logic) manufactured based on this example
C) When the delay time caused by the ring oscillator was measured, a characteristic that was much faster (30 ps) than the conventional one (60 ps) was obtained. The above characteristics are based on this embodiment compared to the conventional structure. It has become possible. As a result of the above, the thickness of the N-type epitaxial layer 3 can be reduced, and higher speed operation becomes possible.

Embodiment 2 FIGS. 4(A) to 4(E) and FIG. 1 are cross-sectional views showing the second embodiment of the semiconductor device of the present invention in order of manufacturing steps.
The figure is a plan view of FIG. 1. In this example, the emitter region and the collector region are not perpendicular to (111), but 11
It was configured so that it was parallel to the 0> axis. In the above Example 1, after forming the epitaxial layer 3, a groove with a depth of 3 and a width of 1.2 mm reaching the Si substrate 1 is formed by RIE method, and a method known as the U-type element isolation method is applied to the groove portion. 0.
A Si○2 film 4 of 2t1m was formed and the trench was filled with a polycrystalline Si (or amorphous Si) film 5. The groove was configured to surround the active region. Subsequently, in accordance with Example 1, Si◯2 films 2o, 21 and Si, N, film 21 were formed (FIG. 4(A)).

From the state shown in FIG. 4A, the overlapping insulating films 20 to 2'2 and the epitaxial layer 3 are patterned according to the first embodiment. In the above patterning, vertical NP
(ljl) of N transistor and lateral PNP transistor
The active region is not perpendicular to [111] in the 211> axial direction (perpendicular to the paper plane of the drawing), and one end of the collector region of the vertical N P N transistor is perpendicular to [111] (110> axial direction) is a U-shaped inter-element isolation region. 5in2 membrane as set in 4
, or patterned so as to partially overlap the top of the polycrystalline Si film. Subsequently, a superimposed film 23 of SiO2 and Si3N is left on the side surface of the patterned epitaxial layer 3 in accordance with Example 1 (FIG. 4(B)).

From the state shown in FIG. 4(B), according to the above-mentioned Example 1, (111
) is perpendicular to the (110> axis direction, a horizontal hole having a ceiling surface and a floor surface parallel to the main surface and a vertical back wall is formed in the Si substrate 1. >The axial direction is defined by the element isolation insulating film 4, and etching proceeds only two-dimensionally (FIG. 4(C)).

From the state shown in FIG. 4(C), according to the first embodiment, the buried insulating film 6 is formed, the polycrystalline Si film 70 is deposited, and the polycrystalline Si film 70 is patterned to selectively remove the polycrystalline Si film 70 on the convex portions. The resist film 240 is installed and the resist film 24 is applied over the entire surface (FIG. 4(D)).

From the state shown in FIG. 4(D), from the flattening etching of the resist film 240.24, manufacturing proceeds according to the above-mentioned Example 1. In the process of forming the horizontal 1) NP transistor, the P+ type emitter diffusion layer 8 and the P+ type collector diffusion layer F! J9 was also formed in the same manner. Thereafter, the base lead-out electrode 7 and the emitter lead-out electrode 71 of the lateral PNP transistor were oxidized in accordance with Example 1 to form 14 Sio2 films (
Figure 4(E)).

From the state shown in FIG. 4(, E), manufacturing proceeds according to the first embodiment, but in the step of forming the N++ emitter diffusion layer 12 by diffusion of As added to the emitter extraction electrode 13, the horizontal type In the region where the PNP transistor is to be formed, the polycrystalline Si film used for the emitter extraction electrode 13 is removed so that it is not formed on the surface of the N+ type resistive diffusion layer epitaxial layer 3. Thereafter, electrodes including emitter electrodes and wiring were formed in accordance with Example 1 above.

FIG. 1 is a cross-sectional view of a semiconductor device manufactured according to this example, including a horizontal PNP transistor 100 and a vertical NP transistor 100.
N transistor 101 was formed at the same time (vertical NPN
The base extraction electrode 7 of the transistor 101 is a horizontal PNP.
A configuration connected to the collector 9 of the transistor 100 is shown).

FIG. 5 is a plan view showing the semiconductor device based on this embodiment, in which 161 is a collector lead-out electrode 71 of the horizontal PNP transistor 100, 171 is a base lead-out electrode 7 of the vertical NPN transistor 101, and 181 is a top view of a semiconductor device based on this embodiment. Similarly, 191 is a connection hole with the emitter extraction electrode 13, and 191 is a connection hole with the collector diffusion layer 15. In FIG. 5, in the semiconductor device based on this embodiment, a horizontal PNP
Emitter 8 and collector 9 of transistor 100 are emitter 12 and collector 1 of vertical NPN transistor 101.
5 is not perpendicular to [111] but is arranged in the 110> axial direction,
The active region is defined by the element isolation insulating film 4 in a direction not perpendicular to (1, 11) but perpendicular to the 110> axis. With the above configuration, in the semiconductor device based on this embodiment, the buried insulating film 6 is formed parallel to the surface of the semiconductor substrate 1 and parallel to the (110) plane, and is located between the P+ type graft base region 10 and the N++ buried layer 2. It was possible to separate them at uniform intervals regardless of the In addition, since the 211> axial direction is not perpendicular to [1,113] and is defined by the inter-element isolation insulating film 4, the (111) plane, which is not parallel to the main surface, is not exposed in the horizontal hole forming anisotropic etch, and the acute-angled plane is Not formed. Formation of a thick oxide film on an acute corner is likely to cause crystal defects etc. due to the difference in coefficient of thermal expansion between the oxide film and the semiconductor substrate. In the semiconductor device based on this example, the semiconductor substrate 1 after forming the buried insulating film
The crystal Wt was observed using an electron microscope, but no crystal defects were detected. In addition, defects due to crystal defects were evaluated by withstand voltage measurement using a configuration in which the vertical NPN transistors 101 according to this embodiment were connected in parallel.
The yield rate was extremely good at 99.99.9%. The base-collector breakdown voltage of the vertical N, PN transistor 101 based on this example is 13V, which is equivalent to the highest value obtained with the vertical NPN transistor based on Example 1, and has an excellent yield rate. Ta.

Embodiment 3 FIGS. 8(A) to 8(C) and FIG. 6 are sectional views showing a third embodiment of the present invention in the order of manufacturing steps and a completed sectional view.

As shown in Figure 8 (A), P conductivity type, resistivity 10Ω・
(2) A groove-buried type element isolation insulating film 2 is formed on the main surface of the Si substrate 1 whose main surface is (111) using a known element isolation technology.
00 is formed at a desired location to partition and separate the active region. A thin SiO2 film with a thickness of 15 nm is formed on the surface of the active region by thermal oxidation, and gate insulation 11! It was named i30. Next, deposit polycrystalline Si (or amorphous 5i) 1140 and P
Low resistance is achieved by thermal diffusion of phosphorus using oC et al., followed by Si
A superimposed insulating film 50 of a 3N4 film and a SiO□ film was deposited by chemical vapor phase reaction. After this, the overlapping insulating film 5o,
- Polycrystalline Si film 40 and gate insulating film 30 were sequentially patterned using a resist film (not shown) to form gate protection insulating film 50 and gate electrode 40. Further, the silicon substrate 1 was etched only in the vertical direction by a dry etching method to a depth of 0.3 mm, with the resist film used for patterning left in place. Thereafter, after removing the resist film, the exposed surface of the silicon substrate 1 is oxidized to form a 12 nm Sio2 film (not shown), and then a 120 nm Si, N4 film 60 is formed.
was deposited on the entire surface. From this state, the Si, N, film 60 was etched in a direction perpendicular to the substrate surface by sputter ion etching, leaving the Si3N4 film 60 only on the side walls of the gate electrode 40, etc. (FIG. 8(A)).

From the state shown in FIG. 8(A), the silicon substrate 1 is further etched by 0.3 -
Etched vertically. From this state, the exposed silicon substrate surface is etched using an etching solution containing 80% hydrazine hydrate, isopropatol, and 1% Triton x (trade name: surfactant) in a ratio of 2.00:20:1. did. The temperature of the etching solution was maintained at 10°C. In the above etching method, etching hardly progresses on <111>, and no etching occurs in the direction parallel to the main surface of the (111) semiconductor substrate. Furthermore, the 5in2 film and the Si3N4 film are not etched at all, and the element isolation insulating film 200, gate protection insulating film 50,
and Si.

The gate electrode 40 covered with the N4 film 60 is also not invaded.

(111) When the gate length direction of the gate electrode 40 on the main surface is not perpendicular to [111] and is set to 211>,
The amount by which the semiconductor substrate 1 below the gate electrode 40 is etched by the above process.

That is, the depth of the horizontal hole does not depend on the etching time, and is 1/3 of the height of the horizontal hole, that is, 0.1. Met.

The above is thought to be because when the main surface of the semiconductor is (111), either the (Tll), (11th), or (1st 1st) surface appears on the back surface of the horizontal hole, and etching no longer progresses. It will be done. Note that the above step may be performed using any other etching solution, such as an aqueous potassium hydroxide (KOH) solution, which has an etching rate that varies greatly depending on the surface orientation of the semiconductor substrate. Furthermore, the etching described above may be based on a dry etching method using gas instead of using a solution (FIG. 8(B)).

From the state of FIG. 8(B), the exposed semiconductor substrate 1
About 0.1 part of the entire surface was etched. For etching, a solution of hydrofluoric acid/nitric acid with a mixing ratio of 1/200 was used. After that, the Si3N4 film 60 and the gate protection insulating film 5 are formed.
Thermal oxidation was performed using 0 as an oxidation inhibiting film, and a SiO2 film of o, 3IIrn was formed on the exposed surface of the semiconductor substrate, thereby forming a buried insulating film 70. Next, the remaining exposed Si and N4 films 60 are selectively removed using a phosphoric acid solution heated to 160°C, and then selected on the sidewalls of the gate electrode 40 to which phosphorus is added at a high concentration using a wet oxidation method at 800°C. A SiO□ film having a thickness of 0.2 parts M was formed. The thin 50 nm thick 5iO7 film formed on the low impurity concentration substrate surface by the above thermal oxidation process is removed, and the 5iO7 film formed on the side wall of the gate electrode 40 is coated with 0.0 nm.
A 15-thick gate sidewall insulating film 80 was selectively formed.

From this state, a polycrystalline Si film 9o with a thickness of 0.91 parts was deposited by chemical vapor phase reaction, and then phosphorus (P) ions were implanted at an acceleration energy of 80 keV and an implantation amount of 5 x 101
After that, heat treatment was performed at 950° C. for 10 minutes in an N2 atmosphere to activate the implanted ions and form the source diffusion layer 110 and drain diffusion layer 1.
11 was formed in the Si substrate 1 (FIG. 8(C)).

From the state shown in FIG. 8(C), the polycrystalline Si film 90 was planarized and etched to form a source lead-out electrode 91 and a drain lead-out electrode 92, which were separated from each other. Next, a SiO2 film to which a slight amount of phosphorous was added was deposited to a thickness of 0.5IRn to form a surface stabilizing film 120. Finally, a desired portion of the surface stabilizing film 120 is subjected to dilution, and an electrode wiring film containing chlorine as a main component is deposited and patterned based on the desired circuit configuration, and the source electrode 130. Then, electrodes and wiring including the drain electrode 140 were formed (FIG. 6).

A semiconductor device was manufactured through the above manufacturing process, but the source
In a transistor in which the gate electrode direction is set in advance so that the drain direction is [OT1] or [01 work], the horizontal hole surface of the Si substrate directly below the gate electrode 40 is located at the ceiling and bottom in the state shown in FIG. 8(B). is (111),
The back surface of the horizontal hole was a (110) surface that was perpendicular to (111). In the gate width direction, that is, in the direction perpendicular to the plane of the paper in FIG. 8(B), the element isolation insulating film (not shown)
was defined at the end of the The ceiling surface of the horizontal hole is (111) and is strictly parallel to the main surface of the substrate. Therefore, the single crystal layer on the buried insulating film 7o, which is formed by thermally oxidizing the ceiling surface, has a uniform thickness and is extremely thin. In the semiconductor device based on this example, it was confirmed by a cross-sectional test that the single crystal layer had a uniform thickness of 75 nm. Gate length 0.5tlr++, effective channel length 0.37a manufactured based on this example
When the source-drain breakdown voltage of the positive MOS transistor was measured, a high value of about 9.5V was obtained. For comparison, a transistor with a normal structure having the same gate size and manufactured at the same time had a resistance of about 4.5 square meters, which was limited by the punch-through breakdown voltage.

From the above comparison of breakdown voltages, it was found that the MoS transistor based on this example had a punch-through breakdown voltage approximately twice as high as that of the conventional normal structure. Over here.

Based on this example, MOS transistors with various gate lengths were manufactured, and the dependence of the threshold voltage value on the gate length at a drain voltage of 5V was measured. , the gate length that decreased by 0.5V was 0.2-. On the other hand, in the case of the normal structure transistor No. 1, the gate length was 0.8 mm, confirming that the short channel effect was significantly improved by the structure of this example. That is, based on this embodiment, it is possible to operate with high reliability even at a normal power supply voltage of 5V, and therefore, it is possible to realize an ultra-fine transistor that can operate at high speed and has an extremely small short channel effect.

In the manufacturing process described above, by forming the buried insulating film 70 thickly or by moving the position of the horizontal hole formed in the substrate 1 closer to the main surface of the substrate, the single crystal layer left on the buried insulating film can be reduced. can be made even thinner. MOS based on this example with a single crystal layer thickness of 30 nm
When we evaluated the short channel effect characteristics of the transistor, we found that
Effective gate length is 0.1t! Even in the case of the transistor of 1.0 m, no decrease of 0.3 VL from the threshold voltage value of the long channel transistor was observed, and it became clear that the thinner the single crystal layer thickness, the better the short channel effect. Based on this example, ultrafine transistors with various single crystal layer thicknesses were manufactured and the short channel effect characteristics were evaluated. It was found that if the single crystal layer on the buried insulating film is 0.2 trm or less, the short channel effect There was a tendency for the ratio to be improved, especially when the ratio was 0.1- or less.

In the above embodiment ', a single transistor was described for convenience of explanation, but this embodiment can be applied to a semiconductor integrated circuit device having a plurality of transistors on the same (111) plane substrate. In this case, a configuration in which a plurality of transistors based on this embodiment and a plurality of transistors having a conventionally known structure are mixed on the same substrate may be used. In the above configuration, it is desirable that the gate length direction of the plurality of transistors based on this embodiment be set in the <110> direction.

Furthermore, in this embodiment, a case has been described in which the buried insulating film 70 is configured under the source diffusion layer 110 and the drain diffusion layer 110, but if desired, it can be configured only in one of the layers, and the other can be configured as a diffusion layer with a normal structure. There is no problem even if it has a transistor structure. Further, although this embodiment relates to an n-channel transistor, it goes without saying that it can be similarly applied to a p-channel transistor and a CMO8 configuration including an n-channel transistor and a p-channel transistor.

Example 4 In the third example above, the Si substrate 1 is <111
A semiconductor device was manufactured according to the first example described above using a substrate whose main surface was a plane perpendicular to the <332> axis, which was inclined by about 10° from the <110> direction from the <332> axis. In this example, the source-train direction is
The width direction of the gate was set as 3〉. As a result of cross-sectional observation, the ceiling and bottom surfaces of the horizontal hole formed in the silicon substrate using the hydrazine mixture were parallel to the main surface and were (332) planes. The back surface of the horizontal hole was (engineering 10) and perpendicular to the ceiling and bottom. The side surface of the side hole was defined by an inter-element isolation insulating film 200. The buried insulating film 70 was formed by oxidizing the wall surface of the side hole, and a plurality of n-channel type M
○S transistor was manufactured. The effective channel length of the transistor is 0.5-, and the thickness of the buried insulating film is 0.1tIt.
n, and the distance d between the buried insulating films was varied by controlling the amount of side hole etching. When we measured the source-drain breakdown voltage of each transistor, it was 0.4.0.3.
7.5 for each transistor with each spacing of 0.2 am
v, 9v, and 11v, but no effect of improving breakdown voltage was observed in transistors with d values of 0.5- or more.

In this example, a substrate whose main surface is a plane perpendicular to the <111> axis and tilted by approximately 16 degrees in the 110> direction (221> axis) is used, and the source/drain direction is <T 10> or 1TO>. In the semiconductor device manufactured by setting the direction in the direction of
In a semiconductor device in which the main surface is a plane perpendicular to the <331> axis tilted by <331>, the (111) plane inclined by 22 degrees with respect to the main surface appears on the ceiling and bottom surfaces of the formed horizontal hole, and the buried insulation A single crystal layer of uniform thickness was not obtained on the film 70.

In addition, in the semiconductor device based on this example, which is manufactured with the main surface being a plane perpendicular to the <223> axis that is tilted approximately 11 degrees from the <111> axis in the <001> direction, the ceiling and bottom surfaces parallel to the main surface are A horizontal hole was formed. However, about 30 @ in the <001> direction from the <111> axis
In the semiconductor device based on this example manufactured with the main surface being a plane perpendicular to the inclined <113> axis, it was not possible to form a horizontal hole in which the ceiling surface and the bottom surface were parallel to the main surface.

The above result shows that for each surface with an inclination of about 206 or more from (111), the ceiling and bottom of the horizontal hole formed are parallel to the main surface and are configured at a preset depth,
Therefore, although it is possible to leave an ultra-thin single crystal layer on the buried insulating film 70 with good reproducibility and controllability, it is not possible to control the leaving of the ultra-thin single crystal layer on a crystal plane with an inclination of about 20° or more. In a semiconductor device manufactured based on this embodiment with the former crystal plane as the main surface, a transistor in which the gap between the buried insulating films 70 is narrower than the effective channel length is different from the transistor based on the first embodiment. Similar effects were observed, namely, an improvement in breakdown voltage between the source and train and an improvement in the short channel effect.

〔Effect of the invention〕

As described above, according to the present invention, the buried insulating film can be introduced in self-alignment with the sidewall of the semiconductor substrate, that is, with a constant dimension and parallel to the main surface of the semiconductor. The present invention utilizes crystal orientation as a principle, and since the setting of the buried insulating film region can be controlled extremely accurately, miniaturization of ultrafine transistors is not impaired in any way.

In application to bipolar transistors.

Since the buried insulating film can be controlled as desired, the base-collector breakdown voltage can be more than doubled compared to the conventional method without impairing the crystallinity of the semiconductor substrate on the buried insulating film. Therefore, when designing the base-collector breakdown voltage to be higher than the desired value, the epitaxial layer can be made thinner, and the graft base region does not penetrate into the intrinsic base, so the active region is smaller than the conventional structure. Can be expanded significantly.

As a result, the current density can be significantly increased, making it possible to realize a transistor with an ultra-fine structure and ultra-high speed. In application to MOS transistors, the insulating film can be formed at a desired location inside the single crystal semiconductor substrate under the gate electrode due to the self-alignment relationship with the gate electrode, and since the crystal orientation is utilized, the insulating film can be formed on the main surface of the substrate used. Once the crystal orientation is determined, the setting of the insulating film forming region can be controlled extremely accurately. Furthermore, the single crystal region on the insulating film is originally a good single crystal,
No deterioration occurs even after using the method of the present invention. Furthermore, since it is possible to realize a structure in which the entire junction side region except for the channel region of the source/drain junction is replaced with an insulating film, the punch-through current path can be almost completely blocked.

Therefore, the so-called short channel effect, in which the threshold voltage value changes with miniaturization of the gate length, can be significantly improved. In particular, even in a transistor with an effective channel length of 0.11 m or more, characteristics with small short channel effects can be achieved.

Furthermore, according to the present invention, all of the bottom surface and most of the side surfaces of the source/drain junction can be replaced with an insulating film having a low dielectric constant and a large thickness, thereby significantly reducing the input/output capacitance. . As a result, it also has the effect of increasing the operating speed.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a bipolar transistor according to an embodiment of the present invention, FIG. 2 is a sectional view of a conventional bipolar transistor, and FIGS. FIGS. 4(A) to 4(E) are process sectional views showing another embodiment of the method for manufacturing a bipolar transistor of the present invention,
FIG. 5 is a plan view of the bipolar transistor shown in FIG. 1. FIG. 6 is a cross-sectional view of an embodiment of a MoS transistor of the present invention, FIG. 7 is a cross-sectional view of a conventional example of a MOS transistor, and FIGS. 8 (A) to (C) are a cross-sectional view of a MOS transistor of the present invention. FIG. 2 is a cross-sectional view showing an example of a manufacturing method. 1... P-type Si single crystal substrate 2... N+ type buried layer 3... Epitaxial layer 4... Inter-element isolation insulating film 5... Polycrystalline (or amorphous) Si film 6...・
Buried insulating film 7...Collector extraction electrode (also serves as base extraction electrode) 8...P+ type emitter diffusion layer 9...P+ type collector diffusion layer 10...P+ type graft base 11...P type intrinsic base Diffusion layer 12...N+ type emitter diffusion layer 13...Emitter extraction electrode 14-8 inch, film 15...Collector electrode 16...Emitter electrode 17...Collector electrode 18...Emitter electrode 19...・Collector electrode 2O-Sin2 film 21...Si, N4 film 22...SiO2 film 23...Overlapping insulating film 24...Resist film 30...Gate insulating film 40...Gate electrode 50... ...Gate protection insulating film 60...Si, N, film 61...Buried insulating film 70...Polycrystalline (or amorphous) Si film 71...Emitter extraction electrode 80...Gate side wall insulation Film 91...Source extraction electrode 91...Source extraction electrode 92...Drain extraction electrode 100...Horizontal PNP transistor 101...Vertical NPN transistor 110...Source diffusion layer 111...Drain diffusion Layer 120...Surface stabilization film 130...Source electrode 140...Drain electrode 140...Drain electrode 141...5i02 film 161, 171, 181...Connection hole 200...Separation between elements Insulating film 240...Resist film 710...Embedded insulating film

Claims (1)

[Scope of Claims] 1. A convex semiconductor region formed on a surface region of a semiconductor substrate, a buried insulating film formed on the surface of the semiconductor substrate on at least both sides of the bottom of the convex semiconductor region, and the convex semiconductor region. an extraction electrode layer that is in contact with a sidewall of the shaped semiconductor region and formed on the buried insulating film; and an impurity doped region formed on the sidewall of the convex semiconductor region that is in contact with the extraction electrode layer; A semiconductor device characterized in that the surface of the semiconductor substrate at the bottom of the buried insulating film is a (111) plane. 2. The semiconductor device according to claim 1, wherein a part of the boundary of the impurity doped region is defined by a pair of sides of the impurity doped region coming into contact with an element isolation region. 3. Performing a first vertical etch on the semiconductor substrate to form a trench to form a convex semiconductor region. selectively forming an oxidation-resistant film on the sidewalls of the convex semiconductor region; performing second vertical etching on the semiconductor substrate to deepen the groove; and performing anisotropic etching. 110> A step of proceeding with etching in the axial direction to form a groove that bites into the bottom of the side wall of the convex semiconductor region and whose bottom semiconductor substrate surface has a (111) plane, and at least both sides of the convex semiconductor region. forming a buried insulating film on the surface of the groove. 4. The method of manufacturing a semiconductor device according to claim 5, wherein a (111) plane is used as the main surface of the semiconductor substrate. 5. The method of manufacturing a semiconductor device according to claim 5, wherein a plane having an inclination of about 20 degrees or less with respect to the (111) plane is used as the main surface of the semiconductor substrate.