JPH01144631A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH01144631A JPH01144631A JP62303554A JP30355487A JPH01144631A JP H01144631 A JPH01144631 A JP H01144631A JP 62303554 A JP62303554 A JP 62303554A JP 30355487 A JP30355487 A JP 30355487A JP H01144631 A JPH01144631 A JP H01144631A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- chip
- integrated circuit
- semiconductor integrated
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000007547 defect Effects 0.000 abstract description 3
- 238000001465 metallisation Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路チップに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor integrated circuit chips.
従来の半導体集積回路チップは（以下チップという。）
、オートダイシングする時、スクライブ線上に絶縁膜が
入っていると、スクライブ線が検出できずダイシングが
できないため、スクライブ線上には絶縁膜等が入らない
構造となっている。Conventional semiconductor integrated circuit chips (hereinafter referred to as chips)
When performing automatic dicing, if an insulating film is placed on the scribe line, the scribe line cannot be detected and dicing cannot be performed, so the structure is such that no insulating film or the like is placed on the scribe line.
上述したように従来の半導体集積回路チップ（以下チッ
プという）のスクライブ線上に絶縁膜がないことから第
２図に示すように組立て時にポンディングワイヤーがチ
ップの露出したスクライブ線部７の箇所で接触し、不良
品となってしまう恐れがある。As mentioned above, since there is no insulating film on the scribe lines of conventional semiconductor integrated circuit chips (hereinafter referred to as chips), the bonding wire comes into contact with the exposed scribe line portion 7 of the chip during assembly, as shown in Figure 2. However, there is a risk that the product will be defective.
また、そのことにより、ボンディングワイヤー長及びＩ
Ｃチップ内のポンディングパッドの配置に制約が出来て
いる。In addition, the bonding wire length and I
There are restrictions on the placement of bonding pads within the C chip.
本発明は、以上の問題点を解消するＩＣチップを提供す
るものである。The present invention provides an IC chip that solves the above problems.
本発明の半導体集積回路チップは、スクライブ線（ウェ
ハーからチップを切断するために必要な領域）上が絶縁
膜で覆われた構造を有している。The semiconductor integrated circuit chip of the present invention has a structure in which a scribe line (an area necessary for cutting a chip from a wafer) is covered with an insulating film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例である半導体集積回路チッ
プ（以下チップという）の断面図である。FIG. 1 is a sectional view of a semiconductor integrated circuit chip (hereinafter referred to as chip) which is an embodiment of the present invention.
拡散工程において、メタライゼーション後絶縁膜でチッ
プを覆い、スクライブ線上の絶縁膜のみ除去する。その
状態でダイシングを行ない（例えばハーフカット方式；
ソーによる切断をウェハー厚さの途中までとし、その後
ウェハー曲げストレスをかげてブレーキングする方法）
、もう−度チツブ全体を絶縁膜で覆う。その後ポンディ
ングパッド部の絶縁膜を除去し、ブレーキングすればス
クライブ線上も絶縁膜で覆われる形となり、第１図−６
のようにボンディングワイヤーとチップが接触すること
がなくなる。In the diffusion process, the chip is covered with an insulating film after metallization, and only the insulating film on the scribe lines is removed. Perform dicing in this state (for example, half-cut method;
A method of cutting with a saw to the middle of the wafer thickness and then braking to reduce the wafer bending stress)
Then, cover the entire chip again with an insulating film. After that, if the insulating film on the bonding pad is removed and the brake is applied, the scribe line will also be covered with the insulating film, as shown in Figure 1-6.
This prevents the bonding wire from coming into contact with the chip.
以上説明したように本発明による半導体集積回路チップ
は（以下チップという）ボンディンダパッド以外が絶縁
膜で覆われているため、ボンディングワイヤーとチップ
の接触による不良の心配がなく、ボンディングワイヤー
長及びポンディングパッド配置の自由度が増すことによ
り１種類のリードフレームで多種類のチップを搭載する
ことができ、１種類のリードフレームの大量発注により
、リードフレームのコストダウンが可能になるとともに
、リードフレームの種類が少なくて済むことから在庫管
理が容易となる。As explained above, since the semiconductor integrated circuit chip according to the present invention (hereinafter referred to as the chip) is covered with an insulating film except for the bonder pad, there is no fear of defects due to contact between the bonding wire and the chip, and there is no need to worry about defects due to contact between the bonding wire and the chip. By increasing the degree of freedom in placing pads, it is possible to mount many types of chips on one type of lead frame, and by ordering large quantities of one type of lead frame, it is possible to reduce the cost of lead frames. Inventory management becomes easier because there are fewer types of products.
第１図は、本発明の一実施例である半導体集積回路チッ
プの断面図、第２図は、従来の半導体集積回路チップの
断面図である。
１・・・・・・ボンディングワイヤー、２・・・・・・
絶縁膜、３・・・・・・リードフレーム、４・・・・・
・半導体集積回路チップ、５・・・・・・ポンディング
パッド、６・・・・・・スクライブ線、７・・・・・・
ボンディングワイヤーとＩＣチップのショート部。
代理人 弁理士 内 原 晋FIG. 1 is a sectional view of a semiconductor integrated circuit chip according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor integrated circuit chip. 1... Bonding wire, 2...
Insulating film, 3...Lead frame, 4...
・Semiconductor integrated circuit chip, 5...Ponding pad, 6...Scribe line, 7...
Short part between bonding wire and IC chip. Agent Patent Attorney Susumu Uchihara
Claims (1)
体集積回路。A semiconductor integrated circuit that has a structure in which the scribe lines are covered with an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62303554A JPH01144631A (en) | 1987-11-30 | 1987-11-30 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62303554A JPH01144631A (en) | 1987-11-30 | 1987-11-30 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01144631A true JPH01144631A (en) | 1989-06-06 |
Family
ID=17922409
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62303554A Pending JPH01144631A (en) | 1987-11-30 | 1987-11-30 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01144631A (en) |
-
1987
- 1987-11-30 JP JP62303554A patent/JPH01144631A/en active Pending
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