JPH0115224Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to a bias circuit for supplying bias current to a differential amplifier, and particularly relates to a bias circuit for supplying a bias current to a differential amplifier. The present invention relates to a bias circuit capable of stably biasing a differential amplifier without causing any interference, and capable of low voltage operation. (b) Prior Art A circuit as shown in FIG. 1 has been proposed as a bias circuit for supplying a bias current to a differential amplifier configured as an IC (integrated circuit). In FIG. 1, a differential amplifier 1 includes first and second amplifying transistors 2 and 3 whose emitters are commonly connected, and whose collectors are connected to the common emitters of the first and second amplifying transistors 2 and 3. 4, and load resistors 5 and 6 connected to the collectors of the first and second amplification transistors 2 and 3, respectively.
and the differential input signals applied to the first and second input terminals 7 and 8 connected to the bases of the second amplification transistors 2 and 3, and the differential input signals are connected to the collector of the second amplification transistor 3. An amplified output signal is obtained at the output terminal 9. The bias circuit 10 also includes a first transistor whose base and emitter are commonly connected to the constant current transistor 4.
A constant current source 13 including a transistor 11 and a second transistor 12 whose collector is connected to the collector of the first transistor 11 amplifies the difference current between the collector currents of the first and second transistors 11 and 12, and a third transistor that supplies the base current of the current transistor 4 and the first transistor 11;
and a fourth transistor 14 and 15, a diode-connected fifth transistor 16, and a sixth transistor 17 whose base and emitter are commonly connected to the fifth transistor 16.
a first current inversion circuit 18 that inverts the collector current of the transistor 15 and supplies it to the base of the first amplification transistor 2; and the fifth transistor 1.
6 and a seventh transistor 19 whose base and emitter are commonly connected to the fifth transistor 16, and a second current which inverts the collector current of the fourth transistor 15 and supplies it to the base of the second amplifying transistor 3. and an inverting circuit 20, the first and second amplification transistors 2
A base current of 1/2 I _B is supplied to the bases of transistors 3 and 3, and a base current of I _B is supplied to the base of the constant current transistor 4. In FIG. 1, the collector current of the second transistor 12, which is the output current of the constant current source 13, is expressed as [βI _B
+2/βI _B ] (where β is the current amplification factor of the NPN transistor), the base currents of the third and fourth transistors 14 and 15 are respectively 1/βI _B , and the third and fourth transistors 14 and 15 have base currents of 1/βI B , respectively. When the emitter currents of the transistors 15 and 15 become I _B and the collector current of the first transistor 11 becomes _βIB , the circuit becomes stable. Therefore, the base current of the constant current transistor 4 also becomes I _B , and the collector current of the constant current transistor 4 becomes βI _B. On the other hand, since the base current of the fourth transistor 15 is 1/βI _B , its collector current is I _B , and the collector current I _B is
and is inverted by second current inverting circuits 18 and 20,
first and second amplification transistors 2 and 3, respectively;
supplied to the base of In that case, the emitter area ratio of the fifth transistor 16 and the sixth transistor 17 and the emitter area ratio of the fifth transistor 16 and the seventh transistor 19 are set equal to 2:1.
Then, the collector currents of the sixth and seventh transistors 17 and 19 are equal to 1/2I _B , and the collector currents of the first and second amplification transistors 2 and 3 are also equal to 1/ _2βIB . Therefore, the differential amplifier 1 will be correctly biased by the bias circuit 10. When the circuit in Figure 1 is integrated into an IC, the current of NPN transistors (first and second amplification transistors 2 and 3, constant current transistor 4, first, third and fourth transistors 11, 14 and 15) The amplification factor can be set equally, and PNP type transistors (second, fifth, sixth and seventh transistors 12,
Since the current amplification factors of 16, 17, and 19) can be set equally, the circuit of FIG. 1 has the advantage that the differential amplifier can be stably biased regardless of changes in the current amplification factors. However, in the circuit configuration shown in FIG. 1, for example, the base-emitter paths of the first transistor 11 and the third transistor 14 are connected in series, so in order to operate the circuit stably, [2V _BE +V _CE (sat) ] (where, V _BE is the voltage between the base and emitter of the transistor, and V _CE (sat) is the saturation voltage between the collector and emitter of the transistor)
The drawback is that it cannot be used in ICs that use low power supply voltages. By the way, when using a 3V power supply voltage,
60% of that, or 1.8V, is the compensation voltage,
2V _BE +V _CE (sat) = 2 x 0.7 (V) + 0.2 (V) = 1.6 (
V)
As a result, there is a shortage of Dynamite Cleanse. (c) Purpose of the invention The present invention was created in view of the above points, and aims to provide a bias circuit for a differential amplifier that can ensure sufficient dynamic range even when used in an IC that uses a low power supply voltage. It is something to do. (d) Embodiment Figure 2 is a circuit diagram showing an embodiment of the present invention.
Reference numeral 21 denotes first and second amplifying transistors 22 and 23 whose emitters are commonly connected, and a constant current transistor 2 whose collector is connected to the common emitter of the first and second amplifying transistors 22 and 23.
25 is a first transistor whose base and emitter are commonly connected to the constant current transistor 24; 26 is a diode-connected transistor 27; and a transistor whose base and emitter are commonly connected to the transistor 27. 28 and the diode-connected transistor 2
and a resistor 29 that determines the collector current of 7.
A current source 30 that supplies the collector current of the first transistor 25 is composed of a diode-connected second transistor 31 and a third transistor 32 whose base and emitter are commonly connected to the second transistor 31; A first current inversion circuit 33 inverts the difference current between the collector current of the transistor 25 and the output current of the current source 26; 33 is a diode-connected fourth transistor 34; the base and emitter are commonly connected to the fourth transistor 34; a second current inverting circuit configured to supply a base current of the constant current transistor 24 and the first transistor 25;
36 consists of the fourth transistor 34 and a sixth transistor 37 whose base and emitter are commonly connected to the fourth transistor 34, and a third current inversion circuit which supplies the base current of the first amplification transistor 22 ; the fourth transistor 34
and a seventh transistor 39 whose base and emitter are commonly connected to the fourth transistor 34, and is a fourth current inversion circuit that supplies the base current of the second amplifying transistor 23. The differential amplifier 21 differentially amplifies input signals applied to input terminals 40 and 41 connected to the bases of the first and second amplification transistors 22 and 23, respectively, and the collector of the second amplification transistor 23. The amplified output signal is obtained at the output terminal 42 connected to the differential amplifier 2 .
1 must be supplied with an appropriate bias current in order to operate properly. Thus, by adjusting the value of the resistor 29, the current source 26
If the output current of is [βI _B +2I _B ] (where β is the current amplification factor of the NPN transistor) and the inversion ratio of the first and second current inversion circuits 30 and 33 is 1, then
Due to the effect of the negative feedback path from the collector of the first transistor 25 to the base of the first transistor 25 via the first and second current inverting circuits 30 and 33 , the collector current of the first transistor 25 is βI _B , the collector currents of the second and third transistors 31 and 32 are 2I _B , the collector currents of the fourth and fifth transistors 34 and 35 are also 2I _B ,
The circuit becomes stable. In that case, the base current of the first transistor 25 is I _B and the constant current transistor 24
The base current of the constant current transistor 24 also becomes _IB , and the collector current of the constant current transistor 24 becomes _βIB . On the other hand, if the inversion ratio of the third and fourth current inversion circuits 36 and 38 is 1/4, when the collector current of the fourth transistor 34 is _2IB , the collector current of the sixth and seventh transistors 37 and 39, In other words, the output currents of the third and fourth current inversion circuits 36 and 38 are 1/2I _B , respectively, and the output currents 1/2I _B are supplied to the bases of the first and second amplification transistors 22 and 23 as bias currents. be done. Therefore, the collector currents of the first and second amplifying transistors 22 and 23 are respectively 1/2βI _B , which is a value commensurate with the collector current βI _B of the constant current transistor 24, so that the differential amplifier 21 is Bias is achieved. Fourth transistor 34 and sixth transistor 37
and the fourth transistor 34
The inversion ratio between the transistor 39 and the seventh transistor 39 is set using, for example, a circuit as shown in FIG. In FIG. 3, the fourth to seventh transistors 43 to 46 correspond to the fourth to seventh transistors 34 to 39 in FIG.
The sixth and seventh transistors 45 and 46 shown in the figure each have a multi-collector structure having four collectors. Thus, the first collector of the sixth transistor 45 is connected to the terminal 47 connected to the base of the first amplifying transistor 22 in FIG.
The second to fourth collectors are commonly grounded. In addition, the seventh transistor 46
The first collector is connected to a terminal 48 connected to the base of the second amplification transistor 23 in FIG. 2, and the second to fourth collectors are commonly grounded. Therefore, if the collector current of the fourth transistor 43 is 2I _B , a collector current of 1/2 I _B flows through the first collectors of the sixth and seventh transistors 45 and 46, and this collector current flows through the first and second amplification transistors. 22 and 23 as base bias currents. Further, the base bias current can be supplied to the first and second amplifying transistors 22 and 23 using the circuit shown in FIG. 4. In FIG. 4, only an eighth transistor 49 having a multi-collector structure having four collectors is used in place of the sixth and seventh transistors 45 and 46 of FIG. In that case, the third current inversion circuit 3
6 is constructed using the fourth transistor 43 and the first collector of the eighth transistor 49, and the fourth
The current inversion circuit 38 is configured using the fourth transistor 43 and the second collector of the eighth transistor 49. Thus, the first collector of the eighth transistor 49 is connected to the terminal 50 connected to the base of the first amplifying transistor 22 in FIG.
, the second collector is connected to the second amplification transistor 23.
The third and fourth collectors are commonly grounded. Therefore, if the collector current of the fourth transistor 43 is 2I _B , then the first
A current of 1/2I _B is obtained in the and second collectors, respectively, and the current flows through the first and second amplification transistors 22.
and 23, stable biasing of the differential amplifier 21 is achieved. In FIG. 2, the input current is supplied using the current source 26, but if a constant voltage power source is used, a resistor may be used instead of the current source 26. Further, the inversion ratios of the first to fourth current inversion circuits 30 to 38 are not limited to those in the embodiment, and a current of 2I B is applied to the collector of the fifth transistor 35, and a current of 2I _B is applied to the collector of the fifth transistor 35, and
It can take any value that provides a current of 1/2I _B in the collectors of 7 and 39, respectively. (e) Effects of the invention As described above, according to the invention, it is possible to provide a bias circuit that can stably bias a differential amplifier. In particular, since the base-emitter paths of the transistors are not connected in cascade in the bias circuit, there is a great advantage in that it can be operated at a low voltage (V _BE +V _CE (sat)). In addition, since the bias circuit is configured as a negative feedback type, even if the collector current of the constant current transistor changes due to temperature fluctuations, it can be compensated for, so there is an advantage that a stable bias circuit can be obtained. Furthermore, as shown in FIGS. 3 and 4,
If the sixth and seventh transistors have a multi-collector structure, there is an advantage that the chip area when integrated into an IC can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a bias circuit of a conventional differential amplifier, FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIG. 3 is a circuit diagram showing another embodiment of a part thereof. and FIG. 4 is a circuit diagram showing still another embodiment of FIG. 3. Explanation of main figure numbers, 21 ...Differential amplifier, 24...
... constant current transistor, 25 ... first transistor, 30 , 33 , 36 , 38 ... current inversion circuit.

Claims (1)

[Scope of utility model registration request] Bias for supplying bias current to a differential amplifier comprising first and second amplification transistors whose emitters are commonly connected, and a constant current transistor whose emitters are connected to the common emitters of the first and second amplification transistors. The circuit includes a transistor whose base and emitter are commonly connected to the constant current transistor, a current source that supplies a collector current of the transistor, and a difference current between the collector current of the transistor and the output current of the current source. a first current inverting circuit that inverts the output current of the first current inverting circuit; a second current inverting circuit that inverts the output current of the first current inverting circuit to generate a base current of the constant current transistor; Flip and the first
The third transistor generates the base current of the amplification transistor.
consisting of a current inversion circuit and a fourth current inversion circuit that inverts the output current of the first current inversion circuit and generates a base current of the second amplification transistor,
The first to fourth current inverting circuits are configured by a diode-connected input transistor and an output transistor whose base and emitter are commonly connected to the base and emitter of the input transistor, and A bias for a differential amplifier, characterized in that the base currents of the first and second amplifying transistors are set to 1/2 of the base current of the constant current transistor by setting the inversion ratio of the inversion circuit to a predetermined value. circuit.