JPH01176117A - Through-current preventing circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for any delay circuit by detecting each threshold voltage of P and N-channel MOS transistors(TRs) and switching each gate signal of output N and P-channel MOS TRs in response to the detection output. CONSTITUTION:When a drive signal S1 changes from a low level to a high level, an output signal S11 and a gate voltage S13 are changed respectively, and an output signal S12 and a gate voltage S14 are unchanged till the gate voltage S13 exceeds the threshold voltage TH1 of P-channel MOS TRs 3, 18 into a high level. Moreover, when the drive signal S1 changes from a high level to a low level, the output signal S12 and the gate voltage S14 are changed respectively, an output signal S11 and a gate voltage S13 are unchanged till the gate voltage S14 exceeds the threshold voltage TH2 of P-channel MOS TRs 4, 15 into a low level. Thus, the through-current is prevented without using any delay circuit.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a transistor circuit having an output circuit having a complementary inverter configuration in which first and second conductivity type transistors for output are connected in a complementary manner, for example, P and N transistors. Channel M
O5) - In a CMO5-IC having an output circuit having a CMOS inverter configuration using transistors, the present invention relates to a through-current prevention circuit that prevents through-current flowing when output P and N-channel IAOS transistors of the output circuit switch.

[Prior Art] Normally, an output circuit having a CMOS inverter configuration has a large load driven by the output circuit.
Both N-channel MO5) transistors are designed to carry a large current. Therefore, this output P,
When an N-channel MOS transistor switches,
There is time for both the output P-channel MO5 transistor and the output N-channel MO5 transistor to be in the on state, and at this time, there is a connection between the positive power supply and the negative power supply of the IC via the output P and N-channel MO5 transistors. A large through current flows. This through current hinders the reduction in power consumption of the IC, and when the impedance of the power supply supplied to the IC is high, it causes a voltage drop in the power supply to the IC, causing malfunction.

Conventionally, as a circuit to prevent such through current,
For example, a circuit as shown in FIG. 3 is used. Here, 1 is an output circuit, and 2 is a delay circuit. The output circuit 1 has a CMOS inverter configuration consisting of complementary connection of output P and N channel MOS transistors 3 and 4,
Delay circuit 2 consists of inverters 5 and 6 and capacitor 7. 9 and lO are a Nand gate and a NOR gate that receive the drive signal 51 and the delay circuit output S2 from the delay circuit 2 and form gate signals S3 and S4 for driving the gates of the transistors 3 and 4, respectively.

In FIG. 3, the output P-channel MO of output circuit 1
The gate signals S3 and S4 are formed using the delay circuit 2 so that the gate signal S3 of the S transistor 3 and the gate signal S4 of the output N-channel transistor 4 do not overlap.

FIG. 4 is a time chart for explaining the operation of the conventional circuit shown in FIG.

The drive signal Sl is transformed by the delay circuit 2 into a delay circuit output S2 having a delay Td. The Nant gate 9 synthesizes the drive signal S1 and the delay circuit output S2 to form a gate signal S3 of the output P-channel MO5 transistor 3,
Similarly, the NOR gate 10 creates a gate signal S4 for the output N-channel MO5 transistor 4.

Therefore, according to the circuit shown in FIG. 3, the drive signal Sl is applied to the output P channel MO5 transistor 3 and the output N channel M
Both OS transistors 4 are transformed into a gate signal S3 and a gate signal S4 having an off time T0. As a result, no through current flows through the output circuit 1.

[Problems to be Solved by the Invention] However, the time T0 during which both the output P-channel MOS transistor 3 and the output N-channel MO5 transistor 4 are off depends on the delay T caused by the delay circuit 2. The off time T0 is influenced by manufacturing variations in the capacity f17 of the delay circuit 2 that creates the delay Td. Therefore, when the off-time To is long, the output S5 is susceptible to disturbance noise. On the other hand, when the off-time To is short, the through current cannot be sufficiently prevented. In other words, the conventional circuit shown in FIG. It had shortcomings.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a through-current prevention circuit that can solve the above-mentioned drawbacks and sufficiently prevent through-current.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a transistor having an output circuit having a complementary inverter configuration in which first and second conductivity type transistors for output are connected in a complementary manner. In the circuit, a first means for detecting a threshold voltage of a transistor of a first conductivity type, a second means for detecting a threshold voltage of a transistor of a second conductivity type, and according to a detection output from the second means, a third means for turning on the second conductivity type output transistor after the output first conductivity type transistor is cut off; and a third means for turning on the output second conductivity type transistor, and the output second conductivity type transistor being cut off in response to the detection output from the first means. and a fourth means for later turning on the output first conductivity type transistor, and a through current flowing through the output first and second conductivity type transistors when the output first and second conductivity type transistors switch. It is characterized by being designed to prevent.

[Function] According to the present invention, each threshold voltage of the P- and N-channel MOS transistors is detected, and depending on the detected output, the output N- and P-channel MOS transistors are
Since each gate signal of the OS transistor is switched, a through-current prevention circuit that conventionally required a delay circuit having a capacitor can be realized without using such a delay circuit, which is advantageous for integration.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

As an embodiment of the present invention, FIG. 1 shows an example of a transistor circuit having an output circuit of a CMOS inverter.

In FIG. 1, the same parts as in FIG. 3 are given the same reference numerals. In FIG. 1, 11 is a P-channel MO
S transistor threshold voltage detection circuit,
12 is an N-channel MOS transistor threshold voltage detection circuit.

The threshold voltage detection circuit 11 is made up of a series circuit consisting of a resistor 13 and a parallel circuit of N-channel MOS transistors 14 and 15, and supplies a drive signal S1 to the gate of the transistor 14. An output signal Sll is extracted from the common connection point, and a gate signal 513 obtained by passing this signal Sll through an inverter 19 is applied to the gate of the P-channel MOS transistor 3 in the output circuit 1.

The threshold voltage detection circuit 12 is composed of a series circuit of a resistor 16 and a parallel circuit of P-channel MOS transistors 17 and 18, and supplies a drive signal Sl to the gate of the transistor 17, and a common circuit between the resistor 16 and the transistors 17 and 18. Output signal S12 is taken out from the connection point.

A gate signal 514 obtained by passing this signal S12 through the inverter 20 is applied to the gate of the N-channel MOS transistor 4 in the output circuit 1.

Further, the gate signal 513 from the inverter 19 is supplied to the gate of the P-channel MOS transistor 18, and the gate signal 514 from the inverter 20 is supplied to the gate of the N-channel MOS transistor 15.

Here, the resistors 13 and 16 are each set to have a sufficiently high resistance, and the N-channel UOS transistor 15
Unless the P-channel MOS transistor 18 is cut off, the signal Sll is prevented from becoming high level and the signal 512 is prevented from becoming low level.

When the drive signal S1 is at a low level, the N-channel MOS transistor 14 is turned off and the P-channel MOS transistor 17 is turned on, so that the output signal S of the detection circuit 11
ll is at a high level, the output signal 512 of the detection circuit 12 is at a low level, and the P-channel MO5 for output of the output circuit 1
) - transistor 3 is on, and output N-channel MO5 transistor 4 is off.

Here, when the drive signal Sl changes from low level to high level, the N-channel MOS transistor 14 is turned on and the P-channel MOS transistor 17 is turned off. As a result, the output Sll of the detection circuit 11 becomes low level, but the output 512 of the detection circuit 12 becomes the output P of the output circuit 1.
It remains at a high level until the gate voltage S13 of the channel MO5) transistor 3 becomes equal to or lower than the threshold voltage of the P channel MO5) transistor 18.

Normally, P-channel MOS transistors 3 and 18 are often formed on the same chip, and in that case, they are considered to have the same threshold voltage, so that the gate voltage S13 is sufficiently lowered and the P-channel MOS
) becomes below the threshold voltage of transistors 3 and 18, and the output of detection circuit 12 changes to low level almost at the same time as output P-channel MOS transistor 3 is cut off. As a result, N channels M for output
OS ) - The transistor 4 is turned on, thereby preventing through current.

Next, when the drive signal S1 changes from high level to low level, the P channel MO5 transistor 17 is turned on and the N
Channel MOS transistor 14 is turned off. As a result, the output signal 512 of the detection circuit 12 becomes high level, but the output signal Sll of the detection circuit 11 remains unchanged until the gate voltage S14 of the output N-channel MO5 transistor 4 becomes lower than the threshold voltage of the N-channel MOS transistor 15. remains at a low level.

Normally, N-channel MOS transistors 4 and 15
are often formed within the same chip, in which case,
are considered to have the same threshold voltage, so that the gate voltage 514 is sufficiently reduced that the N-channel MO
S becomes below the threshold voltage of transistors 4 and 15, and output N-channel MO5) transistor 4
Almost at the same time as the signal is cut off, the detection circuit 11 changes to a high level.

As a result, the output P-channel MO5 transistor 3 is turned on, thereby preventing through current.

FIG. 2 is a time chart for explaining the operation of the circuit according to the embodiment of the present invention shown in FIG.

When the drive signal S1 changes from low level to high level, the output signal Sll and the gate voltage S13 change, but the gate voltage S13 is the P channel MO'S).
- threshold voltage T of transistors 3 and 18;
)11 and reaches a high level, the output signal S1
2 and gate voltage 514 remain unchanged.

Furthermore, when the drive signal Sl changes from a high level to a low level, the output signal 512 and the gate voltage S14 change, but the gate voltage S14 is
) Output signal 51 until it exceeds the threshold voltage Tl12 of transistors 4 and 15 and becomes low level.
1 and gate voltage S13 do not change.

Therefore, according to the present invention, the N-channel MOS transistor is turned on after the P-channel MO5)-transistor is cut off, and the P-channel MOS transistor is turned on after the N-channel MOS transistor is cut off, reducing the through current. It can be prevented.

[Effects of the Invention] As explained above, according to the present invention, P and N
Channel UOS) - Each threshold voltage of the transistor is detected, and each gate signal of the output N-channel MOS transistor and P-channel MOS transistor is switched in accordance with the detected output, so conventionally, a delay circuit having a capacitor is used. The through-current prevention circuit that previously required this can be realized without using such a delay circuit, and therefore,
・It is advantageous for integration.

Additionally, in the present invention, the off-period of the output P and N-channel MO5F transistors, which was dependent on manufacturing variations, can be set to the minimum by detecting the threshold voltage of the MOS transistor. In addition, through-current can be sufficiently prevented.

Note that in the above description, the present invention is applied to P and N channel MOS
) - Although the case of a transistor has been described, the present invention is not limited to this example, but can be applied to a pair of switches that operate in a complementary manner such as on-off or off-on, for example, Of course, the present invention can also be effectively applied to an output circuit configured with a complementary inverter using PNP and NPN bipolar transistors.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the through current prevention circuit of the present invention, Fig. 2 is a time chart for explaining the operation of the circuit shown in Fig. 1, and Fig. 3 is a circuit diagram showing an example of a conventional through current prevention circuit. FIG. 4 is a time chart for explaining the operation of the circuit shown in FIG. 1... Output circuit, 2... Delay circuit, 3... P-channel MOS for output) - transistor, 4
... N-channel MOS transistor for output, 5.6.
...Inverter, 7.Capacitor, 9.Nands gate, lO.Nor gate, 11.N-channel MOS transistor threshold voltage detection circuit, 12.P-channel MO5)-transistor threshold. Hold voltage detection circuit, 13.18...Resistor, 14.15...N channel MOS transistor, 1
7.18...P channel MOS transistor, 19.
20...Inverter. Figure 2

Claims (1)

[Claims] 1) In a transistor circuit having an output circuit having a complementary inverter configuration in which first and second conductivity type transistors for output are connected in a complementary manner, a threshold voltage of the first conductivity type transistor is detected. a first means; a second means for detecting a threshold voltage of a transistor of a second conductivity type; and a second means for detecting a threshold voltage of a transistor of a second conductivity type;
a third means for turning on the output second conductivity type transistor after the conductivity type transistor is cut off;
and fourth means for turning on the output first conductivity type transistor after the conductivity type transistor is cut off, and when the output first and second conductivity type transistors switch, the output first and second conductivity type transistors A through-current prevention circuit characterized by preventing through-current flowing through a two-conductivity type transistor.