JPH01184783A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent the generation of abnormal current consumption, power supply voltage variation or malfunction due to these conditions by providing the title device with a deciding circuit for comparing address signals supplied to respective writing/reading circuits, and when plural address signals coincide with each other, setting only one of these signals to a writable state. CONSTITUTION:The said semiconductor storage device provided with plural writing/reading circuits 3a, 3b to independently write/read out data detects the coincidence of addresses and the writable state of both the circuits 3a, 3b. Thereby, simultaneous writing of data in the same address from plural writing circuits can be removed and data stored in a memory cell can be prevented from being undefined. Consequently, the generation of abnormal current consumption, power supply voltage variation or malfunction due to said conditions can be prevented.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device that has two sets of write/read circuits for one set of memory cells and can independently write and read data. [Technology] A conventional semiconductor memory device having two sets of write/read circuits for one set of memory cells has one
A write/read circuit 3a for the set of memory cells 1,
3b, address decoders 4a, 4b, timing circuit 5
．． It has memory cells a and 5b independently, and memory cell 1
Data can be written and read independently.

[Problems to be Solved by the Invention] In the conventional semiconductor memory device described above, when two write circuits write different data to a memory cell, if the specified addresses are the same, However, there are problems in that potential tension occurs between data, making it impossible to determine the value stored in the memory cell, abnormal current consumption in the memory cell, power supply voltage fluctuation, and malfunction due to this.

[Differences between the invention and the prior art] In contrast to the conventional semiconductor memory device described above, the present invention detects a state in which a plurality of write circuits attempt to write to the same address of a memory cell at the same time, and The difference is that it is possible to control the write operation based on the data and avoid potential tension between data.

[Means for Solving the Problems] The gist of the present invention is to provide a semiconductor memory device including a plurality of memory cells and a plurality of write/read circuits for respectively writing or reading data to or from memory cells specified by an address signal. A discrimination circuit is provided which compares the address signals supplied to each write/read circuit and, when a plurality of address signals match, sets only one of the plurality of write/read circuits to a writable state.

[Example] Published by Natsume Tosha Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention. When the block operation clock signals BEa and BEb are set to 0 and the writable signals WEa and WEb are writable, each data is sent to the write/read circuits 3a and 3b and the selector 2.
is written to the address of the memory cell 1 designated by the address encoders 4a and 4b. Furthermore, when the write enable signals WEa and WEb are disabled in the block operation clock signals BEa and BEb rlJ, data is read from the designated address.

Furthermore, if one write enable signal BEa allows writing and the other does not, one side (BEa side) is for writing and the other is for reading. Here, write enable signals WEa, W
If both Eb are writable and the two addresses are the same, that is, if two write circuits try to write to the same address at the same time, 2.
A match of addresses is detected by the human-powered EXNOR element group 12 and the n+1 human-powered AND element 11, and
The AAND element 14 detects that it is in a writable state. The output of the three-man power NAND element 14 is used by the two-man power AND element 13 to cut off the signal sent from the timing circuit 5b to the selector 2, and to cut off the circuit from the write/read circuit 3b to the memory cell 1. As a result,
Data is written to the memory cell 1 only from the write/read circuit 3a, and it is possible to avoid potential tension between the written data, and the value stored in the memory cell 1 is not determined. Such a situation will not occur. This makes it possible to prevent abnormal current consumption in the memory cell 1, power supply voltage fluctuations, and malfunctions caused by these.

Basket lambda row FIG. 2 is a block diagram showing a second embodiment of the present invention.

Detection when data is simultaneously written to the same address from two write circuits is performed using the same procedure as in the first embodiment. Here, the signal detected by the three-man-powered NAND element 13 is sent to the two-man-powered AND elements 13a and 13b, and the operation of the selector 2 is stopped, so that the value stored in the memory cell l is held as it is. It is something.

[Operations and Effects of the Invention] As explained above, the present invention provides a semiconductor memory device that is equipped with a plurality of sets of write/read circuits and can independently write and read data, and is capable of achieving address matching and two sets of write/read circuits. detects a state in which both of the memory cells are write-enabled, avoids a situation where multiple write circuits write data to the same address at the same time, and prevents the data stored in the memory cell from becoming uncertain. This has the effect of preventing abnormal current consumption and power supply voltage fluctuations in cells, as well as malfunctions caused by them.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of a semiconductor memory device of the present invention, and FIG. 3 is a block diagram of a conventional semiconductor memory device. It is a diagram. 1...Memory cell, 2...Φ...Selector, 3a, 3b...Writing/reading circuit, 4a, 4b
...Address decoder, 5a, 5b...timing circuit, 11...n+1 manual AND element, 12...
・・2-man power EXNOR element, 13.13a, 13b・・
・2-manpower AND element, 14...3-manpower NAND
Element, AO, AI, An. BO, Bl, Bn...Address signal, l0
aO, IOam. 10bO, IObm...Human output data signal, BE
a, BEb...Block operation clock signal, WEa,
WEb...Writable signal. Patent Applicant: NEC Corporation Representative, Patent Attorney: Kiyoshi Kuwai −

Claims (1)

[Scope of Claims] In a semiconductor memory device including a plurality of memory cells and a plurality of write/read circuits that respectively write or read data in memory cells specified by address signals, 1. A semiconductor memory device comprising a determination circuit that compares address signals and sets only one of the plurality of write/read circuits to a writable state when the plurality of address signals match.