JPH01185007A - gain control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gain control circuit used in an AGC circuit, an electronic volume, etc.

[Summary of the invention].

According to the present invention, by connecting differential amplifiers in parallel in a gain control circuit, the DC bias of the output is stabilized even when the gain is changed.

[Conventional technology]

A conventional gain control circuit is shown in FIG.

In the figure, 1.2 is an NPN transistor 3 and a resistor 4.
5.6 is a voltage source, 7 is a resistor, 8 is a PNP transistor, and 9 is a signal source. 10 is an output terminal. The operation is as follows.

The current flowing to the collector of the PNP transistor 8 is a DC current 6 determined by the voltage source 4.5 and the resistor 7, and the signal source 9.
The signal current is determined by the voltage and the resistor 7. Here, if the voltage difference between the voltage sources 4.5 and 5 is made variable, the ratio of the current flowing through the NPN transistor and 2 can be made variable.For example, the ratio of the current flowing through the NPN transistor and 2 can be set to 1:1. When the voltage difference of the voltage source 4.5 is set to , the current IC+ flowing through the NPN transistor is the voltage V01 of the output terminal 10 is the voltage of the voltage source 6.6 If the resistance value of the resistor 3 is Rt, then Vo+=Vi RL X I at
(2) Substituting (1) here, VO1=V6-RL X -X (IE +is)
(3) 1+1 Next, the current ratio flowing through the NPN transistor and 2 is 1:
If the voltage difference of voltage vA4.5 is set so that the voltage is 10, the current ICIO flowing through the NPN transistor is equal to the voltage V at the output terminal 10. Similarly, for IQ, V o+o
= V s Ri, X I cl.

As can be seen by comparing equations (3) and (5), in the case of equation (3), a signal proportional to 172 of the signal current is output from the output terminal 10, while in the case of equation (5), a signal proportional to 172 is output. It was found that a signal proportional to /11 can be extracted, and it can be used as a gain control circuit.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology has a problem in that when the gain is made variable, the DC bias of the output changes. That is, in equations (3) and (5), if 18=0, a DC bias point is obtained, and the voltage, V DO
L, V oc+o is VDCL = V6 Rt,
x x IQ (6), and it can be seen that changing the gain changes the MK bias.

The present invention is an attempt to solve these problems, and its purpose is to provide a gain control circuit in which the DC bias of the output is stable even when the gain is made variable.

[Means to solve the problem]

The gain control circuit of the present invention connects the emitter of the first NPN transistor to the emitter of the second NPN transistor, connects the emitter of the third N'PN transistor and the emitter of the fourth NPN transistor, and connects the emitter of the first NPN transistor to the emitter of the second NPN transistor. 1st NP
Connecting the base of the N transistor and the base of the third NPN transistor, connecting the base of the second N P N l- transistor and the base of the fourth NPN transistor, and connecting the base of the first NPN transistor. and the collector of the fourth NPN transistor are connected and grounded via the first resistor, and the collector of the second NPN l-transistor and the third collector are connected and grounded. , a first voltage source is connected to a connection point between the base of the first N P N l-transistor and the base of the third NPN transistor, and the base of the second N P N l-transistor and the fourth A second voltage source is connected to the connection point of the base of the NPN transistor, a collector of the first PNP transistor is grounded, and a second resistor is connected to the emitter of the first PNP transistor.
The other end of the second resistor is connected to the emitter connection point of the first and second NPN transistors, and the third and fourth NPN transistors are connected to each other.
A third resistor is connected to the emitter connection point of the N transistor, and the other end is grounded.

[For production]

According to the above configuration of the present invention, one of the two sets of differential amplifiers operates as an AGC circuit, and the other differential amplifier operates to correct the varying DC bias point. .

〔Example〕

FIG. 1 is a circuit diagram of a gain control circuit according to the present invention. In FIG. 0, 1.2.11.12 is an NPN transistor 3.
．． 7.13 is a resistor, 8 is a PNP transistor, 9 is a signal source, 4.5.6 is a voltage source, and 10 is an output terminal. The operation is as follows.

The sum of DC currents flowing through the emitters of NPN transistors 2 is 181, and the sum of DC currents flowing through the emitters of NPN transistors 11 and 12 is I6□. Then, the sum of the AC signal currents flowing through the emitter of the N P N transistor 1.2 is assumed to be is.

Here, the voltage difference between voltage sources 4.5 and NPN transistors 1.
If the voltage difference of voltage source 4.5 is set so that the current ratio flowing to the emitter of transistor 2 is 1:1, NPN1 to transistor 1
The collector current ICI flowing in is as follows.

On the other hand, since the ratio of the current flowing to the emitter of the NPN transistor 1.12 is also 1:1, the collector current flowing to the NPN transistor 1c+2 becomes, and the current ILI flowing to the resistor 3 is the sum of equations (8) and (9). It will look like this:

ILl= (It++Ic2+is)
<10) Next, if the voltage difference of voltage source 4.5 is set so that the ratio of current flowing to NPN transistor and transistor 2 is 1:10, kJ flowing to NPN l-transistor 1: h
The flow lc1 becomes.

On the other hand, since the current ratio flowing to the emitters of NPN transistors 11 and 12 is 10:1, NPN transistor 1
Collector current 1 crt flowing through resistor 2 is current ILL flowing through resistor 3. is the sum of equations (11) and (12), and is as follows.

As can be seen from equations (10) and (13), the voltage source 4.5
As in the case of FIG. 2, the gain can be varied by making the voltage difference variable.

Next, in order to find the DC bias current flowing through the resistor 3, if i s = 0 in equations (10) and (13), the DC bias current in each case is .

C1, I DCIO are calculated and each 1oc+ = (IEl+IE2)
(14). And I E, = I E□= I
In other words, if the value of resistor 7.13 is set so that the sum of the DC bias currents flowing to the emitter of NPN transistor 2 and the sum of the DC bias current flowing to the emitter of NPN transistor 1.12 are the same, ( 1
4), Equations (15) are 1oc+ = (It + It) = I + = (
16).

〔Effect of the invention〕

As described above, according to the present invention, (16), (17)
As can be seen from the equation, by connecting two sets of differential amplifiers in parallel, the DC bias at the output terminal 10 can be stabilized even if the gain is made variable. If the gain control circuit of the present invention is used as a video camera's video tvI@ device, the DC bias point is stable, so the response of pedestal clamps, etc. becomes faster, and even when the brightness of the subject changes suddenly. However, a stable image can be obtained. Furthermore, when used as an electronic volume for audio, etc., the DC bias point remains stable even if the gain is made variable, making it possible to suppress the generation of unnecessary noise such as pop noise.

[Brief explanation of the drawing]

FIG. 1 is a gain control circuit diagram according to an embodiment of the present invention. FIG. 2 is a conventional gain control circuit diagram. ■, 2.11.12...NPN transistor 8...
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Claims (1)

[Claims] (1) Connect the emitter of the first NPN transistor to the emitter of the second NPN transistor, and
The emitter of the transistor is connected to the emitter of the fourth NPN transistor, the base of the first NPN transistor is connected to the base of the third NPN transistor, and the base of the second NPN transistor is connected to the emitter of the fourth NPN transistor. NPN
The bases of the transistors are connected, the collectors of the first NPN transistor and the fourth NPN transistor are connected, grounded via the first resistor, and the second
The collector of the NPN transistor and the collector of the third NPN transistor are connected and grounded, and the collector of the first NPN transistor is connected and grounded.
A first voltage source is connected to the connection point between the base of the PN transistor and the base of the third NPN transistor, and a second voltage source is connected to the connection point between the base of the second NPN transistor and the base of the fourth NPN transistor. A voltage source is connected, the collector of the first PNP transistor is grounded, a second resistor is connected to the emitter, and the other end of the second resistor is connected to the first PNP transistor.
, a gain control circuit characterized in that the second resistor is connected to the emitter connection point of the second NPN transistor, the third resistor is connected to the emitter connection point of the third and fourth NPN transistors, and the other end is grounded. .