JPH01200647A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of elements required to constitute a delay circuit by a method wherein a power supply voltage which is lower than that of a logic circuit part is applied to the delay circuit part and the delay time of a signal in individual logic gates is delayed. CONSTITUTION:Because a delay circuit part 2 is driven by a power supply voltage Vcc' (e.g., 2.5V) which is lower than a power supply voltage Vcc (e.g., 5V) of logic circuit parts 1, 4, the delay time of a signal to be input from the logic circuit part 1 to the logic circuit part 4 through individual inverters 2a of five stages is also longer than the delay time of a signal in the logic circuit parts 1, 4. Accordingly, the same delay time can be realized by the small number of inverters 2a as compared with a case driven by the power supply voltage Vcc; the number of FETs required to obtain the desired delay time can be made small; more FETs can be used in the logic circuit parts 1, 4 and the like.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a master slice type semiconductor integrated circuit device (LSI) which is formed by arranging transistors of the same size in an array and has a delay circuit section.

<Prior art> The master slicing method is a method in which elements such as transistors of the same size are arranged in an array according to a designed basic pattern, and the connection between the elements is changed as necessary to manufacture individual LSIs. means. The delay circuit section of an LSI made using this master slice method is made up of multistage logic gates made by combining transistors, etc., and delays signals by passing them through these logic gates. It is.

<Problems to be Solved by the Invention> Incidentally, the delay circuit can also be realized by increasing the delay time per gate stage by narrowing the gate width or increasing the gate length of each transistor. However, in the above-mentioned master slice type LSI, the transistors fabricated on the master wafer are all of the same size and are aimed at high-speed operation, so the delay time per stage is short. Therefore, if you try to realize a delay circuit using the conventional LSI mentioned above, you will have to increase the number of stages of logic gates, which will require many transistors and other elements, which will be used in logic circuits other than delay circuits. The disadvantage is that the number of elements that can be made is reduced.

Therefore, an object of the present invention is to focus on the fact that the delay time of a transistor gate changes depending on the power supply voltage, and to make it possible to configure a delay circuit section with a small number of elements, and to use more elements in a logic circuit section, etc. An object of the present invention is to provide a master slice type semiconductor integrated circuit device (LSI) capable of performing the following steps.

Means for Solving the Problems> In order to achieve the above object, a master slice type semiconductor integrated circuit device of the present invention includes a logic circuit section, a logic circuit power supply line that supplies power to the logic circuit section, and an input The present invention is characterized in that it includes a delay circuit section that delays and outputs a signal, and a delay circuit power supply line that is separate from the logic circuit power supply line and that supplies power to the delay circuit section.

Effect> The signal delay time in each MOS type transistor or the like constituting a semiconductor integrated circuit device becomes longer as the power supply voltage becomes lower. Therefore, if a low power supply voltage is applied to the delay circuit power supply line from the logic circuit power supply line, the delay time per gate stage of the delay circuit section will become longer, and Hiroshima's desired result will be achieved with fewer stages, that is, fewer transistors. You can get the delay time.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 is a schematic diagram showing an embodiment of a master slice type semiconductor integrated circuit device (LSI) of the present invention.
4 is a logic circuit section, 2 is a delay circuit section which is formed by connecting inverters 2a in multiple stages and delays and outputs the human input signal from the logic circuit section 1, and 3 is a section for raising the level of the output signal of this delay circuit section 2. 5 is a logic circuit power supply line that supplies the 711 source voltage Vcc to the logic circuit section 1.4 and the level conversion circuit section 3; 6 is the delay circuit section; 2 and a delay circuit power supply line for supplying a power supply voltage Vcc' lower than the power supply voltage Vcc to the level conversion circuit section 3, and each circuit section 1.2,
3.4 is specifically constructed by appropriately connecting MOSFETs (MO8 type field effect transistors) of the same size fabricated in an array on a master wafer.

FIG. 2 is a circuit diagram showing an example of the configuration of the level conversion circuit section 3. As shown in FIG. This level conversion circuit section 3 has N.

Front-stage CM consisting of P-channel FETs (Tn, Tp)
The first and second parallel connections are made by connecting the OS inverter IO and three N-channel FETs (Tn) in parallel! ? E.T.
11.12, and first and second series FETs 13 and 14 each formed by connecting three P-channel FETs (Tp) in series.
and a subsequent inverter 15.

Assuming that the I-I signal is currently input to the input terminal IN, the FET (T
n) and the second parallel F'ET 12 and the first series FET
l3 is turned on, the first parallel FET II and the second series FE'l
'14 is off and the 1 summer signal is output to the output terminal OU '1', when an L signal is input to the input terminal IN, the FE'r(Tp) of the CMOS inverter lO and the first Parallel rjET l 1 turns on and parallel FET
12 is turned off. At this time, the node 17 is connected to the second parallel F
'ET12. The potential of the node 16 is not determined because the second series 17 E'1' and 14 are both off, but the first parallel r;'Eq'tt is on, and this ability is the first series FET l3. Therefore, the potential of the node 16 becomes L regardless of the input of the first series FET 13, which has the same potential as the node !7.As a result, the potential of the second series FET 14 becomes L.
is turned on, the first series FET 13 is turned off, and an L signal is output to the output terminal 00'r.

Similarly, when the input changes from L to 11, the second series FE
Due to the difference in performance between T14 and the second parallel r'ET l2, I-
1 is output.

FIG. 3 is a plan view showing a specific pattern of the embodiment shown in FIGS. 1 and 2. FIG. In this LSI, rectangular N diffusion regions 20 are formed at equal intervals in the vertical direction on the left side of the substrate shown in FIG. 3, and similarly rectangular P diffusion regions 21 are formed on the right side of the substrate. An N-channel FE is formed by forming a pair of extending polysilicon gates (G n, G n).
On the other hand, a pair of polysilicon gates (Gp, Gp) extending in each PtM region 2 is formed to form a P-channel F'ET (T[)), and the left N-channel side Connect the ground wire GND to the terminal, and V to the right P channel side.
Power supply lines 5 and 6 for supplying voltages cc and Vcc' are formed vertically.

And the above N, P channel F'ET (Tn, Tp)
, the ground line CND, and the power supply line 5.6 are appropriately connected to each other by wiring 23 through a large number of contact holes 22 to form a circuit.
4, corresponding to the delay circuit section 2 and the level conversion circuit section 3, respectively.

That is, the delay circuit section 2 includes N and P channel FETs (
It consists of five stages of CMOS inverters 2a (see FIG. 1) consisting of Tn, Tp) connected in series, and the incoming J signal from the logic circuit section 1 is inverted every time it passes through gates G, .about.G.

Further, as described in FIG. 2, the level conversion circuit section 3 includes a CMOS inverter lO and an N-channel
The first and second parallel FETs II and 12 each have three parallel FETs (Tn) connected in parallel, and the first and second series FETs 1 each have three P-channel FETs (Tp) connected in series.
3. +4 and CMOS Impark 15 in the latter stage.

Then, the drain of the final stage of the level conversion@step section 3 is connected to the gate G1 of the first stage of the next logic circuit section 4. is connected to.

The function and operation of the LSI having the above configuration will be described next.

The delay circuit section 2 is a logic circuit section! , 4 power supply voltage Vcc(
For example, 5 V) is lower than the power supply voltage Vcc' (for example, 2.
5V), the delay time of the signal that passes through each of the five stages of inverters 2a from the logic circuit section 1 and is manually input to the logic circuit section 4 is also shorter than the delay time of the signal in the logic circuit section 1.4. become longer. Therefore, the same delay time can be achieved with a smaller number of inverters 2a than in the case of driving with the power supply voltage Vcc, the number of FETs required to obtain the desired delay time is small, and the logic circuit Part 1.4 etc.
The advantage is that more FETs can be used.

Incidentally, if a large current consumption is acceptable in the backup mode or during operation, the level conversion circuit section 3 may be configured as shown in FIG. 4.

This level conversion circuit section 3° is a CMOS shown in FIG.
The P channel FET (TI) of the inverter 10 is
A series FET 25 driven by the power supply Vcc, which is formed by connecting three ET (TI)) in series, an N-channel FET (Tn) of a CMOS inverter lO, and a parallel FET 26, which is formed by connecting three FETs (Tn) in parallel. They have been modified respectively. In this level conversion circuit 3°, series inverter 2
Since the power supply voltage Vcc applied to the source Sp of 5 is higher than the signal level (V cc' ) of the input terminal IN, when a signal of +( corresponding to V cc' is input to the input terminal IN, the series The PET 25 does not turn off completely but becomes partially conductive, and an L signal is input to the inverter 15, which is inverted and an output signal of r is obtained at the output terminal OUT. A through-current flows to the ground through the capacitor, increasing power consumption, and the same drawback occurs during backup mode, but the advantage is that the number of elements can be reduced.

FIG. 5 is a graph showing the relationship between the drive voltage and gate delay time of each FET constituting the delay circuit section 2 and the like. As is clear from the figure, when the power supply voltage is halved, the gate delay time increases approximately three to four times. Therefore, the logic circuit section 1.
4, when the power supply voltage Vcc=5■, f of the delay circuit section 2,
If the source voltage is Vcc'-2°5■, the number of elements necessary to construct the delay circuit section 2 can be reduced to 1/3 to 1/4 of the conventional one, and the reduced elements can be used as the logic circuit section 1. .4 etc. can be used.

It goes without saying that the present invention is not limited to the above embodiments.

<Effects of the Invention> As is clear from the above description, the master slice type semiconductor integrated circuit device of the present invention supplies the delay circuit section with a lower power supply voltage than the logic circuit section, thereby reducing the signal delay in each logic gate. By extending the time, the number of elements required to configure the delay circuit can be reduced compared to the conventional one! The number of elements can be reduced to approximately 1/3 to 1/4, and the reduced elements can be effectively used in other circuit sections.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an embodiment of the master slice type LSI of the present invention, FIG. 2 is a circuit diagram showing an example of the level conversion circuit section of FIG. 1, and FIG. 3 is a specific diagram of the above embodiment. FIG. 4 is a plan view showing the pattern, FIG. 4 is a circuit diagram showing another example of the conversion circuit section, and FIG. 5 is a diagram showing the relationship between FET drive voltage and gate delay time. 1.4...Logic circuit section, 2...Delay circuit section, 2a
... Inverter, 3... Level conversion circuit section, 5...
- Power supply line for logic circuit, 6... Power supply line for delay circuit.

Claims (1)

[Claims] (1) In a master slice type semiconductor integrated circuit device in which transistors of the same size are arranged in an array, the logic circuit section, the logic circuit power supply line that supplies power to the logic circuit section, and the input signal are delayed. 1. A semiconductor integrated circuit device comprising: a delay circuit unit that outputs power to the delay circuit unit; and a delay circuit power supply line that is separate from the logic circuit power supply line and that supplies power to the delay circuit unit.