JPH01212118A - Differential circuit - Google Patents

Abstract

PURPOSE:To constitute a differential circuit, for which an output simultaneously goes to be a high level, by executing a clamp to the potential, which is larger than a constant reference voltage to be given to the bases of first and second NPN transistors. CONSTITUTION:When an 'H' is inputted to an enable terminal 104, the common emitters of NPN transistors 101 and 102 are clamped by the 'H' which is inputted to the enable terminal 104. Accordingly, even when either 'H' or 'L' is inputted to an input terminal 103, the both transistors 101 and 102 are simultaneously turned off. Thus, both outputs 105 and 106 simultaneously go to be the 'H'. Thus, when the enable terminal 104 is the 'H', the NPN transistors 101 and 102 are turned off and the outputs 105 and 105 simultaneously goes to be the 'H' even in either case that the input terminal 103 is the 'H' or 'L'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a differential circuit suitable for forming a tristate circuit.

[Conventional technology]

Bipolar/CMOS composite technology is being developed with the aim of combining bipolar transistors and CMOS in a basic circuit to create an LSI that combines the low power consumption and high integration of CMO3 with the high speed of bipolar transistors. This bipolar/CMOS composite technology is a memory,
It is being applied to gate arrays, etc., and products have already been announced by various companies. An output circuit used in a gate array based on this bipolar/CMOS composite technology is disclosed, for example, in Nikkei Electronics ('85.8.12, p. 196). This circuit diagram is shown in FIG. The basic operation is as follows. The output signal of the internal circuit is 201
input to the CMOS inverter. This inverter is an amplifier circuit that allows the internal circuit signal to fully swing up to the power supply voltage.

The output of the inverter 201 is sent to the PMOS transistor 202 and the NMOS transistors 203 and 204.
Each MOS transistor drives 205.206 bipolar transistors. For example, input terminal 207
When IIH" is input to the
3 is on, 203.204 NMOS is off, 2
The NPN transistor 05 is turned on, the NPN transistor 206 is turned off, and the output of 208 becomes "H". Conversely, when "L" is input to the input 207, the input is inverted by the inverter 201 and becomes "Hlj. Therefore, PMO3 of 202 is off, and 203, 204 (7) N
The MOS is turned on, the NPN transistor 205 is turned off, and the NPN transistor 206 is turned on, so that the output of 208 becomes 'L''. In this way, the conventional output circuit receives internal signals with the CMOS, and outputs them with the CMOS. Complementary operation was achieved by driving bipolar, and low power consumption was achieved.

[Problem to be solved by the invention]

In the above conventional technology, since the input section has a CMOS configuration, two contradictory control signals are required when configuring a tri-state circuit, resulting in an increase in the number of elements. This will be explained in detail with reference to FIG. FIG. 3 shows the output circuit explained with reference to FIG. 2 as a tri-state circuit. The extra elements compared to FIG. 2 are 303 (7) PMOS, 304, 305, 30
6(7)NMOS. These four MOSs are elements necessary to configure a tri-state circuit. Also,
301 and 302 are enable terminals.

Conflicting control signals are input to 301 and 302.

Below is a brief explanation of the operation: 301'''L 7F
is input, and when "'H" is input to 302, 303 is turned on, 305 and 306 are turned off, and 304 is turned on. In this case, the circuit operates normally according to the input signal 207,
Output the output signal. For example, when "L" is input to 207, the input is inverted by the inverter 201, 202 is turned off, and 203 and 204 are turned on. Therefore, 205 is off.

206 turns on and the output becomes igL. On the other hand, when "H" is input to input 207, the input is inverted by 201 and becomes g(L lj, and 202 turns on.

203 and 204 are on, so 205 is on, 2
06 is turned off and the output becomes "H".

In this way, when "L" is input to 301 and "IIH" is input to 302, 1 normal operation is performed.
When "tl L" is input to 302, 303 is off, 3
05, 306 is on, 304 is on, so 205,
206 are both turned off and the output is in a high impedance state.

In this way, by inputting contradictory control signals to 301 and 302, this conventional circuit outputs the output signal ((HII, #LIt) to 208 according to the input signal of 207, or enters a high impedance state. .

However, in this conventional circuit, four new MOSs of 303, 304, 305, and 306 are added to configure the tristate circuit, and two contradictory MOSs are added to control these MOSs. It is necessary to input a control signal.

An object of the present invention is to provide a circuit that does not require the addition of new elements even when configuring a tri-state circuit, and that requires only one type of enable signal to control the tri-state circuit.

[Means to solve problems]

The means for achieving the above object will be roughly divided into two parts and explained below. The first is to use a differential circuit whose outputs are II Hlj at the same time, and the second is to input the output of the first differential circuit to the gate of a single channel MOS. First, the first differential circuit will be explained with reference to FIG. 1(a). 1
01 and 102 are NPN transistors whose emitters are connected to each other and have a common potential. The base of 102 is fixed to a certain reference potential VaS, and the base of 1010
03 is the input terminal. Emitter 10 of 101 and 102
4 is an enable terminal, and the collector 106 of 101 and the collector 105 of 102 are output terminals. The circuit operation will be explained below. First, consider the case where the enable terminal 104 is high impedance. At this time, V is applied to input 103.
When a voltage uH higher than aa is input, 101 turns on 10
2 is off, 105 is "H", and 106 is "L".

Conversely, if a voltage lower than Vaa is input to input 103, 1
01 is off, 102 is on, 105 is “L”, 1
06 becomes "H", and this series of operations is the same as that of a normal differential circuit. On the other hand, consider the case where 'H' is input to the enable terminal 104.

At this time, the common emitter of 101 and 102 is.

It is clamped to "H" input to 104. Therefore, when either tg Ht+ or 11 L" is input to the input terminal 103, both 101 and 102 are turned off at the same time. Therefore, the outputs 105 and 106 are both turned off at the same time.
The above operation is summarized as shown in Table 1 below.

Table 1 Truth Table However, 112 $1 represents a high impedance state.

Next, the second half of the means will be explained with reference to FIG. 1(b). (
In b), an inverter made of a single channel MOS is connected to the outputs 105 and 106 of circuit (a). Since the differential circuit has been described in detail above, the operation of the latter stage will be explained below.

107 and 108 are PuO2, 109 and 110 are N
It is a PN transistor. 105 is “L” 106 is “H”
”, 107 is on and 108 is off, so 109 is on and 110 is off, and the output 111
becomes “H”.

Conversely, when 105 becomes "H" and 106 becomes "L", 107 becomes OFF, 108 becomes ON, 109 becomes OFF, 110 becomes ON, and the output 111 becomes "L". 10 if both 105 and 106 become rtH”
7 and 108 are turned off, and both 109 and 110 are also turned off. Therefore, the output 111 is in a high impedance state. This operation can be summarized as follows.

From Table 2 Truth Table, it can be seen that Figure 1(b) constitutes a tri-state inverter. As is clear from the above explanation, the circuit shown in FIG. 1(b) can be made into a tri-state circuit by simply providing the terminal 104, so that the number of elements does not increase.

[Effect]

The following explanation will be given with reference to FIG. First, FIG. 1(a) shows a differential circuit in which the outputs become "H" at the same time, as shown in Table 1 mentioned above. That is, when the enable terminal 104 is in high impedance.

If 103 is “H”, 105 is “H” and 106 is “H”
If 103 is glL, then 105 is “L”
, 106 become "H". On the other hand, enable terminal 104
When is “H”, 101 and 102 are off, and 105 and 103 are both “H” and “L”.
06 connects an inverter constituted by a single channel MOS to a differential circuit that performs 6 or more operations that become "H1M" at the same time. This circuit is shown in FIG. 1(b). That is.

By inputting the complementary signals outputted to the outputs 105 and 106 of the differential circuit to the gate of the single channel MOS, the single channel MOS performs complementary operation.

For example, when 105 is "H" and 106 is "Ln".

107 is off, 108 is on, 109 is off, 1
10 is turned on, so the output 111 becomes It L tt. Conversely, 105 is #L 31, 106 is 41 HI+
At this time, 107 is on, 108 is off, 109 is on, and 110 is off, so the output 111 becomes "H".

On the other hand, when both 105 and 106 become "HIt" at the same time, both 107 and 108 are turned off, 109 and 110 are also turned off at the same time, and the output 111 becomes a high impedance state.As described above, the output becomes It H71 at the same time. By using an inverter consisting of a differential circuit and a single channel MO3, a tri-state inverter can be constructed without increasing the number of elements.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

The output circuit according to this embodiment outputs the signal of the internal circuit operating between the power supply -5, 2V and GND in FIG. 2 to the first power supply +5V.
It is output as a TTL level signal between (2) and GND. Based on the above, the circuit configuration and circuit operation will be described below. The circuit can be roughly divided into input section 4
07, a level shift section 408, and an output section 409. The power supply terminal of the input section is connected to GND, and the power supply terminal 406 is connected to the second power supply (-5, 2V). A signal from the internal circuit is input to the input terminal 401 . The low level VIL of the internal circuit signal is -5.2V, and the high level vro is a signal with an amplitude of Ov or close to this.

The input section 407 converts the input signal into a signal with an amplitude of approximately 0.8 V.

At the output 103 of the input section, a signal having an amplitude of approximately 0.8 .mu.m after conversion appears. In this way, the reason why the internal circuit signal having an amplitude of about 5V is converted to an amplitude of about 0.8V at the output 103 of the input section is to minimize the reverse bias applied between the base and emitter of the NPN transistor 101. This is to suppress it. Next, the power supply terminal 404 of the level shift section is connected to the first power supply (+
5 V), and the power supply terminal 406 is connected to the second power supply (
-5,2V). This level shift section 408
In this method, the signal at the output 103 of the input section is level-shifted and amplified, and a complementary signal is created.

The potential is lower than GND, and the amplitude is approximately 0.8V (7
) 103(7) signal is converted at 105, 106 into a positive potential amplitude having an amplitude of approximately 5V.

The signals 105 and 106 are inverted from each other. lastly,
The power supply terminal 404 of the output unit 409 is connected to the first power supply (+5
V), and the power supply terminal 405 is connected to GND. The output section 409 is a buffer circuit, and 105.106
outputs a single-ended complementary signal. Output terminal 111
A TTL level signal is output. PMOS403
The functions of and 407 will be described later. The circuit configuration is as described above, and the circuit operation will be explained below. In the following explanation, the input signal "Hjl level 11 L?j
Level and “H” level of the output 103 of the input section 407 “L”
"Level and level shift section output 105° 106"H
” level “1L” level and output signal 1 (H” level t
Each tL" level has a different value, but for simplicity, each 'H" level is all ttH", each (
j L All 11 levels are written as "L". Input terminal 4
When L'H'' enters 01, 103 becomes "L". Therefore, 101 becomes OFF, 102 becomes ON, and 106 becomes "H".
, 105 become "L". 107 is turned on, so 10
Since 9 is on and 407.108 is off, 110 is off, so KI H11 is output to the output terminal 111. Furthermore, when “L” is input to the input terminal 401,
103 is tt Htp, 101 is on, and 102 is off. Therefore, 105 becomes "H" and 106 becomes 'L'. Since 107 is off, 109 is off, and 407,1
Since 08 is turned on, 110 is turned on, and therefore j(L 7+ is outputted to the output terminal 111. From this operation, this embodiment constitutes a through circuit. It is possible to change this embodiment to an inverter circuit. is easily possible, i.e. connect 105 to the collector of 101 and connect 106 to the collector of 10
Connect to the second collector. In such a configuration, since a signal that is inverted from the circuit operation described above is output, the circuit ends up being an inverter circuit. Further, if it is desired to configure a multi-input logic, the logic can be configured using CMOS of the input section 407. Furthermore, the feature of this embodiment circuit is that PMO3403
By adding , a tri-state circuit is constructed. When "H" is input to the enable terminal 402, the PMOS 403 is turned off and the circuit operates normally.

On the other hand, when #L u is input to 402, PMOS403
is on, the emitters of 1o1 and 102 are clamped to high level, and both 101 and 102 are turned off. Therefore, 105.106 are both 'H' and 107
゜108.407(7) PuO2 is completely off, that is, both 109 and 110 are off.

Output 111 becomes high impedance. Finally, 40
7(7) PuO2 is a base supply MOS of 110. When 106 is j(L''), 407 continues to supply the base current to 1104, so 110 maintains the on state.

Therefore, the output 111 connected to the TTL circuit is T
It can sufficiently absorb the sink current IOL from TL,
11 L'' of output is maintained.

In addition, in this embodiment, the single channel MOS is PuO2
Although this is configured using NMOS, it is also possible to configure this using NMOS.

FIG. 5 shows a circuit in which the embodiment shown in FIG. 4 is partially modified. The overall circuit configuration and circuit operation are the same as the embodiment shown in FIG. The changed parts are that a Schottky diode 502 is inserted between the collector of the NPN transistor 110 and GND, and a Schottky diode is inserted between the collector of the NPN transistor 111 and GND. By inserting a diode in this way, the NPN transistor 11
The low level of the collectors of 0 and 111 can be clamped to the GND level. This clamp prevents saturation of the NPN transistor and allows the circuit to operate stably.

Furthermore, although the embodiments shown in FIGS. 4 and 5 constitute a through circuit, the inverter circuit can be configured by connecting the terminal 105 to the collector of the transistor 110 and connecting the terminal 106 to the collector of the transistor 111. Can be configured.

〔Effect of the invention〕

According to the present invention, it is possible to configure a differential circuit whose outputs are simultaneously ttH''.Furthermore, by using the differential circuit of the present invention and a single channel MOS, it is possible to configure a tri-state circuit. A state circuit can be constructed without adding new elements.First of all,
A differential circuit in which the outputs become 'H' at the same time is realized by clamping the common emitters of the transistors forming the differential pair to 'H'.
This corresponds to inputting 11 H11 to the 04 terminal.

On the other hand, for the differential circuit to operate normally.

104 may be in a high impedance state.

The gate of a single channel MOS is connected to the output of this differential circuit, as shown in FIG. 1(b), for example.

Since complementary signals are output from the outputs 105 and 106 of the differential operation circuit, the single channel MOSs 107 and 108 perform complementary operations. An inverter circuit can be configured by this operation. Further, when the outputs 105 and 106 become gtH'' at the same time, both single channel MOSs 107 and 108 are turned off.

Both NPN transistors 109 and 110 are also turned off, and the output 111 becomes a high impedance state.
As described above, by applying a control signal to the common emitter 104 of the differential circuit, a tristate circuit can be configured without adding any elements.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of the present invention, Figure 2 is a conventional circuit diagram, and Figure 3 is a conventional circuit diagram.
4 is a circuit diagram of an embodiment of the present invention, and FIG. 5 is a circuit diagram of a partially modified embodiment of FIG. 4. 101.102...NPN transistor, 103...
・Input terminal, 104... Enable terminal, 105°1
06...Output terminal, 107,108・PuO2,1
09,110...NPN transistor, 111...
Output terminal, 202 ・PM OS, 203, 204 ・
...NMO3,205,206...NPN transistor, 301.302...Enable terminal, 303...
・PuO2,304,305,306-NMOS,40
1... Input terminal, 402... Enable terminal, 40
3-P M OS, 407., blade section, 408-17 bell shift section, 409... output section. (b) -Ding-

Claims (1)

[Claims] 1. On the same semiconductor substrate, the emitter of the first NPN transistor and the emitter of the second NPN transistor are connected, the base of the first NPN transistor is the input terminal, and the base of the second NPN transistor is connected to the emitter of the second NPN transistor. In a differential circuit in which the base is fixed to a constant reference voltage, an impedance element is connected to the collector of each NPN transistor, and the collectors of the first and second NPN transistors are respectively output terminals, the first NPN transistor By clamping the base of the second NPN transistor to a potential higher than a certain reference voltage applied to the base of the second NPN transistor, the collectors of the first and second NPN transistors become high level at the same time. dynamic circuit. 2. In claim 1, the first and second NPs
A differential circuit characterized by connecting the collector of an N transistor to the gate of a single channel MOS.