JPH01243707A - Multiplying circuit - Google Patents

Abstract

PURPOSE:To facilitate the three multiplication and odd number multiplication with a simple and smaller elements by providing a means to generate an output signal having an odd number of pulses for every cycle of a triangular wave signal. CONSTITUTION:In a multiplying circuit 10, a triangular waveform signal generating circuit 5 converts the input signal at frequencies Fsc into a triangular waveform signal (a). A comparison circuit 6 consists of first and second differential type level comparators CP1 and CP2, and respectively discriminates the signals (a) by first and second reference levels V1 and V2. In such a case, the reference levels V1 and V2 are respectively set at the level points 2/3 and 1/3 of an amplitude Vm of the signal (a). By executing a logical-processing by means of a product-logic and a sum-logic for two comparative outputs (a<V1) and (a<V2) obtained at every level points (V1=2Vm/3) by means of the comparison circuit 6, a logical circuit 7 generates an output signal (a<V1).(a>V2)'+(a< V1)'.(a>V2) having an odd number of pulses for every cycle of the triangular wave signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplier circuit, and furthermore, to a technique that is effective when applied to multiply the frequency by three times or by an odd number. The present invention relates to a technique that is effective for use in a circuit that generates a signal with a frequency three times the color signal subcarrier frequency in a video signal processing device such as a tape recorder (tape recorder).

[Prior Art] Frequency multiplier circuits have been used for a long time, for example, in the field of wireless communications. The multiplier circuit used in this field is
This method extracts the harmonic components enhanced by intentionally distorting the input signal using an LC-tuned filter, but it requires an LC-tuned filter and is not suitable for microcircuiting. As a result, multiplication efficiency is generally poor, and it is particularly difficult to extract harmonic components in odd-numbered sequences.Therefore, these systems are being replaced by systems using PLL (phase locked loops).

For example, in a video signal processing device, a multiplier circuit using a PLL operates at a frequency 3f, which is three times the color signal carrier frequency fsc.
It is used to obtain sc.

The multiplier circuit used here is composed of a PLL consisting of a VCO (voltage-controlled oscillator) that oscillates at a frequency of 3 fsc, a 173 frequency divider circuit, and a phase detector (for example, Chokoku Shoten Co., Ltd. June 30, 1986 Published on ``
(See "Integrated Circuit Application Handbook," pages 64-66).

[Problems to be Solved by the Invention] However, the present inventors have found that the above-mentioned technique has the following problems.

In other words, the PLL multiplier circuit, as described above,
Since it is constituted by a vCO1 frequency divider circuit and a phase detector, its configuration is complicated and has a large number of parts, and when implemented as a semiconductor integrated circuit, it occupies a large circuit area. There was a problem.

Further, multiplier circuits using PLLs have a problem in that the response of the frequency of the output signal to changes in the frequency of the input signal is not necessarily good due to the loop response delay of the PLL.

An object of the present invention is to have a structure that is relatively simple, has a small number of elements, and is suitable for semiconductor integrated circuits, and is capable of efficiently performing triple frequency multiplication or odd-number multiplication, and has good responsiveness to frequency changes. Our goal is to provide technology that can improve

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, convert the input signal into a triangular waveform signal.

This triangular waveform signal is level-discriminated at multiple level points, and multiple comparison outputs obtained for each level point are subjected to logical processing using product logic and sum logic. In this method, an output signal having an odd number of pulses is generated.

[Operation] According to the above means, by dividing the period of the triangular waveform signal into three or an odd number, a signal having a frequency three times or an odd number multiple of the frequency of the input signal can be efficiently generated without depending on the PLL. can do.

As a result, with a relatively simple configuration that has a small number of elements and is suitable for semiconductor integrated circuits, it is possible to efficiently triple the frequency or multiply the frequency by an odd number, and also improve responsiveness to frequency changes. be able to do so. That purpose is achieved.

[Embodiment] A preferred embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, the same reference numerals indicate the same or equivalent parts.

FIG. 1 shows a schematic configuration of a multiplier circuit according to a first embodiment of the present invention.

Further, FIG. 2 shows a waveform diagram of a main part of the multiplier circuit shown in FIG. 1.

The multiplier circuit 10 shown in the figure multiplies a signal with a frequency fsc input from an input terminal 1 to a signal with a frequency of 3 fsc and outputs the resultant signal to an output terminal 3. 6. Consists of logic circuit 7.

The triangular waveform signal generation circuit 5 converts the input signal of frequency fsc into a triangular waveform signal a.

The comparison circuit 6 includes the first . It is configured by two second differential level comparators CPI and CP2, and the triangular waveform signal a
First. Level discrimination is performed using the second two reference levels Vl and V2.

In this case, the first level comparator CPI receives the triangular waveform signal a at its inverting terminal (-), and
A first reference level v1 is applied to the non-inverting side terminal (+). This first reference level v1 is set at a level point that is 2/3 of the amplitude Vm of the triangular waveform signal a.

Further, the second level comparator CP2 receives the triangular waveform signal a at its non-inverting terminal (+), and receives the second reference level v2 at its inverting terminal (-). This second reference level v2 is the triangular waveform signal a.
The level point is set to 1/3 of the amplitude Vm.

The logic circuit 7 is constructed using an exclusive OR gate, and the comparison circuit 6 calculates each level point (Vl=2V m
/ 3 , V 2 = V m / 3 ), resulting in two comparison outputs (a<Vl) and (a>V2).

By applying logical processing using product logic and sum logic,
Output signal having an odd number of pulses per cycle of the above triangular waveform signal (a < V 1 ) (a) V
2)+(a<Vl) ・(a)V2)) is generated.

As described above, the input signal is converted into a triangular waveform signal a, the level of this triangular waveform signal a is discriminated at two level points, and the two comparison outputs obtained for each level point are summed with the product logic. By applying logic processing, an output signal having an odd number of pulses is generated for each period of the triangular waveform signal a.

By dividing the period of the triangular waveform signal a into three in this way, the frequency fs of the input signal can be adjusted without depending on the PLL.
It is possible to efficiently generate a signal with a frequency of 3Esc, which is three times c.

As a result, one frequency can be multiplied by 3 or an odd number efficiently with a relatively simple configuration that has a small number of elements and is suitable for semiconductor integrated circuits, and
Responsiveness to frequency changes can also be improved.

FIG. 3 shows a circuit diagram of a multiplier circuit according to a second embodiment of the invention.

Further, FIG. 4 shows a waveform diagram of the main part of the multiplier circuit shown in FIG. 3.

The multiplier circuit 10 shown in the figure is a triangular waveform signal generating circuit that triples a signal with a frequency fsc input from input terminals 1 and 2 to a signal with a frequency of 3 fsC and outputs it to output terminals 3 and 4. 5. Comparison circuit 6. Logic circuit 7. It is composed of a differential circuit 8, level shift circuits F1 & 9, and the like.

The triangular waveform signal generation circuit 5 includes a transistor Ql.

Q2, resistor R1 and capacitor C1, resistor R2 and capacitor C2, etc., and converts an input signal of frequency fsc into a triangular waveform signal using time constants of R1 and CI and R2 and 02.

The differential circuit 8 includes transistors Ql, Q2 and resistors R1,
R2, etc., from the triangular waveform signal output from the triangular waveform signal generation circuit 5, the first . Generate second triangular waveform signals a and b.

Level shift circuit 9 includes transistors Q3. Q4, diodes Di, D2, resistors R3, R4, R5, R6, etc., and the first. A third triangular waveform signal a, b whose level is shifted downward by 2/3 of its amplitude. Fourth triangular waveform signals c and d are generated.

The comparison circuit 6 and the logic circuit 7 include transistors Q5, Q6, .
Q7. Q8. Q9. QIO, resistors R7, R8, constant current circuit■. The first to fourth triangular waveform signals a, b, ct d are configured together by a multiplication type differential circuit such as
By comparing levels with each other and subjecting this comparison result to logical processing using product logic and sum logic, II
, I2, 13, and I4 are obtained in sequence. When 11 to 4 obtained here are expressed as a logical formula, it is as follows.

11=(a>b) I2=11・(b>c)=(a>b)・(b>c)
I3=(d)a) I4=I2+I3: (a>b) ・(b>c)+ (
d>a) Note that the inequality symbol (>) indicates the magnitude of the level.

Now, focusing on I4, I4 is a signal having an odd number of pulses for each period of the triangular waveform signal. Therefore, by taking out the voltage conversion signal of I4 from the output terminals 3 and 4, the frequency of the input signal
It is possible to obtain an output signal that is triple fsc to a frequency of 3fsc.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.

For example, although the multiplier circuit shown in FIG. 3 is constructed using bipolar transistors, it may also be constructed using MOS transistors. Further, the triangular waveform signal does not necessarily have to be an equilateral triangular waveform signal, and may be, for example, a sine wave or an approximately triangular waveform signal.

In the above description, the invention made by the present inventor was mainly applied to a triple multiplier circuit, which is the background field of application.

It can also be applied to odd number multiplier circuits.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, with a relatively simple configuration that has a small number of elements and is suitable for semiconductor integrated circuits, it is possible to efficiently triple the frequency or multiply the frequency by an odd number.
Responsiveness to frequency changes can also be improved.
This effect can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a multiplier circuit according to a first embodiment of the present invention, FIG. 2 is a waveform diagram of a main part of the multiplier circuit shown in FIG. 1, and FIG. 3 is a circuit diagram of a multiplier circuit according to a first embodiment of the present invention. FIG. 4 is a waveform diagram of the main part of the multiplier circuit shown in FIG. 3. 1.2...Input terminal, 3,4...Output terminal, 5
... Triangular waveform signal generation circuit, 6... Comparison circuit. 7...Logic circuit, 8...Differential circuit, 9...
level shift circuit. 1st r

Claims (1)

[Claims] 1. A triangular waveform signal generation circuit that converts an input signal into a triangular waveform signal, and a comparison circuit that discriminates the level of the triangular waveform signal output from the triangular waveform signal generation circuit at a plurality of level points. The multiple comparison outputs obtained for each level point by this comparator circuit are subjected to logical processing using product logic and sum logic to generate an output signal having an odd number of pulses for each period of the triangular waveform signal. A multiplier circuit equipped with a logic circuit that performs 2. A comparison circuit that discriminates the level of the triangular waveform signal output from the triangular waveform signal generation circuit at two level points of 2/3 and 1/3 of its amplitude, and two comparison outputs obtained from this comparison circuit. 2. The multiplier circuit according to claim 1, further comprising a logic circuit that takes the exclusive OR of . 3. A differential circuit that generates first and second triangular waveform signals with the same amplitude and opposite phase from the output signal of the triangular waveform signal generation circuit, and a differential circuit that generates first and second triangular waveform signals with the same amplitude and opposite phase, and 2/
A level shift circuit that generates the third and fourth triangular waveform signals whose levels are shifted by 3, a comparison circuit that compares the levels of the first to fourth four triangular waveform signals, and a signal obtained by this comparison circuit. Claim 1 or Claim 1, further comprising: a logic circuit that generates an output signal having an odd number of pulses for each period of the triangular waveform signal by subjecting the comparison result to logical processing using product logic and sum logic. Multiplier circuit described in Section 2.