JPH01263778A - Address control method for picture memory - Google Patents

Abstract

PURPOSE:To enhance memory utilizing efficiency by writing a second picture signal into an area where a video signal is not written when second picture information such as a character and a graphic having small information quantity is stored, correlating with first picture information, into the area other than the area where the picture information having the large information quantity is stored. CONSTITUTION:A character signal is a digital signal having the capacity of one bit per one picture element prepared in synchronization with the video signal inputted to a terminal 3. The video signal from the terminal 3 is supplied to a character signal generator 9 due to the synchronization. The data of the character pictures to be superimposed on the video signal are successively read. After respective prescribed serial/parallel conversions, a video signal (the first picture information) and a character signal (the second picture information) are stored into the prescribed parts of a digital memory 7 by an input multiplexer 6. When they are read, they are separated into the video signal and the character signal by an output multiplexer 8, and a prescribed parallel/ serial conversion is executed, and the characters are superimposed by an adder 15.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to an image memory for storing image information, and more particularly to an address control method for an image memory.

(Naka) Conventional Technology In recent years, research on high-definition television systems (HDTV systems) has been progressing, and efforts to unify standards for HDTV studio equipment are also being considered. In this draft standard, the number of scanning lines is 112.
5, the number of effective scanning lines is 1065, the field rate is 60 Hz, the interlace scanning method is used, the aspect ratio is 16:9.1, and the number of samples per scanning line is 1920.

In the case of this standard, the number of pixels is about five times that of the NTSC system, and the sample rate when storing image information in the memory increases proportionally. In the above example, R, G, B
The frequency is approximately 64 MHz for each color. Therefore, it is necessary that the image memory can be written to and read from at high speed.

Furthermore, in the image memory, it is desirable to arrange image information two-dimensionally for convenience in image processing (screen enlargement, reduction, etc.) (for example, Japanese Patent Application Laid-Open No. 61-233851, GO6F12102).

Next, we will specifically consider the image memory in the HDTV system.

FIG. 11 shows an example of the arrangement of image information cR, G, and B in the above-mentioned HDTV system. (1) is an area consisting of all sample points and all scanning lines, and the number of pixels is 112
It becomes 5x1920. At this time, sample 1/-t is
-Since both sides are transmitted at 3QHz, 1125X 1920X30 (from 60Hz with interlaced scan)
H2=64.8MHz.

However, the actually effective image information is 10 as shown in (2).
35xt60C1 area (because there is a blanking period). Therefore, in order to handle HDTV system information, 8-bit information must be written and read out at a rate of 64.8 MHz in a memory arranged at addresses 1035 vertically and 1600 horizontally. By the way, the digital memory (for example, SRAM) used for this image memory is
This is an array specified by a one-dimensional address of 2' (1 is a natural number). Therefore, in order to cover a two-dimensional array of 1035x1600, 11 bits (2
048) is necessary, but it becomes very inefficient (see FIG. 12).

(g) Problems to be Solved by the Invention The present invention aims to minimize invalid areas in an image memory that stores image information.

B) Means for Solving the Problems In the present invention, second image information such as characters and figures with a small amount of information is combined with the first image information in an area other than the area where image information with a large amount of information is stored. Make sure you remember it.

(g) Effect Therefore, the invalid area in the image memory can be reduced as much as possible.

(f) Example Hereinafter, the present invention will be described in detail with reference to the drawings.

First, a first embodiment will be described with reference to FIGS. 1 to 4.

Fig. 1 is a diagram showing address control, Fig. 2 is a block diagram showing the configuration of the image memory, Fig. 3 is a block diagram showing the main parts of the image memory, and Fig. 4 is an explanatory diagram showing the state of storage. .

In Figure 2, (3) is an input terminal for HDTV video signals, (4) is an A/D converter, (5) is a serial/parallel converter, (6) is an input multiplexer (MPX), and (71 is a digital Memory, (81 is an output multiplexer, (9) is a character signal generator to be superimposed on the video signal from terminal (3), α0 is an 8-bit serial/parallel converter, and αυ is a 32-bit serial/parallel converter. Parallel converter, ■ is an 8-bit parallel/serial converter, la is a 62-bit parallel/serial converter, (2
) is an 8-bit parallel/serial converter@based on the output, a 32-bit parallel/serial converter Q3) is an adding circuit that has the function of adding a predetermined value to the output, αQ is a D/A converter, and a is an output terminal. It is. The control circuit also controls the serial/parallel converter, multiplexer, digital memory, and parallel/serial converter.

The character signal is a digital signal created in synchronization with the video signal input to the terminal (3) and has a capacity of 1 bit per pixel. For synchronization, the character signal generator is supplied with a video signal from a terminal (3). Then, the data of the character screen to be superimposed on the video signal is sequentially read out.

Video signal (first image information) and character signal (second image information)
are respectively subjected to predetermined serial/parallel conversion and then stored in a predetermined portion of the digital memory (7) by the input multiplexer (6). When read out, the output multiplexer (8) separates the signal into a video signal and a character signal.
undergoes a predetermined parallel/serial conversion. Then, the addition circuit (15
1 executes character superimposition.

Digital memory (7) is divided into nine memory blocks. The input and output multiplexers (6) and (8) are provided for correct input/output to each memory block. One memory block is (8x8Kbit
) memories are connected in parallel.

The HDTV video signal input to the input terminal (3) is
It is sampled at 64.8 MHz, A/D converted, and becomes 8-bit data. This 8-bit data is converted into 32 parallel data by a serial/parallel converter (5) and written into a digital memory.

The serial/parallel conversion is performed because the 64.8 MHz data rate needs to be reduced to approximately 2 MH2.

As a result, the SRA used in digital memory (7)
Even if the access time of M is about 120 ns, write and read operations can be performed substantially simultaneously and delays in address control etc. can be absorbed.

A more detailed explanation will be given with reference to FIG. In the figure, 09) is the input terminal of the 64.8MHz clock signal,
■) is the horizontal (1() counter (11 bits from AO to A1.D) that counts this clock signal, (21 is the vertical (
V) Counter (All-, -A21's i lbi,, II
Corresponding to c) and 2) are two counter control circuits (1, 2, which control the operation of 2M2D, and Z) which output write addresses (A o to A21).

In the figure, . is an address generation circuit for a video number, 0 is an address generation circuit for a character signal, and 17 is an address generation circuit for a character signal.

There are 1600 pieces of image information to be stored in the horizontal direction, so
11 counter brew is 159? Count up to 1 no 1. ′, reset on next clock input. At this time, the count value of the V counter C21J increases by one. ■Counter (21
) requires 1035 scanning lines, so 1064
It is reset on the next input.

The reason for the video signal address generation circuit is to input the address signal (AO~A I? > - sound) from the counter control circuit and send AO~A4 to the 62-bit direct/parallel converter (5).
5 = - Allocate A17 to Ato1/S MPX Kani I (
(See Figure 1 (4)).

The 4-bit address signal of A18--A21 is input to input MPX (61) and address MPX (25
1.

Address generation circuit for character signals (24i is a counter control circuit with input 1. Performs a predetermined operation 5 on the address signal of AO%A17 from 22 and outputs it., 6 of AO to A2
The bits are assigned to an 8-bit direct/parallel converter (Iff, !), and the 5 bits A3 to 87 are assigned to a 62-bit direct/parallel converter (Iff, !).
11). Address MPX) has A8~
A10, 5 bits that are always "1", and An-An7 are supplied in this order as a memory address. (Figure 1 (+:
9),.

In other words, in the case of a character signal, the address indicating the horizontal direction is
- The digit bit is always "1". Therefore, the address of the character (1792~;o47 in the case of number 8) is specified to the corresponding memory.

At the input multiplexer (6), AI8 to A21
/ signal, selects two memory blocks,
The video signal (No. 4) is supplied to one side, and the character signal (11) is supplied to the other side.

The designation of the two memory blocks changes according to changes in the signals AI8 to A21. For example, 4 from AI8 to A21
Corresponding to the bit changing from “0” to “8”, (
Memory 1. Memory 2), (Memory 2, Memory ro), (Memory 6, Memory 4), (Memory 4. Memory 5), (Memory 5. Memory 6), (Memory 6, Memory 7), (Memory 7, Memory 8) ), (memory 8, memory 9), (memory?
, memory 1), (memory 1. memory 2)... (the video is stored in the first memory and the characters are stored in the second memory) 6 And the address MPX (25! is the same as A18~ A
21 is input, and an address signal (video signal address generation circuit (c) output or
The output of the character signal address generation circuit (4) is selected (7) and supplied. Also, this write at 1/s is supplied to the memory in synchronization with the timing to put the memory in the write state.

A character signal is originally a 1-bit signal, which is first
Since 8-bit serial/parallel conversion is performed, the horizontal direction is 1792
-2047 can be sufficiently stored. The vertical direction is the same as for the video signal.

The writing operation for one screen will be briefly explained in the fourth drawing. First, memory 1 (7-1) and memory 2 (7-2) are selected, and a video signal is written to memory 1 (7-1) and a character signal is written to memory 2 (7-2). It will be done. Both image signals are then sequentially written into the next memory. 1024 to 103 of the scanning line of the video signal
Data corresponding to the fourth line is written to the memory 9 (7-9). At this time, 1024 to 10 of the scanning line of the character signal
Data corresponding to the 64th line will be stored in memory 1 (7-1).

The means for creating the read address has been omitted, but it can be created in the same way as the write address. In this case, the address MP15) and the output MPX(8) are controlled by 4-bit signals B18 to B21. Then, the video signal is sent to the 32-bit parallel/direct converter ball.
A character signal is always supplied to the other 62-bit parallel/direct converter α button.

Writing and reading may be executed alternately in a time-sharing manner. At this time, the data is controlled to be read from the area that has already been written.

In this way, a character signal (a 1-bit signal corresponding to one pixel) can be stored in an area where a video signal is not stored. Moreover, since the video signal and character signal are written to different memory blocks, they can be processed simultaneously.

Next, a second embodiment will be explained with reference to FIGS. 5 to 10. Figure 5 is a block diagram showing the configuration, Figure 6 is a block diagram showing the main parts, Figure 7 is a schematic diagram showing the screen, Figure 8 is a diagram showing address control, and Figure 9 explains the memory configuration. FIG. 10 is a block diagram showing the main parts of the character signal address generation circuit.

In FIGS. 5 and 6, parts common to those in the first embodiment are designated by the same reference numerals. In this second embodiment, the digital memory is divided into two memories, and only the video signal is written to the first memory (7a), and the second
Memo! Both video one character signals are written to J(7b). So input M P X (6) is the second memo! j
(7b), and the output M P
1 is arranged only in the output stage of the first memory (7a).

The first memory (7a) has a large capacity and has a configuration of (8x64 bits)x32. The second memory (7b) has a small capacity and has a configuration of (8xsK bits)x62.

Due to memory capacity limitations, the area in which character signals can be superimposed is narrower than that shown in FIG. That is, character signals (1-bit digital signals) corresponding to 936 screens from the 48th scanning line to the 98686th scanning line are stored in the second memory (7b). This selection is
It's not an absolute thing, you can choose it arbitrarily.

In the video signal, the outputs of the H counter (2) and the V counter (21), which are controlled in the same manner as in the first embodiment, are directly used as address signals. (Figure 8 0)). However, the most significant bit A21 is input MPX + 6) and address MPX
@, the first memory (7a) and the second memory (7b
) is used for selection. That is, when Azr is "0", the first memory (7a) is selected, and when it is "1", the second memory (7b) is selected and the video signal is written.

Addresses for character signals are created as shown in FIG. 8(b). In other words, the lower 3 bits are the 8-bit serial/parallel converter σα
The data is supplied as is and used as is after being shifted by 3 bits. As a result, eight scanning lines of the character signal are written in the memory capacity corresponding to one scanning line of the video signal.

Furthermore, for the lower 3 bits of A14 to A20, (10
1) 2 (binary number) is added and A14 to A20
When is outside the range of 48 to 98, gate 2 (to) in FIG. 10 is closed, and AO to A20 are set to a high impedance state. Note that the character signal generator also generates and outputs character signals only within the range of 48 to 938 video signals.

Therefore, from within the character signal address generation circuit, when starting to output a character signal, A14 to A20 change to start with the value "11" and end with r127J. In other words, the first memo! When the video signal is being written to J (7a), the character signal must be written to the second memory (7b) at the same time.

Meanwhile, second memo! When a video signal is written to 7 (7b), no character signal is written (see FIG. 9).

Addresses for reading from memory can be created in a similar manner.

As described above, according to the second embodiment, character signals can be synchronously stored in the area of the second memory where no video signals are written.

Note that the video signal and character signal written in the memory as described above are subjected to various processes such as reading.

(G) Effects of the Invention As described above, according to the present invention, since the second image signal is written into the area where the video signal is not written, the memory usage efficiency is improved by 1 no. , the effect is great.

[Brief explanation of the drawing]

Figures 1 to 4 relate to the first embodiment, with Figure 1 showing address control, Figure 2 a block diagram showing the configuration of the image memory, and Figure 3 showing the main parts of the image memory. Block Diagram,
FIG. 4 is an explanatory diagram of the write operation. 5 to 10 relate to the second embodiment, FIG. 5 is a block diagram showing the configuration, FIG. 6 is a block diagram showing main parts, FIG. 7 is a schematic diagram showing the screen, and FIG. 8 is a block diagram showing the main part. 9 is a diagram showing address control, FIG. 9 is an explanatory diagram of the structure of the memory, and FIG. 10 is a block diagram showing the main part of the character signal address generation circuit. Figure 11 is a diagram showing one screen of HD TV system, Figure 12 is a diagram showing one screen of HD TV system.
The figure is an explanatory diagram for explaining the drawbacks of the conventional example. (7)...Image memory, α8rA...Control circuit. Figure 4 (A) (O) Figure 9. +599);T
Good fortune telling! Figure 10→Horizontal

Claims (1)

[Claims] (1) An image memory in which second image information with a small amount of information is written in association with the first image information in an area of the image memory other than the area where the first image information with a large amount of information is written. Address control method.