JPH01279630A - Bus driver circuit - Google Patents

Abstract

PURPOSE:To prevent the through current of an inter-bus driver circuits at the time of switching, to reduce consumption currents and to prolong service life of wiring by changing the level of a control signal in synchronism with a clock signal and holding an output terminal to a high level until the clock signal comes to a prescribed level even if a system comes to an operation state by means of the control signal. CONSTITUTION:The control signal CN controls the operation and non-operation of a bus driver circuit, sets the system to the operation state in the low level 'L', and sets MOSFET Q1 and Q2 to off states and the system to the non- operation state in the high level 'H'. The control signal CN synchronizes with the clock signal CK and changes with the rise of the clock signal CK. The clock signal CK compulsorily turns on MOSFET Q2 in the level 'H', and sets an output signal V0 to 'H'. Even if the bus driver circuits 10 are respectively connected to the output terminals of plural function blocks 20A-20C, and the output terminal of the bus driver circuits 10 is commonly connected to connect it with a subsequent level, MOSFET Q1 and Q2 are prevented from simultaneously being tuned on at the time of switching the bus driver circuits 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus driver circuit, and particularly to a bus driver circuit used when data is transferred between a plurality of functional blocks.

[Conventional technology]

Conventionally, as shown in FIG.
○′ [゛Circuit 4 and this NO]゛Circuit 1-circuit 5 that performs N, AND operation between the output signal of circuit 4 and input signal DT, and NOR between input signal DT and control signal CN, A gate circuit 6 for calculation, a source connected to a ground potential terminal, and a drain connected to an output terminal T. Connect to gate circuit 6
N-type MO8FE that turns on and off by inputting the output signal of
TQ, and the source are connected to the power supply terminal (voltage Vcc) 1
~Rain output terminal T.

The configuration includes a P-type MOS FET Q 2 connected to the gate and inputting the output signal of the gate circuit 5 to the gate to turn on and off.

In this bus driver circuit, when the control signal CN is at a high level (hereinafter referred to as "H"), the NOT circuit 1 is at a low level (hereinafter simply referred to as 'L'), and the gate circuit 5 is at a 'H' level.
", the gate circuit 6 becomes 'L' logic level, and M
OS F ET Q 1 and MO3F F, T
Both Q2 are in the OFF state.

Also, when the control signal CN is "'L'", NO'
The r circuit 1 becomes the logic level "H", and the gate circuit 5.
The output of 6 has a logic level that is an inversion of the input signal D'F.

That is, when the input signal DT is ``high'', the output of the gate circuit 5.6 is ``L'' and MO8FET Q2 is turned on, and the output signal V, . . . becomes ``H''.

Similarly, when the input signal DT is 'L', MO3FE
TQI turns on and output signal vo' becomes 'L'.

becomes.

As a bus circuit, as shown in FIG. 6, the outputs of each functional block 2OA~20c are
Multiple functional blocks 20 using Raiha circuit (10A)
Connect the outputs of A to 20C to form a hash circuit.

Switching of bus sources is controlled by control signals CNA to CN so as to turn off unused bus driver circuits 10A connected to each functional block 20A to 20c.

FIG. 7 shows a time chart when the bus driver circuit 10A of the functional blocks 20A to 20c is switched.

In FIG. 7, when the control signals CNA to CNC are "L", the bus driver circuit of the corresponding functional block operates, and the output signal (
DTA to DTo) are transmitted to the next stage as an output signal DTo'.

[Problem to be solved by the invention]

[Conventional hash driver circuit described above] OA is connected to the outputs of a plurality of functional blocks (20A to 20c) and outputs these output signals (DTA to DTC) to control signals CNA to CNc.
When switching and transmitting to the subsequent stage, the control signal (CNA
~CNc) There is a period in which the MO3FETs Q, , Q2 of the bus driver circuit 10A, which are switched due to overlap, are turned on at the same time, and these bus driver circuits 10A
This has the disadvantage that an excessive current (through current) flows between the wires, increasing current consumption and shortening the life of the wiring.

An object of the present invention is to provide a bus driver circuit that can reduce current consumption and extend wiring life by preventing through current between bus driver circuits during switching.

[Means to solve the problem]

The bus driver circuit of the present invention has N input signals.

a NOT circuit that performs a T operation, a first gate circuit that performs a NOR operation between a control signal whose level changes in synchronization with a clock signal, and the output signal of the NOT circuit; NOR operation with clock signal (
or an OR operation), and a third gate circuit that performs a NOR operation on the input signal, the control signal, and the clock signal.
a gate circuit, one of the source and drain is connected to the first power supply terminal, the other is connected to the output terminal, and the third gate circuit is connected to the gate.
A first MOSFET of one conductivity type is turned on and off by inputting an output signal of a gate circuit, and one of its source and drain is connected to a second power supply terminal, the other is connected to the output terminal, and the gate is connected to the second MOSFET. A second MOS of opposite conductivity type (or one conductivity type) that is turned on and off by inputting the output signal of the gate circuit of
FET.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, a NOT operation is performed on the input signal DT.
a circuit 1; a first gate circuit 2 that performs a NOR operation between a control signal CN whose level changes in synchronization with a clock signal CK and an output signal of the NOT circuit 1; and this first gate circuit 2.
a second gate circuit 3 that performs a NOR operation on the output signal of the clock 6 and the clock signal CK, the input signal DT, the control signal CN, and the clock signal CK;
A third gate circuit 4 performs a NOR operation, and a source is connected to a first power supply terminal (ground potential terminal), and a train is connected to an output terminal T. The first N-type MOS F is connected to the gate and is turned on and off by inputting the output signal of the third gate circuit 4 to its gate.
E T Q 1 and the source is connected to the second power supply terminal (voltage Vc
c), the drain is connected to the output terminal To, and the second P-type MOS FETQ 2 is turned on and off by inputting the output signal of the second gate circuit 3 to the gate. ing.

Control signal CN is the operation of this bus driver circuit.

Control non-operation, low level (hereinafter simply °゛LL puzzle)
When , it is considered to be an active layer, and the high level (hereinafter simply °' H”
) when MOS FET Q 1. Q
2 are both turned off (high resistance) and rendered inactive.

Further, this control signal CN is synchronized with the clock signal CK and changes at the rising edge of the clock signal CK.

When the clock signal CK is "H", MO3FETQ2 is forcibly turned on, and the output signal V is output. is "H".

Therefore, when transitioning from a non-operating state to an operating state, when the clock signal CK rises, the output signal becomes 0 or "H", the control signal CN becomes "L", and the clock signal CK becomes "L°'". Since the input signal DT is transmitted after the
Even in the case where the bus driver circuits 10 are connected to the output terminals of MO3FETQ1. Since Q2 is not turned on at the same time, no through current (excessive current) flows between these bus driver circuits 10.

FIG. 3 is a waveform diagram of each part signal of FIG. 2 for explaining the above effect.

Even if the control signals CNA to CNc become L'' and the bus driver circuit]0 is in the operating state, the clock signal CK becomes 'H.
”, the output terminal (To) of each bus driver circuit 10 is “°H”, and when the clock signal CK becomes “L, ”, the output terminal (To) of each bus driver circuit 10 is “°H”, and then the output terminal (To) of each bus driver circuit 10 is “°H”. Driver circuit] 0 to output signal (VOA to Vo
c) is output.

Therefore, these output signals (VoA to Voc) are not output simultaneously, and no through current occurs between the bus driver circuits 10.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, the second gate circuit 3A is a gate circuit that performs an OR operation between the output signal of the first gate circuit 2 and the clock signal CK, and correspondingly, the second gate circuit 3A is
E T Q 3 is N type, MO8FETQ
There is an advantage that both + and Q3 can be constructed of N type.

〔Effect of the invention〕

As explained above, the present invention changes the level of the control signal in synchronization with the clock signal, and even when the control signal enters the operating state, the output terminal remains at a high level (“H”) until the clock signal reaches a predetermined level. ), even in the case where the bus driver circuit of the present invention is connected to the output ends of a plurality of functional blocks, and the output signals of these functional blocks are selected, switched, and transmitted to the subsequent stage.
Penetration current (excessive current) between these bus driver circuits can be eliminated, which has the effect of reducing current consumption and extending the life of the wiring.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIGS. 2 and 3 are block diagrams of an applied circuit and signals of each part of this applied circuit to explain the effects of the first embodiment, respectively. FIG. 4 is a circuit diagram showing a second embodiment of the present invention,
FIG. 5 is a circuit diagram showing an example of a conventional bus driver circuit.
6 and 7 are a block diagram of an applied circuit and a waveform diagram of signals of various parts, respectively, for explaining the problems of the bus driver circuit shown in FIG. 5. 1.NOT circuit, 2.3.3A, 4-6.-gate circuit, 10. ], OA・Bus driver circuit, 20A~20
c...Functional block, Q+~Q3...MOSFET. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] a NOT circuit that performs a NOT operation on an input signal; a first gate circuit that performs a NOR operation on a control signal whose level changes in synchronization with a clock signal and an output signal of the NOT circuit;
a second gate circuit that performs a NOR operation (or OR operation) between the output signal of the first gate circuit and the clock signal; and a NOR operation of the input signal, the control signal, and the clock signal.
A third gate circuit that performs calculations, one of the source and drain is connected to the first power supply terminal and the other is connected to the output terminal, and the output signal of the third gate circuit is input to the gate to turn it on and off. A first MOSFET of one conductivity type and a source
A reverse conductivity type (or one conductivity type) in which one of the drains is connected to the second power supply terminal, the other is connected to the output terminal, and the output signal of the second gate circuit is input to the gate to turn on and off.
A bus driver circuit comprising a second MOSFET.