JPH01295462A - Manufacture of mos type semiconductor device - Google Patents
Manufacture of mos type semiconductor deviceInfo
- Publication number
- JPH01295462A JPH01295462A JP63126311A JP12631188A JPH01295462A JP H01295462 A JPH01295462 A JP H01295462A JP 63126311 A JP63126311 A JP 63126311A JP 12631188 A JP12631188 A JP 12631188A JP H01295462 A JPH01295462 A JP H01295462A
- Authority
- JP
- Japan
- Prior art keywords
- film
- groove
- gate oxide
- semiconductor device
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野１ 本発明はＭＯＳ型半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field 1 The present invention relates to a method of manufacturing a MOS type semiconductor device.
［従来の技術１
従来、シリコン基板にドライエツチングにより溝を形成
し、該溝の側面に熱酸化によるゲート酸化膜を形成し、
該ゲート酸化膜表面に多結晶シリコンを前記溝を埋める
が如くに形成するいわゆるトレンチ・ゲートのＭＯＳ型
半導体装置があった。[Prior art 1] Conventionally, a groove is formed in a silicon substrate by dry etching, and a gate oxide film is formed on the side surface of the groove by thermal oxidation.
There has been a so-called trench gate MOS type semiconductor device in which polycrystalline silicon is formed on the surface of the gate oxide film so as to fill the trench.
〔発明が解決しようとする課題］
しかし、上記従来技術によると、溝型ゲートすなわちト
レンチ・ゲートの溝の深さ方向への電気抵抗が大きく、
電気、信号のゲートへの伝帳に遅延を生ずると云う課題
があった。[Problems to be Solved by the Invention] However, according to the above-mentioned conventional technology, the electrical resistance in the depth direction of the trench gate, that is, the trench gate, is large;
There was a problem with delays in transmitting electricity and signals to the gate.
本発明は、かかる従来技術の課題を解決し、トレンチ・
ゲート構造のＭＯＳ型半導体装置の低抵抗ゲート構造の
新しい製造方法を提供する事を目的とする。The present invention solves the problems of the prior art and
It is an object of the present invention to provide a new method for manufacturing a low resistance gate structure of a MOS type semiconductor device having a gate structure.
［課題を解決するための手段１
上記課題を解決するために、本発明はＭＯＳ型半導体装
置の製造方法に関し、シリコン基板にドライエツチング
により溝を形成し、該溝に熱酸化によるゲート酸化膜を
形成し、該ゲート酸化膜表面に、多結晶シリコン膜とＴ
ｉ、ＷあるいはＴｉＳｉ、ＷＳｉあるいはＴｉＮの如き
高融点金属膜やそのシリサイド膜あるいは窒化膜を前記
溝内を埋めるが如くに形成する手段をとる。[Means for Solving the Problems 1] In order to solve the above problems, the present invention relates to a method for manufacturing a MOS type semiconductor device, which includes forming a groove in a silicon substrate by dry etching, and forming a gate oxide film in the groove by thermal oxidation. A polycrystalline silicon film and a T film are formed on the surface of the gate oxide film.
A method is taken to form a high melting point metal film such as i, W, TiSi, WSi, or TiN, or its silicide film or nitride film so as to fill the inside of the trench.
［実 施 例］ 以下、実施例により本発明を詳述する。[Example] Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は、本発明の一実施例を示すトレンチ・ゲートの
断面図である。すなわち、Ｓｉ基板１の表面から通常の
ホトリゾグラフィーとドライエツチングにより溝を形成
し、該溝の壁面に熱酸化によるゲート酸化ＩＩＩ ２が
形成され、該ゲート酸化膜２の表面にはＣＶＤ法により
多結晶Ｓｉ膜３が形成され、次で該多結晶Ｓｉ膜表面に
、やはり、ＣＶＤ法によりＷＳｉ、ＴｉＳｉ等のシリサ
イド膜４が溝の深さ方向に侵入するが如く、又、溝内を
埋めるが如くに形成されて成る。フィールドＳｉ０ｇ膜
６や拡散層５は、通常の熱酸化法やイオン打込み法等に
より形成され、ＭＯＳ型トランジスタを構成して成る。FIG. 1 is a cross-sectional view of a trench gate showing one embodiment of the present invention. That is, a groove is formed from the surface of the Si substrate 1 by ordinary photolithography and dry etching, gate oxide III 2 is formed on the wall surface of the groove by thermal oxidation, and the surface of the gate oxide film 2 is etched by CVD. A polycrystalline Si film 3 is formed, and then a silicide film 4 of WSi, TiSi, etc. is formed on the surface of the polycrystalline Si film by the CVD method so that it penetrates in the depth direction of the trench and fills the inside of the trench. It is formed like this. The field Si0g film 6 and the diffusion layer 5 are formed by a normal thermal oxidation method, ion implantation method, etc., and constitute a MOS type transistor.
尚、シリサイド膜４は、多結晶５ｉｌｌ上にＣＶＤ法に
よりＷやＴｉ膜を形成した後、加熱処理によりシリサイ
ド化しても良く、ＷやＴｉ膜として残しても良く、又、
シリサイド膜のみならずＴｉＮ膜等の窒化膜であっても
良い６
〔発明の効果〕
本発明の如く、溝型ゲート構造のＭＯＳ型半導体装置の
溝の内部に迄低抵抗の高融点金属膜やそのシリサイド膜
あるいは窒化膜を形成する事により溝型ゲート電極への
信号の伝帳速度を速くすることができる効果がある。Incidentally, the silicide film 4 may be formed by forming a W or Ti film on the polycrystalline 5ill by CVD method and then silicided by heat treatment, or may be left as a W or Ti film, or
Not only a silicide film but also a nitride film such as a TiN film may be used.6 [Effects of the Invention] As in the present invention, a high melting point metal film with low resistance can be formed inside the trench of a MOS semiconductor device with a trench gate structure. Forming the silicide film or nitride film has the effect of increasing the transmission speed of signals to the trench gate electrode.
第１図は本発明の一実施例を示す溝型（トレンチ）ゲー
ト構造のＭＯＳ型トランジスタの要部の断面図である。
■・・・Ｓｉ基板
２・・・ゲート酸化膜
３・・・多結晶Ｓｉ膜
４・ ・ ・シリサイド膜
５・・・拡散層
６・・・フィールド５ｉＯｚ膜
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 上 柳 雅 誉（他１名）１．５１基
籾
第１図FIG. 1 is a sectional view of a main part of a MOS transistor having a trench gate structure, showing an embodiment of the present invention. ■...Si substrate 2...Gate oxide film 3...Polycrystalline Si film 4...Silicide film 5...Diffusion layer 6...Field 5iOz film or above Applicant Seiko Epson Corporation Agent Patent attorney Masatoshi Kamiyanagi (and 1 other person) 1.51 base paddy figure 1
Claims (1)
該溝の側面に熱酸化によるゲート酸化膜を形成し、該ゲ
ート酸化膜表面に多結晶シリコン膜とＴｉ、Ｗあるいは
ＴｉＳｉ、ＷＳｉあるいはＴｉＮの如き高融点金属膜や
そのシリサイド膜あるいは窒化膜を前記溝内を埋めるが
如くに形成する事を特徴とするＭＯＳ型半導体装置の製
造方法。Grooves are formed on the silicon substrate by dry etching,
A gate oxide film is formed on the side surface of the trench by thermal oxidation, and a polycrystalline silicon film and a high melting point metal film such as Ti, W, TiSi, WSi, or TiN, or a silicide film or nitride film thereof are formed on the surface of the gate oxide film. A method for manufacturing a MOS type semiconductor device characterized by forming the device so as to fill a trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63126311A JPH01295462A (en) | 1988-05-24 | 1988-05-24 | Manufacture of mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63126311A JPH01295462A (en) | 1988-05-24 | 1988-05-24 | Manufacture of mos type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01295462A true JPH01295462A (en) | 1989-11-29 |
Family
ID=14932044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63126311A Pending JPH01295462A (en) | 1988-05-24 | 1988-05-24 | Manufacture of mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01295462A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5583065A (en) * | 1994-11-23 | 1996-12-10 | Sony Corporation | Method of making a MOS semiconductor device |
| WO1999007019A1 (en) * | 1997-08-01 | 1999-02-11 | Siemens Aktiengesellschaft | Three-pole high-voltage switch |
| US6538280B2 (en) | 1997-07-11 | 2003-03-25 | Mitsubishi Denki Kabushiki Kaisha | Trenched semiconductor device and method of fabricating the same |
-
1988
- 1988-05-24 JP JP63126311A patent/JPH01295462A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5583065A (en) * | 1994-11-23 | 1996-12-10 | Sony Corporation | Method of making a MOS semiconductor device |
| US6538280B2 (en) | 1997-07-11 | 2003-03-25 | Mitsubishi Denki Kabushiki Kaisha | Trenched semiconductor device and method of fabricating the same |
| WO1999007019A1 (en) * | 1997-08-01 | 1999-02-11 | Siemens Aktiengesellschaft | Three-pole high-voltage switch |
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