JPH01308069A - Memory cell structure of semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In particular, regarding the memory cell structure of a semiconductor memory such as a DRAM having a memory capacitor, the present invention relates to a semiconductor memory having a structure in which a capacitor can be freely formed without competing with a bit line. The purpose of providing a memory cell structure is to include a substrate in which a plurality of field regions in which access transistors are built are arranged in a row direction, an insulator covering the upper surface of the substrate, and an insulator formed along the field region, at least A groove in the row direction that does not reach the substrate surface, a first recess that reaches the source region of the access transistor and is formed in the insulator and is continuous with the trench, and is formed on the inner surface of the first recess and the wall surface of the trench. a focus line continuous in the row direction; a second recess formed in the insulator reaching the drain region of the access transistor; and a focus line continuous in the upper surface of the insulator and in the second recess; and a memory capacitor, one electrode of which is connected to the drain region of the access transistor.

[Industrial application field]

The present invention relates to a memory cell structure of a semiconductor memory, and more particularly to a memory cell structure of a semiconductor memory such as a DRAM that serves as a memory capacitor.

In recent years, as a result of various technological developments such as microfabrication technology, development and improvement of circuit technology and cell structure, the degree of integration of semiconductor memories, particularly DRAMs, has significantly improved. In general, an increase in the degree of integration leads to a reduction in the cell area, leading to a decrease in storage capacity and vulnerability to soft errors. There was a limit to increasing capacity.

Therefore, various cell structures that can obtain a relatively large cell capacity with a small cell area have been put into practical use, contributing to the realization of large-capacity semiconductor memories.

[Prior Art] As a conventional cell structure of this type, a trench capacitor type cell structure as shown in FIG. 9 is known. In FIG. 9, ■ is a substrate, 2 is a drain region, 3 is a source region, 4 is a word line functioning as a gate electrode, and 5 is a first
, an insulating film, 6 a separation layer, 7 a bit contact pad,
8 is a capacitor compact bat, 9 is a dielectric film, 10
11 is a second insulating film, and 12 is a bit line.

In the trench capacitor type cell structure, a trench is dug inside the substrate 1, and a capacitor consisting of a capacitor contact pad 8, a dielectric film 9, and a cell plate 10 is formed in the trench. Although the capacitance can be increased, the area of the depletion layer also increases as the cell capacitance increases, resulting in an increase in the amount of absorbed charge, making soft errors more likely to occur.

On the other hand, as another cell structure, a stacked capacitor type cell structure as shown in FIG. 1O is also known. In FIG. 10, 21 is a substrate, 22 is a drain region, 23 is a source region, 24 is a word line functioning as a D1-electrode, 25 is a first insulating film, 26 is a separation layer, 27 is a bit contact pad, 28 is a capacitor contact pad,
29 is a dielectric film, 30 is a cell plate, 31 is a second insulating film, and 32 is a bit line. In the stacked capacitor type cell structure, a capacitor consisting of a capacitor contact pad 28, a dielectric film 29, and a cell plate 30 is formed above the access transistor and wiring region of the cell itself, and the drain region 22 and the capacitor contact pad 28 Since the contact area is small, the diffusion layer area is small and has excellent soft error resistance. However, sufficient cell capacity cannot be obtained because the capacitor area is limited.

[Problems to be Solved by the Invention] Although the conventional stacked capacitor type cell structure has a small diffusion layer area and has excellent soft error resistance, it has a structure in which the bit line 32 is located above the capacitor. Therefore, when designing the shape of the capacitor, a complicated shape must be designed within the extremely narrow space between the substrate 21 and the bit line 32, resulting in a problem in that manufacturing reliability is reduced. In addition, in recent DRAMs, there is a tendency to reduce the cell area by 2 stages, but there are limits to capacitor shape design to obtain sufficient cell capacity in a narrow space, and the recent trend difficult to respond to. Although sufficient cell capacitance can be obtained by enlarging the space between the substrate 21 and the bit line 32, this is not preferable because the bit line 32 becomes longer and line resistance and stray capacitance increase.

The present invention was made in view of these problems, and
It is an object of the present invention to provide a memory cell structure of a semiconductor memory in which a capacitor can be freely formed without competing with a bit line.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a substrate in which a plurality of field regions in which access transistors are built are arranged in a row direction, an insulator covering the upper surface of the substrate, and an insulator formed along the field region. A groove in the row direction that does not reach the substrate surface, a first recess that reaches the source region of the access transistor and is formed in the insulator and is continuous with the trench, and is formed on the inner surface of the first recess and the wall surface of the trench. a bit line continuous in the row direction; a second recess formed in the insulator reaching the drain region of the access transistor; and a memory capacitor whose electrode is connected to the drain region of the access transistor.

(Function) In the present invention, the focus line is formed substantially perpendicular to the substrate except for the source region of the access transistor.

Further, the capacitor is connected to the drain region of the access transistor via a second recess that does not conflict with the bit line.

Therefore, the shape of the capacitor can be freely determined without being restricted by the bit line, and the cell capacity can be increased, and the degree of freedom in design and reliability in manufacturing can be improved.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 8 are diagrams showing one embodiment of a memory cell structure of a semiconductor memory according to the present invention.

First, the pattern layout of this embodiment will be explained with reference to FIGS. 1 to 3. In FIG. 1, 40 is a substrate, and a plurality of field regions 41 shown by cross hatching are formed on the substrate 40. As shown in FIG. The field region 41 has a source region S in the center, and a channel region CH and a drain region CH are arranged on both sides of the source region S, and an access transistor TR is formed by these CH1S and D.

Further, the upper surface of the substrate 40 is covered with an insulator (not shown), and the insulator includes grooves 4 in the row direction (horizontal direction in the figure).
A first recess 43 is formed at the source region S of the access transistor TR. Note that the groove portion 42
The depth of the first recess 43 is such that it does not reach the substrate 40, and the depth of the first recess 43 reaches the substrate 40. In this way, the insulator on the upper surface of the substrate 40 has irregularities that are repeated regularly, and an island-like portion is formed in the area other than S in the row direction where the field regions 41 are lined up, and between the field regions 41 (
(row direction) to form a trough (groove 42), and further,
A hole (first recess 43) reaching the substrate 40 is made at S of the access transistor TR. Note that 44 is a word line, and the word lines 44 are arranged over the entire surface of the substrate 40 at approximately equal intervals.

The bit line layout is explained according to FIG.

In FIG. 2, 45 is a bit line (indicated by hunting in the figure), and the bit line 45 is formed on the inner surface of the first recess 43 and the wall surface of the groove 42, and is continuous in the row direction. That is, bit line 45 is not formed at least above CH and D of access transistor TR. Note that 46 is a second recess formed in the insulator so as to reach D of the access transistor TR.

The layout of the memory capacitor is explained according to FIG. In FIG. 3, 47 is a memory capacitor (indicated by hatching in the figure), two memory capacitors 47 are provided in one field region 41, and each memory capacitor 47 is connected to an access transistor via a second recess 46. Connected to TR D.

Next, the manufacturing process of this embodiment will be briefly explained with reference to FIGS. 4 to 8. In addition, in Figures 4 to 8, (a)
The figure shown in Figure 3 is the ! -1′ arrow cross section is shown,
Moreover, the figure shown by (b) shows the nn' arrow cross section in FIG.

11 Summer Work ■ 14 In Figures (a) and (b), a word line 44, a capacitor contact pad 50,
A focus contact pad 51 is formed, and a first glabellar insulating layer 52 is formed to a predetermined thickness so as to cover these.

11 summer process In FIGS. 5(a) and 5(b), the first glabella insulating layer 52
A resist mask (not shown) is formed on top of the bit contact bat 51 and between TR and TR0 (see FIG. 5).
(see b)), holes 53 and 54 with a depth h are formed by RIE or the like. Here, the hole 53 corresponds to the bit contact pad 51.
The holes 54 are formed only in the upper part, and are continuous in the row direction of the substrate 40, and also continuous with the holes 53. That is, the hole 54 is formed as the groove 42. Note that the hole 53 is continuously dug down until it reaches the bit contact pad 51 as shown by the dotted line in the figure, and the first recess 43 is formed.

In 1Q Engineering 5, Figures 6(a) and 6(b), AI
! , Po1y-5i, etc. are formed, and then the entire surface is etched using REE, etc., to leave a 2-2 etc. on the side wall of the recess 43. Further, a pattern is formed by forming a resist mask where necessary. As a result, A1 and the like remain on the inner surface of the first recess 43 and the wall surface of the groove 42, and the bit line 45 is formed. The bit line 45 in the first recess 43 is in contact with the bit contact pad 51 . Note that 55 is a second glabellar insulating layer.

In the second Saturday and summer process in FIGS. 7(a) and 7(b), the second insulating layer 52 and the second insulating layer 5 on the capacitor contact pad 50 are
A second recess 46 is formed in the second recess 46, and a capacitor electrode 56 reaching the substrate 50 through the second recess 46 is formed, and a dielectric film 57 and a cell plate 58 are laminated. That is, the memory capacitor 47 is formed by the capacitor electrode 56, the dielectric film 57, and the cell plate 58.

Ith Summer Work■ Finally, as shown in FIGS. 8(a) and 8(b), a third glabella insulating layer 59 is formed, and a third interlayer insulating layer 59 is formed.
A 1M wiring 60 is formed thereon as necessary to complete the process.

In such a configuration, data writing and reading operations are performed as follows. That is, as a result of selecting a predetermined word line and bit line, for example, as shown in FIG.
a) The potential of the word line 44 in ■8. When data is applied to the bit line 45 from a sense amplifier (not shown), this data is applied to the word line 44 at vl,
It is applied to the capacitor electrode 56 through CH of the access transistor TR which is made conductive by D, and is stored in the cell capacitance between the capacitor electrode 56 and the cell plate 58, thereby writing data.

On the other hand, to read data, first raise the potential of the word line 44 to
conduction. As a result, the cell capacitance potential between the capacitor electrode 56 and the cell plate 58 is applied to the bit line 45, and is applied to a sense amplifier (not shown) to read data.

As described above, in this embodiment, after forming the bit line 45, the first interlayer insulation JW 52 and the second glabellar insulation layer 5 are formed.
A second recess 46 is formed in the second recess 46 and a memory capacitor 47 is formed inside the second recess 46 and on the upper surface of the second glabella insulating layer 55. Therefore, the cell capacity can be adjusted by adjusting the depth of the second recess 46, and the cell area on the upper surface of the second glabellar insulating layer 55 can also be increased, making it easy to obtain the desired cell capacity. be able to. Further, even if the cell capacitance is increased, the contact area between the capacitor electrode 56 and the S of the access transistor TR does not change, and the diffusion capacitance does not increase.

In other words, it is excellent against soft errors. moreover,
The layout of the bit line 45 can be set to the shortest distance regardless of cell capacitance, and increases in wiring resistance and stray capacitance can be suppressed.

〔Effect of the invention〕

According to the present invention, a capacitor can be formed without competing with a bit line. Therefore, sufficient cell capacity can be obtained by optimizing the capacitor shape. Furthermore, since the capacitor is formed after the bit line is formed, the manufacturing process can be simplified.

[Brief explanation of the drawing]

1 to 8 are diagrams showing one embodiment of the memory cell structure of a semiconductor memory according to the present invention, FIGS. 1 to 3 are diagrams each showing its pattern layout, and FIGS. 4 to 8 are diagrams showing its manufacturing process. Figures shown respectively, Section 9.1
0 is a diagram showing a conventional example, FIG. 9 is a diagram showing its trench capacitor type cell structure, and FIG. 10 is a diagram showing its stacked capacitor type cell structure. 40... Substrate, 41... Field region, 42... Groove, 43... First recess, 45... Bit line, 46... Second recess, 47... Memory capacitor, 52... First interlayer insulating layer, 55... Second interlayer insulating layer, TR...Access transistor, S...
- Source region, D...Drain fJ Li. Patent Applicant: Fujitsu Limited

Claims (1)

[Scope of Claims] A substrate in which a plurality of field regions in which access transistors are built are arranged in a row direction, an insulator covering the upper surface of the substrate, and an insulator formed along the field region so that it does not reach at least the substrate surface. a groove in the row direction, a first recess that reaches the source region of the access transistor and is formed in the insulator and is continuous with the groove; a continuous bit line; a second recess formed in the insulator reaching the drain region of the access transistor;
A memory cell structure for a semiconductor memory, comprising: a memory capacitor having one electrode connected to a drain region of an access transistor.