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JPH0199031A - Driving method of electro-optical device - Google Patents

Driving method of electro-optical device

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Publication number
JPH0199031A
JPH0199031A JP25691287A JP25691287A JPH0199031A JP H0199031 A JPH0199031 A JP H0199031A JP 25691287 A JP25691287 A JP 25691287A JP 25691287 A JP25691287 A JP 25691287A JP H0199031 A JPH0199031 A JP H0199031A
Authority
JP
Japan
Prior art keywords
voltage
hysteresis
electro
erasing
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25691287A
Other languages
Japanese (ja)
Other versions
JP2727546B2 (en
Inventor
Sunao Ota
直 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62256912A priority Critical patent/JP2727546B2/en
Publication of JPH0199031A publication Critical patent/JPH0199031A/en
Application granted granted Critical
Publication of JP2727546B2 publication Critical patent/JP2727546B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Liquid Crystal Display Device Control (AREA)

Abstract

PURPOSE:To erase the display in a short time even in case of a liquid crystal panel for showing an abnormal hysteresis by executing the erasion by applying both of a pulse voltage and '0' or about '0' volt, in an electro-optical device having a hysteresis characteristic. CONSTITUTION:In a device which has utilized a fact that an applied voltage and transmittivity cause a hysteresis phenomenon in a high twist state exceeding 90 deg., in an area where an abnormal hysteresis is shown especially when sweeping speed becomes high, a period te in which a holding voltage Vk is dropped to '0' from an ON state and erased becomes very long. Therefore, a high pulse for erasing the voltage being higher than the holding voltage is applied to the head of an erasion period for a time ts (5-0.2msec), and subsequently, an erasing waveform for applying zero volt is used. According to this erasing waveform, the erasing time te is shortened surely.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、表示装置、透過光量制御装置等として用いる
ことのできる電気光学装置の駆動方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for driving an electro-optical device that can be used as a display device, a transmitted light amount control device, etc.

[従来の技術J 従来、電気光学装置として種々のものが開発されている
。これらの中でも、液晶を用いた電気光学装置は比較的
構成が簡単で、小型、軽量、低消費電力等の特徴により
、表示装置、光シヤツター等の用途に広く用いられてい
る。
[Prior Art J] Conventionally, various electro-optical devices have been developed. Among these, electro-optical devices using liquid crystals have a relatively simple structure and are widely used in applications such as display devices and optical shutters due to their features such as small size, light weight, and low power consumption.

液晶電気光学装置の製造上、大容量化/大面積化時には
単純7トリクスを用いたものがアクティブマトリクスを
用いたものより有利であるが、従来の単純マトリクスを
用いた液晶電気光学装置においては、電気光学特性の制
限から大容量のものを作製することが困難である。例え
ば、ツイストネマチックモードを用いたものでは1/2
00デユ一テイ程度、J:リツイスj・角を大きくして
高性能にしたS TN/S B Eモードでも1/40
0デユ一テイ程度とすると、表示品位あるいは応答速度
が悪化して実用上使用に酎えないという問題点があった
In manufacturing a liquid crystal electro-optical device, when increasing capacity/area, using a simple 7 matrix is more advantageous than using an active matrix, but in a conventional liquid crystal electro-optical device using a simple matrix, It is difficult to manufacture large-capacity devices due to limitations in electro-optical properties. For example, in one using twisted nematic mode, 1/2
00 duty, about 1/40 even in S TN/S B E mode, which has high performance by increasing the angle.
When the duty is about 0, there is a problem that display quality or response speed deteriorates, making it impractical for practical use.

そこで、液晶とその配向制御によって記憶を持たせる(
印加電圧によるヒステリシス特性を利用するものJ、A
ppl、Phys、 、剣、3087.“86など)方
法が考えられた。これは、液晶材料によっては90度を
超える高ツイスト状態で印加電圧と透過率がヒステリシ
ス現象を起こすことを利用しており、選択的に書き込ん
だ情報を、ヒステリシスループ内となるような保持電圧
を印加することによって作持しJ:つとするものである
。以下、本発明では、この方式のことをHT N方式と
略記する。
Therefore, memory is created using liquid crystals and their orientation control (
J, A that utilizes hysteresis characteristics due to applied voltage
ppl, Phys, , sword, 3087. This method takes advantage of the fact that depending on the liquid crystal material, a hysteresis phenomenon occurs between the applied voltage and the transmittance in a highly twisted state exceeding 90 degrees. This is achieved by applying a holding voltage that falls within the hysteresis loop.Hereinafter, in the present invention, this method will be abbreviated as the HTN method.

このHT N方式を用いた電気光学装置においては、電
気光学特性にヒステリシス特性が発現するには種々の条
件を満たすことが必要である。すなわち、電気光学装置
を(1り成する液晶パネルにおけるツイスト角、セル厚
、プレチルト角、液晶組成物の自発ピッチ、弾性定数、
配向膜と液晶分子の相互作用の状況等によってヒステリ
シス特性の発現状況が異なってくる。一般には、プレチ
ルト角が犬、ツイスト角が大、界面規制力が大、弾性定
数の比K ”s/ K + +、Kり3/に22が共に
犬、Δε/ε土が小、液晶セルのピッチPcと液晶組成
物の自発ピッチPsのずれ△P (= Pc/Ps −
1)が小の方向にある等の方がヒステリシス特性が発現
し易いという傾向にある。
In an electro-optical device using this HTN method, various conditions must be satisfied in order for hysteresis characteristics to appear in the electro-optical characteristics. That is, the electro-optical device (the twist angle, cell thickness, pretilt angle, spontaneous pitch of the liquid crystal composition, elastic constant,
The state of expression of hysteresis characteristics differs depending on the state of interaction between the alignment film and liquid crystal molecules. In general, the pretilt angle is large, the twist angle is large, the interfacial regulating force is large, the ratio of elastic constants K ''s/K + +, Kri3/ and 22 are both small, Δε/ε is small, and the liquid crystal cell ΔP (= Pc/Ps −
There is a tendency that hysteresis characteristics are more likely to occur when 1) is in the small direction.

[発明が解決しj;うとする問題点] しかし、界面規制力、弾性定数等、他の条件にも左右さ
れるが、例えば、極端に△Pを小さくする、言い替えれ
ばカイラルドーパントの量を減らしたり、セル厚を厚く
したりすると、液晶組成り勿側のツイスト力が入れ物と
してのセル側で規制するツイスト角に達しなくなり、い
わゆるローツイストドメインが発生ずるようになって電
気光学装置としては使えなくなる。
[Problems to be solved by the invention] However, it depends on other conditions such as interfacial regulating force and elastic constant, but for example, it is possible to make △P extremely small, or in other words, reduce the amount of chiral dopant. If the cell thickness is increased, the twisting force of the liquid crystal composition will no longer reach the twist angle regulated by the cell side as a container, and a so-called low twist domain will occur, making it unusable as an electro-optical device. It disappears.

このローツイストドメインが発生ずる領域と、通常のヒ
ステリシス特性が発現する領域の間は不安定領域となり
、異常なヒステリシス現象を示すことがある(以下、異
常ヒステリシスと呼ぶ)。
The region between the region where this low twist domain occurs and the region where normal hysteresis characteristics are expressed becomes an unstable region, which may exhibit an abnormal hysteresis phenomenon (hereinafter referred to as abnormal hysteresis).

通常、ヒステリシス特性を有する液晶パネルの電気光学
特性を測定する場合には、駆動電圧の掃引スピードをで
きる限り小さくする。しかし、ヒステリシス特性は、測
定する際の駆動電圧の掃引スピードによって影響を受け
ることが多い。HT N方式の液晶パネルの場合にも、
通花のヒステリシス特性を示す領域では、掃引スピード
を非常に遅くすると、駆動電圧上昇過程では第2図a、
駆動電圧下降過程では第2図すに示すような特性を示す
が、掃引スピードを速くすると、駆動電圧上昇過程では
第2図C,駆動電圧下降過程では第2図dで示すように
、ヒステリシス特性の幅が異なるような特性を示す。し
かし、上記の異常ヒステリシス領域では、この傾向がさ
らに助長され、駆動電圧の掃引スピードが充分に遅けれ
ば第2図a、bで示されるような通常のヒステリシス特
性を示すが、駆動電圧の掃引スピードが速い場合には、
駆動電圧上昇過程では第2図Cとほぼ同じ特性を示すが
、駆動電圧下降過程では第2図eに示ずにうな特性を示
し、ON状態から電圧をゼロにして消去しようとしても
、表示が消えるまでには非常に長い時間を必要とする。
Normally, when measuring the electro-optical characteristics of a liquid crystal panel having hysteresis characteristics, the sweep speed of the driving voltage is made as small as possible. However, hysteresis characteristics are often affected by the sweep speed of the drive voltage during measurement. Even in the case of HT N type liquid crystal panels,
In the region showing the hysteresis characteristic of Tsuka, if the sweep speed is made very slow, the driving voltage rise process will be as shown in Figure 2a,
The driving voltage falling process exhibits the characteristics shown in Figure 2 (S), but when the sweep speed is increased, the hysteresis characteristics change as shown in Figure 2 (C) in the driving voltage rising process and Figure 2 (D) in the driving voltage falling process. It shows characteristics such that the width of the width is different. However, in the above-mentioned abnormal hysteresis region, this tendency is further exacerbated, and if the sweep speed of the drive voltage is slow enough, normal hysteresis characteristics as shown in Figure 2 a and b are exhibited, but the sweep speed of the drive voltage is If is fast, then
In the process of increasing the driving voltage, it shows almost the same characteristics as in Figure 2C, but in the process of decreasing the driving voltage, it shows characteristics not shown in Figure 2e, and even if you try to erase it by turning the voltage to zero from the ON state, the display will not work. It takes a very long time to disappear.

従来のHT N方式での駆動波形の概念は第3図に示す
ように、前の表示状態を保持している保持期間th1、
ゼロポル)・を印加して前の表示状態を消去する消去期
間te、新しい表示状態を書き込む書き込み期間tw、
さらにヒステリシスループ内となる保持電圧vhを印加
して表示状態を保持する保持期間し++2とからなる。
As shown in Figure 3, the concept of the drive waveform in the conventional HT N method is as follows: a holding period th1 during which the previous display state is maintained;
an erasure period te in which the previous display state is erased by applying zeropol); a write period tw in which a new display state is written;
Furthermore, the holding period consists of ++2 during which the display state is maintained by applying the holding voltage vh that falls within the hysteresis loop.

従って、保持電圧vhのON状態から、ゼロボルトを印
加して?111去しようとする場合は、前述の掃引スピ
ードが速い場合に相当し、異花ヒステリシス特性を示す
液晶パネルでは消去時間が非′、lKに長くなってしま
い、電気光学装置として使用するには非常に問題があっ
た。
Therefore, from the ON state of the holding voltage vh, apply zero volts? 111 corresponds to the case where the sweep speed is high as described above, and the erasing time becomes extremely long for liquid crystal panels exhibiting hysteresis characteristics, which is extremely difficult to use as an electro-optical device. There was a problem.

そこで本発明では、ΔPの許容範囲を広げ、液晶パネル
の製造を容易にすることが可能なHT N方式を用いた
電気光学装置の駆動方法を提供することを目的としてい
る。
Therefore, an object of the present invention is to provide a method for driving an electro-optical device using the HTN method, which can widen the allowable range of ΔP and facilitate the manufacture of liquid crystal panels.

[問題点を解決するための手段] 本発明では、書き込まれた表示内容を保持電圧を印加し
て保持する方法で駆動されるヒステリシス特性を有する
電気光学装置の駆動方法において、消去をパルス電圧と
ゼロもしくは略ゼロボルトの電圧双方を印加することで
行なうことを特徴とする特 〔実施例〕 以下、実施例に基づき本発明の詳細な説明する。
[Means for Solving the Problems] In the present invention, in a method of driving an electro-optical device having a hysteresis characteristic, which is driven by applying a holding voltage to hold written display contents, erasing is performed using a pulse voltage. Embodiment The present invention will be described in detail below based on embodiments.

(実施例1) 電気光学装置として、750’X1120画素のHTN
方式の液晶パネルを試作した。配向処理としてはSiO
の斜方蒸着によって液晶分子のプレチルト角を25度、
上下基板間の液晶のツイスト角を270度とし液晶を注
入して液晶パネルとした。
(Example 1) As an electro-optical device, HTN with 750' x 1120 pixels
We prototyped a liquid crystal panel using this method. For orientation treatment, SiO
The pretilt angle of liquid crystal molecules is set to 25 degrees by oblique evaporation of
The twist angle of the liquid crystal between the upper and lower substrates was set to 270 degrees, and the liquid crystal was injected to form a liquid crystal panel.

このパネルにメルク社製のZ L I −3187にカ
イラルドーパントとじてBDH社のCB−15を添加し
たものを封入して、液晶パネルとした。
This panel was filled with Z L I-3187 manufactured by Merck and CB-15 manufactured by BDH as a chiral dopant, thereby preparing a liquid crystal panel.

界面規制力などセル製造の各条件によってヒステリシス
特性の発現状況は異なるが、発明者らの実験では、例え
ば4.4μmのセル厚の液晶パネルに、メルク社のZL
I−3187にカイラルドーパントとしてB D H社
のCB−15を2.43〜2.17wt%添加した液晶
を注入し、△Pの値を−0,05〜−0,15としたも
のについては通常のヒステリシス特性が得られた。また
、CB−15の添加量を2.05w−1;%以下とし、
ΔPを−0,2よりも小さくするとローツイストドメイ
ンが発生ずることが多くなった。△Pの値が−0,15
〜−0,2の領域ではローツイストドメインは発生しな
いが、液晶パネルの製造条件によっては異常ヒステリシ
スを示したり、示さなかったりした。
The appearance of hysteresis characteristics differs depending on the cell manufacturing conditions such as interfacial regulation force, but in the inventors' experiments, for example, Merck's ZL was used in a liquid crystal panel with a cell thickness of 4.4 μm.
For I-3187, a liquid crystal containing 2.43 to 2.17 wt% of CB-15 from BDH as a chiral dopant was injected, and the value of ΔP was set to -0.05 to -0.15. Normal hysteresis characteristics were obtained. In addition, the amount of CB-15 added is 2.05w-1% or less,
When ΔP was made smaller than -0.2, low twist domains were often generated. The value of △P is -0,15
Although no low twist domain occurs in the range of ~-0.2, abnormal hysteresis may or may not occur depending on the manufacturing conditions of the liquid crystal panel.

これらの液晶パネルで、例えばΔPを−0,1とした通
常のヒステリシス特性を示す液晶パネルでは、30°C
において、第3図に示した従来のHTN方式のゼロボル
ト印加の消去法では13 m5ecで消去が可能てあっ
た。一方、△Pを−0,2とした異常ヒステリシスを示
す液晶パネルでは、従来のHTN方式の消去波形では速
くても数百m5ec、遅い場合には数秒の単位の消去時
間が必要であったに対し、第1図(a)あるいは(b)
に示ずJ:うに、消去期間の先頭に保持電圧よりも高い
電圧消去用高パルスを印加し、それに引続きゼロボルト
を印加する消去波形とすることで消去時間を非常に短か
くすることができた。消去用高パルス印加時間tsを5
〜0 、 2 m5ecとしたときの、消去用高パルス
電圧Ve対する消去時間τe (msec)の値を第1
表に示す。
Among these liquid crystal panels, for example, liquid crystal panels that exhibit normal hysteresis characteristics with ΔP of -0 and 1 have a temperature of 30°C.
In the conventional HTN erasure method of applying zero volts shown in FIG. 3, erasure was possible in 13 m5ec. On the other hand, for liquid crystal panels exhibiting abnormal hysteresis with ΔP of -0 and 2, the erasing waveform of the conventional HTN method requires an erasing time of several hundred m5ec at the fastest, and several seconds at the slowest. On the other hand, Fig. 1 (a) or (b)
Not shown in J: By applying a high voltage erase pulse higher than the holding voltage at the beginning of the erase period, and then applying zero volts to the erase waveform, we were able to make the erase time extremely short. . The high pulse application time ts for erasing is set to 5
The value of the erasing time τe (msec) for the high pulse voltage Ve for erasing when 0, 2 m5ec is the first
Shown in the table.

現時点ではその機構まで確定できる段階ではないが、O
N状態、すなわち、書き込みによって液晶分子が立って
いる状態は準安定状態であり、ここからOFF状態、す
なわち、液晶分子が水平配向している状態になるために
は、何等かのポテンシャルの壁を乗り越えなければなら
ないが、消去パルスを印加することがそのエネルギーを
外部から与えることになり、自然緩和による消去にりも
速くなるのではないかと考えている。
At this point, we are not at the stage where we can confirm the mechanism, but O
The N state, that is, the state in which the liquid crystal molecules stand up due to writing, is a metastable state, and in order to go from this state to the OFF state, that is, the state in which the liquid crystal molecules are horizontally aligned, some kind of potential wall must be overcome. Although we have to overcome this problem, we believe that by applying an erase pulse, the energy is given from the outside, and erasing due to natural relaxation may be faster.

第1表から、消去用高パルスは高電圧で印加時間が短か
い方がよいことが判る。
From Table 1, it can be seen that it is better for the erasing high pulse to have a high voltage and a short application time.

以上、現象の原理については推測の域を出ないが、本発
明によれば消去時間を短くすることが可能なことは事実
である。
As described above, although the principle of the phenomenon remains in the realm of speculation, it is a fact that according to the present invention it is possible to shorten the erasing time.

〔実施例2〕 電気光学素子として、400X640画素の■(TN方
式のパネルを試作した。配向処理は実施例1と同様に、
SiO斜方蒸着とし、プレチルト角25度、ツイスト角
270度、セル厚6.0μmとし、メルク社のZ L 
I−1132にカイラルドーパントとしてB D H社
のCB−15を添加した液晶を封入した。
[Example 2] As an electro-optical element, a 400 x 640 pixel (TN type) panel was prototyped. The orientation treatment was the same as in Example 1.
SiO oblique evaporation, pre-tilt angle of 25 degrees, twist angle of 270 degrees, cell thickness of 6.0 μm, Merck &Co.'s Z L
I-1132 was filled with liquid crystal to which CB-15 from BDH was added as a chiral dopant.

この液晶パネルにおいては、CB−15の添加量が1.
90〜1.1.1wt%、△Pの値にして0.3〜−0
.2の領域では正常なヒステリシス特性が得られ、CB
−15の添加量が1.07〜1゜ 02wt%で、 △
Pが−0,25〜−0,3の領域では以上ヒステリシス
が発生ずる。また、CB−15の添加量を1.02wt
%以下にし、ΔPが−0,3以下になるとローツイスト
ドメインの発生ずる領域になる。△Pが−0,2〜−0
゜25の領域は不安定で以上ヒステリシスを示したり、
示さなかったりする。
In this liquid crystal panel, the amount of CB-15 added was 1.
90~1.1.1wt%, △P value is 0.3~-0
.. In the region 2, normal hysteresis characteristics are obtained, and CB
-15 addition amount is 1.07~1゜02wt%, △
Hysteresis occurs in the range of P from -0.25 to -0.3. In addition, the amount of CB-15 added was 1.02wt.
% or less, and when ΔP is -0.3 or less, it becomes a region where low twist domains occur. △P is -0,2~-0
The region of °25 is unstable and shows hysteresis,
It may not be shown.

△Pが−0,3の以上ヒステリシスを示す液晶パネルを
用いて、実施例1と同様に消去時間を測定したところ、
25°Cにおいて、消去パルス電圧Ve=20V、消去
パルス印加時間te=0.5m5ecの条件で、第3図
に示す従来のHTN方式の消去波形では約5 secで
あったのに対し、第1図(a)および(b)の本発明の
消去波形では40m5ecで消去が可能であった。
When the erasing time was measured in the same manner as in Example 1 using a liquid crystal panel exhibiting hysteresis with ΔP of -0.3 or more,
At 25°C, under the conditions of erase pulse voltage Ve=20V and erase pulse application time te=0.5 m5ec, the erase waveform of the conventional HTN method shown in FIG. With the erasing waveforms of the present invention shown in FIGS. (a) and (b), erasing was possible in 40 m5ec.

以上、実施例を述べたが、本発明は上記実施例にのみ限
定されるものではなく、消去期間中にゼロボルト以外の
電圧を印加するもの全てに適用てき、その電圧、パルス
幅などの条件に何等制限を与えるものではないことはい
うまでもない。
Although the embodiments have been described above, the present invention is not limited to the above embodiments, but can be applied to any device that applies a voltage other than zero volts during the erase period, and can be applied to any voltage, pulse width, etc. Needless to say, this does not impose any restrictions.

[発明の効果] 以上、説明したように、本発明によれば、書き込まれた
内容を保持電圧を印加して保持する方法で駆動されるヒ
ステリシス特性を有する電気光学装置の駆動方法におい
て、本来ならば実用的な消去ができないために使用する
ことができない、異常ヒステリシスを示す液晶パネルて
も短時間で表示を消去することが可能になり、液晶パネ
ルの製造マージンを増加することて製造が容易になると
いう大きな効果を有する。
[Effects of the Invention] As described above, according to the present invention, in a method for driving an electro-optical device having a hysteresis characteristic that is driven by a method of applying a holding voltage to hold written contents, Even if a liquid crystal panel exhibits abnormal hysteresis, which cannot be used because practical erasing cannot be performed, it becomes possible to erase the display in a short time, increasing the manufacturing margin of the liquid crystal panel and making it easier to manufacture. It has the great effect of becoming.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の駆動波形の概念を示す図である。 第2図は、ヒステリシス特+1.を有する電気光学装置
の電気光学特11:を1t12明する図である。 第3図は、従来にHT N方式の駆動波形の概念をを示
す図である。 以    上 第1図 7i 第2図 一12= 第3図
FIG. 1 is a diagram showing the concept of drive waveforms of the present invention. Figure 2 shows the hysteresis characteristic +1. FIG. 12 is a diagram illustrating electro-optical characteristics 11: of an electro-optical device having the following. FIG. 3 is a diagram showing the concept of drive waveforms in the conventional HTN method. Above Figure 1 7i Figure 2-12 = Figure 3

Claims (1)

【特許請求の範囲】[Claims] (1)書き込まれた表示内容を保持電圧を印加して保持
する方法で駆動されるヒステリシス特性を有する電気光
学装置の駆動方法において、消去をパルス電圧とゼロも
しくは略ゼロボルトの電圧双方を印加することで行なう
ことを特徴とする電気光学装置の駆動方法。
(1) In a method of driving an electro-optical device having a hysteresis characteristic, which is driven by applying a holding voltage to hold written display contents, erasing is performed by applying both a pulse voltage and a voltage of zero or approximately zero volts. 1. A method for driving an electro-optical device, characterized in that the driving method is performed by:
JP62256912A 1987-10-12 1987-10-12 Driving method of electro-optical device Expired - Fee Related JP2727546B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62256912A JP2727546B2 (en) 1987-10-12 1987-10-12 Driving method of electro-optical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62256912A JP2727546B2 (en) 1987-10-12 1987-10-12 Driving method of electro-optical device

Publications (2)

Publication Number Publication Date
JPH0199031A true JPH0199031A (en) 1989-04-17
JP2727546B2 JP2727546B2 (en) 1998-03-11

Family

ID=17299108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62256912A Expired - Fee Related JP2727546B2 (en) 1987-10-12 1987-10-12 Driving method of electro-optical device

Country Status (1)

Country Link
JP (1) JP2727546B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07107000A (en) * 1993-09-30 1995-04-21 Nec Corp Portable radio equipment
US5454451A (en) * 1991-12-27 1995-10-03 Bridgestone Corporation Process for controlling vibration damping force in a vibration damping device
WO2005093509A1 (en) * 2004-03-29 2005-10-06 Seiko Epson Corporation Electrophoretic display, method for driving electrophoretic display, and storage display

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6446730A (en) * 1987-08-17 1989-02-21 Seiko Epson Corp Driving method for electro-optical element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6446730A (en) * 1987-08-17 1989-02-21 Seiko Epson Corp Driving method for electro-optical element

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5454451A (en) * 1991-12-27 1995-10-03 Bridgestone Corporation Process for controlling vibration damping force in a vibration damping device
JPH07107000A (en) * 1993-09-30 1995-04-21 Nec Corp Portable radio equipment
WO2005093509A1 (en) * 2004-03-29 2005-10-06 Seiko Epson Corporation Electrophoretic display, method for driving electrophoretic display, and storage display
US7701435B2 (en) 2004-03-29 2010-04-20 Seiko Epson Corporation Electrophoretic display, method for driving electrophoretic display, and storage display
US8300009B2 (en) 2004-03-29 2012-10-30 Seiko Epson Corporation Electrophoretic display, method for driving electrophoretic display, and storage display

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