JPH02126341A - Central processing unit - Google Patents

Abstract

PURPOSE:To speed up a trap processing operation by providing an instruction decoding part having an instruction code register, an instruction executing part, an instruction mark register, a trap instruction register and a comparator with a mask. CONSTITUTION:An instruction decoding part 1 stores an instruction code IC to an instruction code register 11, decodes it and informs an instruction executing part 2 of decoded instruction information DINS. The executing part 2 executes an instruction INS based on information DINS and sets the value to a trap instruction register 4 and an instruction mask register 3. At this time, the value to registers 4 and 3 is set by the execution of a special instruction beforehand, and the instruction code IC stored in the register 11 is compared with a trap instruction signal TI by a comparator 5 with a mask. When the result of the comparator with the mask is all coincident, the trap is informed to the executing part 2 by a trap signal TR, and the executing part 2 immediately executes the trap processing. Thus, it is sufficient even when processing is not executed each time all instructions complete the execution and the action can be speeded up.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a central processing unit, and particularly to a central processing unit of an information processing device configured to generate a trap signal to check the execution status of an instruction code. Regarding.

[Conventional technology]

Conventionally, in this type of central processing unit, when checking the execution status of a specific instruction code, a trap signal is generated every time the execution of all instructions is completed, and the instruction code of the next instruction to be executed is sent to the software in the trap processing program. I was checking it.

[Problem to be solved by the invention]

The above-described conventional central processing unit is configured to generate a trap each time the execution of each instruction is completed and check the instruction code using software, which has the disadvantage of slow operation speed.

An object of the present invention is to provide a central processing unit that can operate at high speed.

[Means to solve the problem]

The central processing unit of the present invention includes an instruction decode section that includes an instruction register that stores at least an instruction code of an instruction code and an address field of an instruction, and that decodes the instruction and outputs decoded instruction information; A trap instruction signal of a specific pattern for executing the instruction according to the information and having the same number of bits as the output signal of the instruction register and generating a trap, and a trap instruction signal having the same number of bits as the trap instruction signal and for each of these bits. an instruction execution unit that outputs an instruction mask signal for specifying a mask and performs trap processing when a trap signal is input;
A trap instruction register and an instruction mask register respectively store a trap instruction signal and an instruction mask signal from the instruction execution unit, and output signals of the instruction register, instruction mask register, and trap instruction register are input to the instruction register. and a comparison with a mask that compares the output signals of the trap instruction register for each corresponding bit, and outputs the trap signal when the comparison results for each of the bits that are not masked by the corresponding bit of the instruction mask signal do not all match. It has a container.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment includes an instruction code register 11 that stores an instruction code of an instruction INS and an instruction code of an address field, an instruction decoder 1 that decodes the instruction INS and outputs decoded instruction information DINS, and an instruction decoder 1 that decodes the instruction INS and outputs decoded instruction information DINS. A trap instruction signal TI of a specific pattern for executing the instruction INS according to the instruction information DINS and having the same number of bits as the output signal of the instruction code register 11 and generating a trap, and a trap instruction signal TI having the same number of bits as the trap instruction signal TI. An instruction execution unit 2 outputs an instruction mask signal IM that specifies a mask for each of these bits, and performs trap processing when a trap signal TR is input, and an instruction mask that inputs, stores, and outputs the instruction mask signal IM. a register 3, a trap instruction register 4 for inputting, storing and outputting a trap instruction signal TI, and an instruction register 11. The output signals IC, IM, and TI of the instruction mask register 3 and the trap instruction register 4 are input, and the output signals IC, TI of the instruction register 11 and the trap instruction register 4 are compared for each corresponding bit, and the output signals IC, IM, and TI of the instruction mask register 3 and the trap instruction register 4 are compared for each corresponding bit. The configuration includes a masked comparator 5 that outputs a trap signal TR when all of the comparison results for each bit that are not masked by the corresponding bits match.

Next, the operation of this embodiment will be explained.

The instruction decoding unit 1 stores the instruction code IC in the instruction code register, decodes it, and generates decoded instruction information DIN.
S is notified to the instruction execution unit 2.

The instruction execution unit 2 executes the instruction INS based on the decoded instruction information DINS, and also sets values in the trap instruction register 4 and the instruction mask register 3.

Values are set in the trap instruction register 4 and instruction mask register 3 in advance by executing a special instruction, and the instruction code IC stored in the instruction code register 11 is compared with the trap instruction signal TI by the comparator with mask 5. . If all the results of this masked comparison match, a trap is notified to the instruction execution unit 2 by the trap signal TR, and the instruction execution unit 2 immediately starts trap processing.

Note that the trap instruction register 4. Instruction mask register 3
By using a plurality of sets of comparators 5 and masked comparators 5, it is possible to check a plurality of different instruction codes at the same time.

FIG. 2 is a circuit diagram showing a specific circuit of the masked comparator 5 of this embodiment, and shows the instruction mask signals IMO to IMn.
The instruction codes ICO to ICn and the trap instruction signals TIO to T are
In is compared to detect whether or not they match. That is, the comparison is performed on the portions not masked by the instruction mask signals IMO to IMn.

FIG. 3 is a block diagram showing a second embodiment of the invention.

In this embodiment, in addition to the instruction code register 11, an address field register 12 is provided in the instruction decode section IA.

The address field register 12 is the instruction decode section IA.
This is a register that stores the address field that specifies the operand of the instruction when decoding the instruction.

In this embodiment, the bit length of trap instruction register 4, instruction mask register 3, and masked comparator 5 is equal to the sum of the bit lengths of instruction code IC and address field AF.

That is, a trap can be generated by simultaneously comparing the instruction code IC and the address field AF with a mask. Further, depending on the value of the mask, a trap can be generated only in the address field AP, regardless of the instruction code IC.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which trap processing is performed when a specific instruction is detected by specifying a mask for each bit, thereby eliminating the need to perform trap processing every time the execution of all instructions is completed as in the past. This has the effect of greatly speeding up the operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
This figure is a specific circuit diagram of the masked comparator according to the embodiment shown in FIG. 1, and FIG. 3 is a block diagram showing a second embodiment of the present invention. 1, IA...instruction decoding section, 2... instruction execution section,
3... Instruction mask register, 4... Trap instruction register, 5... Comparator with mask, 11... Instruction code register, 12... Address field register,
Gll~G, fl, G2. ~a2Il, G3...
gate circuit. nose concession

Claims (1)

[Claims] an instruction decode unit that includes an instruction register that stores at least an instruction code of an instruction code and an address field of an instruction, and that decodes the instruction and outputs decoded instruction information; and executes the instruction according to the decoded instruction information; and a trap command signal having the same number of bits as the output signal of the command register and having a specific pattern for generating a trap; and a command mask signal having the same number of bits as the trap command signal and specifying a mask for each of these bits. a trap instruction register and an instruction mask register that respectively store a trap instruction signal and an instruction mask signal from the instruction execution section, respectively; The output signals of an instruction register, an instruction mask register, and a trap instruction register are input, and the output signals of the instruction register and trap instruction register are compared for each corresponding bit, and each of the output signals not masked by the corresponding bit of the instruction mask signal is compared. A central processing unit comprising: a comparator with a mask that outputs the trap signal when all bit-by-bit comparison results match.