JPH02126352A - Data transfer control method for information processing equipment - Google Patents

Abstract

PURPOSE:To quickly start the execution of a data transfer microprogram and to improve the throughput of a data transfer by making the value of a starting pointer larger than the value of an end pointer when an error is detected. CONSTITUTION:At a channel control part 200, a starting pointer generating circuit 205 and an end pointer generating circuit 206 are provided. When the error of a starting pointer 202 or an end pointer 203 received from a channel device 100 is detected by an error detecting circuit 204, generation and output are executed so that the value of the pointer 202 is larger than the value of the pointer 203. Thus, when at a storing control part 300, the value of a pointer 301 received from the control part 200 is larger than the value of a pointer 302, the instruction that the byte to be written is absent is issued and the data transfer is executed. Consequently, since a data transfer microprogram can quickly start the execution without writing the data to the erroneous address of a memory 500, the throughput of the data transfer can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data transfer control method for an information processing device,
In particular, the present invention relates to a data transfer control method suitable for improving the throughput of data transfer from an input/output device to a main storage device via a channel.

[Conventional technology]

FIG. 4 shows a block diagram of an information processing device that uses a conventional data transfer control method.
The configuration is shown when data is transferred to the storage device 500 by way of transfer. FIG. 5 shows an operation time chart of the channel control section 200 in this case.

The data read from the input/output device is sent to the channel device 10.
As shown in FIG. 5, each 4 byte is transferred to the 0 data buffer 101 in 8 machine cycles. Channel device], 00 data in the data buffer 101 is written to the main memory 501 of the storage device 500 via the storage control unit 300.

The channel device 100 uses the buffer 01 as a pointer to indicate the byte position to actually load out of 32 bytes of data transferred to the storage device 500 via the buffer 201 of the channel control unit 200 and the storage control unit 300. , a start pointer 10 indicating the write start byte position
2. It has an end pointer 103 that indicates the write end byte position.

The start pointer 102 and end pointer 102 each consist of 5 bits+parity pit (P). When data is transferred from the buffer 101 of the channel device 100 to the buffer 201 of the channel control unit 200, the start pointer ]02 and the end pointer 103 are set in the bit serial format in accordance with the timing shown in FIG. Pointer 202. It is transferred to the end pointer 203.

In the channel control unit 200, a start pointer 202,
The end pointer 203 is parity-checked by the error detection circuit 204, and if no error is detected, the steal control circuit 2
The steal request signal 209 is output from 07, the data transfer microprogram 401 of the execution control unit 400 is activated, and at the timing shown in FIG. It is written into the storage device 501 via the control circuit 303. At this time, the start pointer 202 and end pointer 203 are also sent to the start pointer 301 and end pointer 302 held in the storage control unit 300. The mark generation circuit 304 uses this start pointer 30
J1, the end pointer 302 generates 8-bit mark data that indicates byte-by-byte positions of the 32-byte data to actually write, and supplies it to the write data control circuit 303. Write data control circuit 3
03, the buffer 201 of the channel control unit 200 is
Select the byte to be written out of the 32 bytes of data received from .

Transfer to storage device 500.

On the other hand, in the channel control section 200, the start pointer 202 and the end pointer 203 are connected to the error detection circuit 200.
If a parity error is detected in step 4, the steal request signal 209 is not output from the steal control circuit 207, so the data transfer microprogram 401 of the execution control unit 400 is not activated, and the data is transferred from the buffer 201 to the storage device 500. will also not be implemented.

Incidentally, a known document related to this type of data transfer control system includes, for example, Japanese Patent Laid-Open No. 63-26756.

[Problem to be solved by the invention]

In the prior art shown in FIG. 4, an error in the start pointer 202 or end pointer 203 is
00, it is necessary to prevent the execution control unit 400 from stealing the data transfer microprogram 401. Therefore, the steal request signal 209 from the steal control circuit 207 is sent to the start pointer 202 and end pointer in the error detection circuit 204. There is a problem in that the data must be output after the error detection of the pointer 203 is completed, making it impossible to improve the throughput of data transfer. An object of the present invention is to make it possible to output a steal request signal to a data transfer microprogram before the end pointer and end pointer errors are detected.
The purpose is to start execution of a data transfer microprogram early and improve data transfer throughput.

[Means to solve the problem]

In order to achieve the above object, in one embodiment of the present invention, if there is an error in the start pointer and end pointer received from the channel device, for example in the channel control unit, the value of the start pointer is lower than the value of the end pointer. Change the start pointer and end pointer values to increase the star 1 pointer generator 1.
A circuit, an end pointer gene ~1 node circuit is provided.

[For production]

When the error detection circuit detects an error in the star pointer or end pointer received from the channel device, the star pointer generation circuit and end pointer generation circuit convert the values of the star pointer and end pointer into Generate and output so that the start pointer is larger than the end pointer. If no error is detected, the received value is output as is. In the storage control unit, if the values of the start pointer and ento point 5 inter received from the channel control unit have a relationship of start pointer>end pointer. The data transfer microprogram issues an instruction that there is no bye-1- to be written to the storage device and executes the data transfer.Therefore, the data transfer microprogram does not write data to an incorrect address in the storage device.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a start pointer generation circuit 20 is included in a channel control section 200.
5. The difference from FIG. 4 is that a pointer generation circuit 206 is added.

The configuration other than the stiffness is basically the same as that in FIG. 4.

FIG. 2 shows a detailed circuit diagram of the start pointer generation circuit 205 and the end pointer generation circuit 206, and FIG. 3 shows an operation time chart according to the present invention.

In FIG. 1, data read from input/output device 1 is stored in buffer JO1 within channel device 12100. The data in the buffer 101 of the channel device 100 is processed at 4 times per machine cycle at the timing shown in FIG.
It takes 8 machine cycles for each byte, and each time 32 pies are transferred to the data buffer 201 of the channel control unit 200.
will be forwarded to.

In parallel with writing to the data buffer 201, the steal request signal 2.9 is output from the steal control circuit 207, and the data transfer microprogram 4 of the execution control unit 400
01 is activated. As a result.

The data stored in the data buffer 201 of the channel control unit 200 is immediately written to the main memory 501 of the storage device 500 via the write data control circuit 303 of the storage control unit 300 under the control of the data transfer microprogram 401. It will be done.

The channel device loo transfers data from the buffer 101 to the buffer 201 . A start pointer 102 indicating the write start byte position serves as a pointer indicating the byte position to actually write among the 32 bytes of data transferred to the storage device 500 via the storage control unit 300;
It has an end pointer 103 indicating the write end byte position.

The start pointer and end pointer each consist of 5 bits + parity bit (P). When transferring data, this start pointer 102. The end pointer 103 is also sent bit serially from the channel device 100 to the channel control unit 200 at the timing shown in FIG.

The channel control unit 200 uses the start pointer 202 and end pointer 2 received from the channel device 100.
The serial data of 03 is converted to parallel data and the start pointer 202. Set in the end pointer 203. This start pointer 202, end pointer 203
is parity-checked by the error detection circuit 204.
The error signal from the error detection circuit 204 is input to a start pointer generation circuit 205 and an end pointer generation circuit 206. start pointer 20
5. The output of the end pointer 206 is also input to the start pointer generation circuit 205 and the end pointer generation circuit 206, respectively. The outputs of the start pointer generation circuit 205 and end pointer generation circuit 206 are input to the mark generation circuit 304 via the latches of the start pointer 302 and end pointer 302 in the storage control unit 300.

The mark generation circuit 304 generates a start pointer 3.
01, 8-bit mark data indicating the byte to be written out of the 32-byte data sent to the storage device 500 from the value of the end pointer 302 is generated and provided to the write data control circuit 303. The write data control circuit 303 selects bytes to be written from among the 32 bytes of data received from the buffer 201 of the channel control unit 200 based on the mark data from the mark generation circuit 304 and transfers them to the storage device 500. and then write it to main memory.

According to FIG. 2, the start pointer generation circuit 20
5. The operation of the end pointer generation circuit 206 will be described in detail. Start pointer 202° End pointer 20
3 are input to the parity check circuit 211, and if there is an error in at least one of them, an error signal is input to the start pointer generation circuit 205 and the end pointer generation circuit 206. When the start pointer generation circuit 205 receives the error signal from the error detection circuit 204, it suppresses input from the start pointer 203 and uniquely outputs the value (111110) as the start pointer. Upon receiving the error signal from the error detection circuit 204, the end pointer generation circuit 206 similarly generates the end pointer 203.
Suppresses input from and uniquely uses it as an end pointer (
000001) is output. That is, the start pointer and end pointer are changed so that the relationship of start pointer>end pointer holds.

If no error is detected in each parity check circuit 211, the start pointer generation circuit 205 and end pointer generation circuit 206 output the values of the start pointer 202 and end pointer 203 as they are. In this case, there is always a relationship between the start pointer and the end pointer.

Mark pointer generation circuit 3 of storage control unit 300
04 compares the values transferred from the start pointer generation circuit 205 and end pointer generation circuit 206 and set in the start pointer 301 and end pointer 302, and when the relationship of start pointer>end pointer is established, a mark is set. Set the data to all 0.

No indication of the byte to write data to. Thereby, writing to the main memory 501 can be suppressed.

Regardless of the output of the error detection circuit 204, the steal control circuit 207 operates at the timing shown in FIG. 3 as described above.
A steal signal 209 for starting the data transfer microprogram 401 is output to the execution control unit 400. Therefore, the data transfer microprogram 401 executes memory startup regardless of whether there is an error in the start pointer 202 or end pointer 203. However, if there is an error, the mark pointer generation circuit 304 specifies that all mark data is 0), writing to the main memory 501 will not be performed.

According to this embodiment, the data transfer microprogram 401 can be activated without waiting for the completion of error checking of the start pointer 202 and end pointer 203 received from the channel device 100.

Data transfer throughput is improved.

〔Effect of the invention〕

As explained above, according to the present invention, the data transfer microprogram can be activated before the error check of the start pointer and end pointer received from the channel device is completed, so that the throughput of data transfer can be improved. be. Furthermore, the present invention is also applicable to a format in which mark data is transferred together with data instead of the start pointer and end pointer. That is, when an error is detected in mark data, the mark data may be set to all 0s.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an information processing apparatus using the data transfer control method of the present invention, FIG. 2 is a detailed circuit diagram of the start pointer generation circuit and end pointer generation circuit of FIG. 1, and FIG. 3 1 is a time chart for explaining the operation of FIG. 1, FIG. 4 is a block diagram of an information processing apparatus using a conventional data transfer control method, and FIG. 5 is a time chart for explaining the operation of FIG. 4. 1... Input/output device, 102.202,301... Start pointer, 10
0...Channel device, 103.203,302...End pointer, 200
...Channel control unit, 204...Error detection circuit. 300...Storage control unit, 304...Mark pointer generation circuit. 400... Execution control unit, 500... Storage device,
501... Main memory, 205... Start pointer generation circuit, 20
6... End pointer generation circuit. 2nd ward

Claims (2)

[Claims] (1) An information processing device that transfers data blocks between an input/output device and a storage device, and when transferring a data block from the input/output device to the storage device, which data blocks should actually be written. In a data transfer control method in which a pointer indicating a data position is transferred together and a data block is written to a storage device based on the pointer, an error check is performed on the transferred pointer, and if no error is detected, the pointer is 1. A data transfer control method for an information processing apparatus, characterized in that the pointer is left as it is, and if an error is detected, the pointer is changed to a value indicating that there is no data position to write to. (2) The pointer consists of a start pointer that indicates the start position of writing to the storage device and an end pointer that indicates the end position of writing in the data block to be transferred from the input/output device to the storage device, and The information processing apparatus according to claim (1), characterized in that, when an error is detected in at least one of them, the values of the start pointer and the end pointer are changed so that the value of the start pointer exceeds the value of the end pointer. data transfer control method.