JPH02121349A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and in particular to a semiconductor integrated circuit that can design a high-speed large-scale integrated circuit (LSI) using a dynamic circuit in a short period of time, and its use. Regarding design methods.

[Conventional technology]

Conventionally, regarding high-speed theory *r, s■1 using dynamic circuits, see I Niss Niss C Digest on Technical Papers, 1987, p. 62 (T S S CC Digest of Technic
al papers, 1987. Discussed on p. 62). In addition, regarding speeding up using precharge circuits, see Symposium on VLSI Technology, Digest on Technical Papers, p. 93 (Symposium on VLSI Technology, Digest on Technical Papers, p. 93).
SI Technology, Digest of
Technical Pagers.

pp, 93. (1,987)) and JP-A-62-9
8827. Furthermore, regarding shortening the design period using automatic design systems, see Proceedings on I.C.C., 1982, pp. 512-515.
fICCC, 198z, Pp, 512-515) 4m
It's a well-argued tale.

[Problem to be solved by the invention]

Although the above-mentioned conventional precharge circuit can increase the speed of a circuit with complex logic capabilities, the following points must be kept in mind when designing an LSI using this circuit.

(1) If there is capacitive coupling between a dynamic node inside a circuit and a signal wiring in its vicinity, the dynamic node will be affected by potential fluctuations in the wiring during circuit operation, causing the potential to change, reducing the circuit's operating margin. , and may even cause malfunctions. Therefore, when designing a cell layout, it is necessary to pay attention to the capacitance between the wiring inside the cell and the dynamic node.

(2) For the same reason as above, signal wiring cannot be passed above cells using precharge circuits.

(3) It is necessary to supply clock signals of the same phase to all cells using precharge circuits.

First, regarding (1), when designing the layout of the various cells required for LSI design, the work must be done while paying attention to the above points for each cell, which makes automation difficult and extremely time-consuming. It took. Furthermore, the amount of work required to modify cells when layout rules, processes, etc. are changed is enormous. Next, in the step of arranging the thus designed cells and wiring between the cells to complete the LSI, the above (2) has been a major obstacle to automatic placement and wiring using the DA core technology. Furthermore, regarding (3),
The clock signal power supply system had to be carefully designed throughout the LSI chip, making it difficult to convert it into a DA.

An object of the present invention is to enable high-speed LSI technology to be applied to LSIs using precharge circuits.
The objective is to be able to design SI in a short period of time.

Another object of the present invention is to make it possible to design a plurality of LSIs with the same logical function but different performance, cost, etc. from the set of design data, depending on the performance and cost required for the LSI.

Another object of the present invention is to reduce the number of design steps for cells, which are the basic unit of LSI design, and to make it possible to construct cells and libraries that can quickly respond to changes in layout rules and the like.

Another object of the present invention is to reduce the number of circuit stages in a logic circuit including a portion in which a plurality of precharge circuits are connected in cascade.

[Means to solve the problem]

In order to apply DA nuclear technology, the present invention covers high impedance nodes within the cell with a power supply wiring layer in a cell using a precharge type circuit, and provides a clock buffer that can be embedded in the cell column. Clock signal channels are provided along the columns.

Furthermore, in order to design LSIs with different characteristics from one set of design data, a plurality of cell libraries with the same function but different processes and circuits are provided.

In addition, in order to reduce the number of steps required for cell design, a cell library was created from several types of basic cells and information on the intra-cell wiring for each cell.

Furthermore, two types of precharge type circuits are used in combination to reduce the number of logic circuit stages.

[Effect]

High impedance nodes within the cell are shielded by the power wiring layer, allowing wiring to pass over it. Further, by providing a clock buffer and a clock signal channel that can be embedded in a cell column, there are no restrictions on the arrangement of the clock buffer. With these, L
SI can be designed by automatic placement and routing using DA nuclear technology.

Furthermore, by selecting the optimal cell to use from among a plurality of cell libraries, it is possible to design according to required performance, cost, etc.

Furthermore, since cell layout work can be performed symbolically from basic cells and wiring information, the time required to construct a cell library can be significantly reduced.

Furthermore, by using two types of precharge circuits in combination, it is possible to eliminate the input signal control circuit required in the conventional example.

〔Example〕

The present invention will be explained in detail below.

FIG. 1 shows an example of a cell implementing the present invention, and FIG.
is a circuit diagram of a cell, (b) is a schematic diagram of the layout of the circuit in (a), and (C) and (d) are cell circuit diagrams of other circuit formats.

In the figure, 101, 103, and 104 are three-man-powered AND cells using a precharge circuit, and 102 is an inverter cell using a CMOS static circuit.

Cl0L, ClO2 are clock signal wiring, 1101-1
103 is an input signal wiring, vDD is a power supply wiring, GND is a ground wiring, 0101 is an output signal wiring of the AND cell 101, 0102 is an output signal wiring of the inverter cell 102,
0103 is the output signal wiring of 103, 0104 is the output signal wiring of 104, PIOI~P115 is PMO3FET,
Nl0I~N115 are NMO8FETs, 1 and 2 are NMO
8FET, 3.4 is a gate, 5, 6.8 is a contact hole for connecting a diffusion layer, 7 is a through hole for interconnection between cells, 9 to 11 are dynamic nodes, and 20 is a clock signal power supply terminal. Further, FIG. 2 shows a cross section taken along line XX in FIG. 1. 201 is a silicon substrate, 202 is a well, 203 is an oxide film, and 204, 205, and 206 are glabella insulating films. Note that in this figure, the wiring layer, interlayer insulating film, and passivation film located above [jlo] are omitted. In this example, 1. As shown in FIG. 1, in the cell 101 using a precharge circuit, specifications regarding the layout such as the arrangement of power supply and ground wiring, the outer shape and height of the cell, and the position of input/output terminals are specified. Since the setting is the same as that of the standard cell 102 of the CMOS static circuit, the cell can be arranged using the same DA core technology as the standard cell.

2. Above the dynamic nodes 9 to 11 in the cell are the power supply wiring VDD and ground wiring GN, which have a fixed potential.
Because it is almost covered by D.

Since the capacitance between the signal wiring 1101 passing above the cell and the dynamic node can be kept sufficiently small,
8Il above Cell! There are no limits to the line. This makes it possible to automate the connection wiring between cells, similar to standard cells.

3. The clock signal wiring C101 is provided along the cell row and adjacent to the upper end of the cell. (1) Cells that require a clock signal are automatically connected by providing the clock signal power supply terminal 20. Connected to 0101. (2) D.A.
Therefore, there is no need to perform clock signal wiring when performing automatic placement and wiring.

According to 1 to 3 described above, by applying the present invention, automatic design using DA core technology similar to standard LSI cells including cells using a precharge circuit becomes possible. By providing the lock signal wiring C101 in the channel closest to the cell column, it is possible to prevent it from interfering with other signal wiring. Furthermore, since the number of FETs connected to the clock signal wiring is larger than that of other signal lines, the load capacity is large, and the current flowing through the wiring during operation is also large, so there are conditions for potential drop due to wiring resistance, increase in delay time, and migration. It is more difficult than other signal wiring. To alleviate this problem, as shown in Figure 1, C10
The line width of signal line 1 may be made wider than that of the other signal lines.

In the above embodiment, CMO8 was used as the circuit, but as a method for further increasing the speed, there is a Bi-CMO5 circuit using a bipolar transistor in combination, as described below. FIG. 3(a) shows a circuit diagram of a BjCMOS precharge circuit, and FIG. 3(b) shows a circuit diagram of a B1CMOS inverter circuit. C301 is clock signal wiring, 1301 to 1304 are input signal wiring, 0301゜03
02 is output signal wiring, P301 to P303 are PMO5F
ET, N301 to N310 are NMO8FET, Q301
~Q304 is an NPN type bipolar transistor.

Also, FIG. 4(a).

(b) is a B1C with a different circuit type from that in Figure 3 (,).
It shows a circuit diagram of a MOS precharge circuit,
C401 and C402 are clock signal wiring.

1401-1405 are human signal wiring, 0401°C41
1 is output signal wiring, P2O3~P404 and P411~
P415 is PMO3FET, N401 to N408 and N
411-N419 are NMO3FET, C401 and C4
11 is an NPN type bipolar transistor. FIG. 5 schematically shows an example of the layout of the circuit shown in FIG. 4(b). By applying the present invention in the same manner as in FIG. 1(b), automatic design using DA nuclear technology becomes possible.

Furthermore, since the circuit of FIG. 4(b) requires two clock signal wires C401 and C402, they are arranged adjacent to each other above and below the cell column as shown in FIG.

In this way, by making it possible to realize cells using BiCMO3 circuits, cells using 1, C, MO5 circuits and cells using BiCMO8 circuits can be treated equally from the point of view of automatic design using DA nuclear technology, allowing LSI logic designers to Using a set of logic design data input into the DA system, it is possible to automatically design both an LSI using 8 CMO circuits and an LSI using 3 BiCMO circuits. Generally, when using BiCMO5 circuit, CMO8
Although it is possible to realize a high-speed LSI compared to the case using circuits, the process is complicated and the cost is high. Therefore, the performance, cost, etc. required for the LSI to be designed can be met without changing the logical design.

2. Generally, when automatic design is performed by DA, the wiring length between cells increases and the variation thereof increases compared to when designing is done manually. This causes an increase in the load capacity of the circuit and an increase in its dispersion, as well as an increase in the delay time of the circuit and an increase in its dispersion. The former causes a decrease in circuit performance, and the latter is also equivalent to a decrease in performance because it is necessary to estimate in advance the performance change due to variations as a margin. If a BiCMO8 circuit is used here, the dependence of the circuit performance on the load capacitance is smaller than that of the CMO3 circuit due to its large current-immediate-acting capability, which can reduce performance deterioration due to the above factors, making it suitable for automatically designed LSIs. It is.

etc., and the effect is great.

Next, a method of constructing a cell library to which the present invention is applied will be described. Generally, when performing automatic design using the standard cell method, a cell library consisting of cells having various request functions is required.

Building a cell library requires dozens of types of cells, and in the past, these had to be laid out manually, resulting in an enormous amount of man-hours.

When a cell including a precharge circuit is laid out using the conventional method, the number of steps increases further because the above-mentioned points regarding the dynamic node must be taken into consideration.

The present invention solves this problem.

FIGS. 6(a), (b), and (c) show examples of circuit diagrams of cells included in the cell library.

These cells are necessary for constructing a carry lookahead generation circuit that is generally used for adders that require high speed performance. The carry lookahead generation circuit is discussed, for example, in Keikichi Tamaru's ``Fundamentals of Logic Circuits'', page 227.

A cell to which the present invention is applied has a MOS FET in the cell,
Several types of cells (with only layout information regarding devices such as bipolar transistors and resistors and power wiring)
By synthesizing a cell (hereinafter referred to as a basic cell) and a cell unique to each cell (hereinafter referred to as a wiring cell) that has only layout information regarding internal wiring layers, contact holes, through holes, etc. and the necessary arrangement of basic cells. create. Figures 7(a) and (b) show examples of basic cells, where P2O3 to P703 are PMO8FETs, N701-N
704 is an NMO5FET, Voo is a power supply wiring, and GND is a ground wiring. It is noted in the Proceedings of the I.C.C.
C.C., 1982, pp. 112-115 (
Proceedings of the 1982 I
CCC, 1982, pp. 112-115), the basic cell shown in FIG. 7 can easily implement such a design by including MOSFETs of various gate widths. FIG. 8 schematically shows the resultant array of completed cell layouts by combining basic cells and wiring cells. Figure 8 (or Figure 6 (a), Figure 8 (b) Figure 6 (b), Figure 8 (c) Figure 6 (
c) respectively. Figure 8(a).

The cell shown in FIG. 7(b) is created by combining the basic cell shown in FIG. 7(a) and a wiring cell specific to each cell. Also, the cell in FIG. 8(C) is as shown in FIG. 7(a).
It is created by arranging the basic cells of and (b) adjacent to each other and composing these and a wiring cell. Furthermore, the basic cell layout is performed in the same way as conventional cell layout, but the wiring cell layout is done only by the designer manually inputting the positions of contact holes, through holes, and wiring within the cell; The change work to D
Do it with A. With the cell generation method described above, a) the cell layout work, which conventionally required several dozen types, can be reduced to only a few types of basic cells.

b. By considering the handling of dynamic nodes at the time of basic cell design, there is no need to reconsider each cell as long as cells are synthesized using the basic cell.

Since the C1 wiring cell can be laid out in sympolink,
You can quickly change cell logic, add new cells, etc.

d. If it is necessary to modify the cell layout due to a change in layout rules, etc., all you need to do is modify the basic cell and change the DA parameters that change the symbolic data of the wiring cell into a pattern. The amount of work can be significantly reduced compared to the amount of modification that would otherwise have been required.

Effects such as these can be obtained, and the period required for building and modifying a cell library can be shortened.

A method for completing the LSI design by automatically arranging and automatically wiring the cells generated by the method described above using DA will be described below.

When designing an LSI, it is common to design a block with a certain logical group by placing and wiring cells, and then proceeding with the design in a hierarchical manner, such as placing and wiring the blocks. be. FIG. 9 schematically shows an example of a block constructed by arranging and wiring cells according to the present invention. 901 is the power main line, 90
2 is a ground main line, 910 to 924 are cells using a precharge circuit, B901 to B904 are clock buffer cells, C901 to C905 are clock signal line wiring, TH
901 to TH903 are through holes, 930 to 936 are intercell wiring lines, and 937 is a clock main line. When designing an LSI using a precharge circuit, it is necessary to supply in-phase clocks to all cells using the same circuit, and in order to do this, the loads on the clock buffer cells that feed crossshift signals to the cells must be equalized. However, it is necessary to prevent skew caused by differences in delay times. Figure 9 shows an example of this. In the top row of cells, 1 cell for 3 cells 910°911.
Clock buffer cells B901 and one clock signal wiring C901 are provided. On the other hand, in the second row of cells, there are many cells that require clocks, so
clock buffer cells B902. B9.03 and two clock signal wirings C902 and C903 are provided to divide the cell column into two and supply clocks. Furthermore, since there are fewer cells in the third and fourth stages that require clocks, the clock buffer cell B904 is commonly used in both stages, and clocks are supplied via clock signal lines C904 and C905. In this way, it is necessary to change the number of clock buffer cells so that the load on each clock buffer cell is approximately equal.
In the cell library to which the present invention is applied, this work can be automated for the following reasons.

1. The clock buffer cell is in the same cell library as a cell using a precharge circuit, etc., and the DA
can be treated equally from

2. Channels for clock signal wiring are provided along the cell rows.

FIG. 10 shows an example of a flowchart for automatic block placement and automatic wiring.

First, in step 1001, the logic designer inputs the design data of the target block. At this time, the clock supply system to the cells using the precharge circuit is automatically designed, so there is no need for input.

Next, in step 1002, cells are automatically temporarily placed based on the input design data. In the next step 1003, the load on the clock buffer cells of each cell column is calculated as a result of the temporary placement. In the following step 1004, a necessary number of clock buffer cells are inserted into the cell column so that the loads on each clock buffer cell are approximately equal. In this step, in a cell example that includes many cells that require clocks, many clock buffer cells are inserted, and as a result, the length of the cell string may be significantly different from other cell strings. This is checked in step 1005, and if it is inappropriate, the temporary arrangement is changed in step 1010. If there is no problem, wiring of the clock power supply system is performed in step 106, but since the cell to which the present invention is applied has a channel for clock signal wiring, this step can be easily performed. In the next step 1007, automatic wiring between cells is performed. In step 1008, it is checked whether the required wiring has been completed, and if it has not been completed, the temporary device is changed, and if it has been completed, compaction such as filling up empty channel areas is performed, and the automatic block design ends. .

Next, a method for automatically placing and routing blocks designed using the above method will be described.

FIG. 11 shows an example of the result of designing a tallock power supply system for an LSI according to the present invention, where 1100 is an LSI chip, B1
101 to B1105 are blocks.

1101 is a clock block, CPA is a clock input pad, iCB is a clock input buffer, CB is a clock buffer, CD is a clock driver LIIOI~L11
03. Li2O2 is the inter-block ')O') wiring, El
lol~E1105°B1112 is a clock input terminal. Naori Roshikuba Sofa CB is B901 in Figure 9.
This corresponds to the clock buffer cell of ~B904. Furthermore, L
Regarding the clock coupling system of SI, for example, I.N.C.C., Digest Off Technical Papers, 1987, p. 86 (ISSCCDiges
to of Technical papers, 19
87. pp. 86).

In the clock wiring between blocks, it is necessary to make the loads on each clock driver CD approximately equal, as in the case within the blocks described above. In the example of FIG. 11, block B11
o1 and B1105 are each assigned one clock driver and one interblock clock wiring, whereas block B1, which includes a large number of clock buffers CB,
Two clock drivers and inter-block clock wiring are assigned to 102. Furthermore, block B1103 and block B1104 with few clock buffers share one clock driver and inter-block clock wiring. FIG. 12 shows an example of a flowchart for automatically designing a lock power supply system as shown in FIG. 11. First, in step 1201, the logic designer inputs data regarding blocks and connections between blocks, but at this time there is no need to input data regarding the clock power supply system of the precharge circuit. Next, in step 1202, the number of clock input terminals for each block is determined. Note that this determination method will be described later. Subsequently, in step 1204, a clock block consisting of the same number of clock drivers as the sum of the number of terminals of each block is constructed and placed at the center of the chip. In step 1205, lock wiring between blocks is performed.

In step 1206, it is checked whether the result of step 1205 is appropriate, but since step 1203 uses an estimated value as the load of the clock driver, the result of actual automatic wiring may be inappropriate.

If the clock driver load is determined to be appropriate in step 1206, inter-block wiring other than clock wiring is performed in step 1207, and whether or not the wiring is completed is checked in step 1207. If it is completed, automatic LSI design ends. do.

Next, FIG. 13 shows an example of a method for estimating the load of the clock driver in order to perform step 1203 in FIG. 12. 81301 to B1305 are blocks, 1
301 is the center point of the chip, 1304 is block B130
4, the center point Cin is the input capacitance of the clock buffer CB.

The load of the clock driver in the clock block is the sum of the wiring capacitance and the input capacitance of the clock buffer, but since the former cannot be accurately calculated until the LSI design is completed, it is necessary to use an estimated value.

In general, both the clock block and other blocks are sufficiently small compared to the overall area of the chip, and wiring within the chip is done using channels on a virtual grid.
The wiring length is between the chip center point 1301 and the block center point 1
304 can be approximated by the Manhattan distance L x +L y. Therefore, let the number of glock buffers in a block be n
, the average wiring capacitance per unit length is C1, then the estimated clock driver load CLOAD is cLOAD=Cm ・(Lx+Ly)+n-C1
It becomes n.

Next, FIG. 14 shows an example of a flowchart of a method for determining the number of terminals of each block using the value of C_LOAD obtained by the method described above.

Here, it is assumed that the upper limit value of CLOAD to satisfy the specifications regarding the clock skew between blocks is CM^X, and the lower limit value is Cs I N. To achieve these, the 14th
According to the diagram, for each block, first CLO^D is C)I
Check whether it is less than or equal to AX. If this is not satisfied, CLOAD is decreased by increasing the number of clock input terminals in step 1401. This is the 11th
This corresponds to the example of block B1101 in the figure. When the conditions regarding CM^X are satisfied, it is next checked whether CLOAD is greater than or equal to CMIN. If this is not satisfied, CLOAD is increased in step 1402 by sharing the clock driver with the approximate example block. This corresponds to the example of blocks B1103 and B1104 in FIG. Note that at this time, as the values of Lx and Ly, for example, the larger value of both blocks may be used. If CMIN<CLO80 and CM^X are satisfied for all blocks, step 1203 in FIG. 12 ends.

As described above, by applying the present invention, it becomes possible to automatically design clock power supply systems within blocks and between blocks without the logic designer explicitly specifying them.

Next, FIG. 15 is a diagram showing an example in which multiple stages of precharge circuits are connected in series, and FIG. 16 is a diagram showing an example of the input signals, and 1501 to 1506 are precharge circuits, φ is tarok signal, 11501 to 11503
is the input signal, ○1501 is the output signal of 1501, AND
is an AND circuit, N1501. N1504 is NMO5FE
It is T. For example, as discussed in 1988-98827, the source of the FETN 1501 to which a signal is inputted like 1501 is directly grounded, and the clock signal is inputted like 1504 to the precharge circuit. FE
There are two types with TN1504 inserted.

Although the former operates faster than the latter, it is necessary to turn off the FET N1501 whose source is grounded during the precharge operation. Therefore, if 11502 can be at high level during the precharge period as in the example in Fig. 16, an AND is inserted as shown in Fig. 15(a), and i 1503 is forced to be at low level during the same period. It was necessary to do so. As a result, for the input 11502, the number of circuit stages increases and the delay time increases. On the other hand, in FIG. 15(b), 15o1 is replaced with 1504, thereby eliminating the need for AND. 1504 is 150
Although it is slower than 1, since AND is not required, a comparison of the entire series-connected circuit arrays is shown in Figure 15 (b).
The delay time can be shortened from that shown in FIG. However, for a logic designer to instruct the DA to use these two types of circuits for all paths, this would be a very complicated task and could lead to errors. In contrast, in the present invention, (1) the cell library includes two different cells of circuits with the same logic function, such as the combination of 1501 and 1504, and (2) the logic designer inputs only the logic function, and 2. Use DA to select which circuit to allocate.
The above problem can be avoided by this point.

FIG. 17 shows an example of a flowchart for selecting cells. First, the target cell is made into a precharge circuit in which the source of the FET inputting the same type of signal as 1501 is grounded. Next, in step 1701, it is checked whether all the input signals of the FETs whose sources are grounded are the output signals of the precharge circuit. Next, if there is an input signal that does not satisfy this condition, in step 1702, check whether the above condition can be satisfied by swapping the inputs, such as the inputs of AND circuits and OR circuits, whose logical functions are equivalent even if they are swapped. Find out. If the condition is still not satisfied, this cell is replaced in step 1703. By selecting cells in this way, 15
The same type of circuit as 01 is mainly used, and 15 is installed only where necessary.
By using the same type of circuit as 04, high-speed combinations can be selected. Note that FIG. 18 shows a precharge circuit of a different type from the above two types, 11801°i 1802
01801 is an input signal terminal, and 01801 is an output signal terminal. This circuit can also be used in place of the 1501 circuit,
In this case as well, a high-speed logic circuit can be formed.

As described above, by applying the present invention, it is possible to construct and modify cell libraries using precharge circuits in a short period of time, and it is also possible to automatically design LSIs using this, reducing the number of man-hours required for designing high-speed LSIs. can be significantly reduced.

In the above embodiments, several types of precharge circuits using CMO8 and BiCMO3 circuits have been taken as examples, but the present invention can be applied as is to other types of dynamic circuits.

〔Effect of the invention〕

Since the present invention is configured as described above, it produces the effects described below.

1. In a cell using a circuit including a node that operates dynamically inside, wiring can be passed above the cell by covering the cell with a power wiring layer and a ground wiring layer.

2. Construct a cell library by unifying the layout specifications such as the external shape and terminal position of the above cell with those of cells of other circuit types, and this library includes clock buffer cells, and further transmits clock signals along the cell rows. By providing wiring, it is possible to automatically design a block in which cells using a precharge circuit and cells using other circuits are mixed.

3. Place the above blocks within the LSI chip area, and place a clock block in the center of the chip.

By automating the latter design and the wiring between the two, the design period can be shortened.

4. By creating cells by combining basic cells and wiring cells, the time required for creating, adding, modifying, etc. a cell library can be shortened.

5. In a signal path formed by connecting precharge circuits in series, the LSI can be made faster by automatically selecting the optimum combination of circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram and cell layout diagram of one embodiment of the present invention, FIG. 2 is an x-x RfA sectional view of FIG. 1, and FIGS. 3 and 4 are circuit diagrams of other embodiments of the present invention. 5 is a cell layout diagram of the circuit of FIG. 4(b), FIG. 6 is a cell circuit diagram, FIG. 7 is a basic cell of an embodiment of the present invention, and FIG. 8 is a cell layout diagram of the circuit of FIG. 4(b). FIG. 9 is a block layout diagram of an embodiment of the present invention; FIG. 10 is a flowchart of automatic block layout; FIG. 11 is a chim layout diagram of an embodiment of the present invention; FIG. 12 is a diagram of a cell layout of an embodiment of the present invention; is a flowchart of chip automatic layout, FIG. 13 is a diagram showing a clock buffer load estimation method, FIG. 14 is a flowchart of a method of determining the number of clock buffers, and FIG. 15 is a diagram showing an example of a signal path by a precharge circuit. 16th
15 is a diagram showing the input signal waveform of FIG. 15, FIG. 17 is a flowchart for determining an optimal cell combination, and FIG. 18 is a circuit diagram of a precharge circuit using another circuit type. Explanation of symbols 101, 103, 104... 3-man power AND cell. 102...Inverter cell, Cl0L, ClO2°C
301, C401, C901, C902° C903, C
904, C905=・Black 7 signal wiring, 1lo1~1
103,1301~i 304°1401~1405・
...Input signal wiring, VDn...Power supply wiring, GND...
・Ground wiring. 0101～0104,0301,0302゜0401.
0411...Output signal wiring, PIOI~pH5, P2
O3~P304. P401-P404. P411-P4
15. P701~P703-PMOS FET, Nl
0I-N115. N301-N310. N401~N4
08. N411-N419. N701~N704-NM
O8FET, Q301-Q304. Q401. Q411
...NPN type bipolar transistor, 910-92
4.1501-1506...Cell using a precharge circuit, B901-B904...Glock buffer cell, B11o1-B1105...Block, 1101
-... Clock block, 1100... LSI chip,
CBI, CB2...clock buffer, AND...
Ani-do circuit, φ...clock signal. Figure 9 Figure C (α) Figure C Figure 9 (b) Figure 1g Fig. 12 Fig. 11 Fig. 11 (/l) Graduation 13
Zuho 15th (↓) 16th 1st period

Claims (1)

[Claims] 1. A dynamic circuit having unit cells arranged and interconnected using a standard cell method, and in which there is at least one node that can be in a floating state during a logic operation. There is at least one wiring layer that connects the elements in the cell, and there is at least one shield layer having a fixed potential above the wiring layer and covering the node in the cell. 1. A semiconductor integrated circuit device comprising at least one wiring layer disposed in an upper layer to form connections between cells. 2. The semiconductor integrated circuit device according to claim 1, wherein the shield layer forms a power supply wiring and/or a ground wiring. 3. Having at least four wiring layers on the semiconductor substrate,
The first and second layers from the bottom layer are wiring layers for connecting between elements within a cell, the third layer is a shield layer, the third and subsequent layers are wiring layers for connecting between cells, and the fourth layer is 3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is arranged above the shield layer. 4. The semiconductor integrated circuit device according to claim 3, wherein a metal layer for a gate electrode of an FET is used as the wiring layer. 5. A cell library of unit cells arranged and interconnected using the standard cell method includes both cells containing dynamic circuits and cells containing static circuits, and the cells are placed adjacent to each other with a gap between the boundaries of each cell. A semiconductor integrated circuit device characterized in that it can be arranged without causing. 6. A cell library of unit cells arranged and interconnected using the standard cell method includes a cell containing a dynamic circuit and a cell containing a static circuit, and two cells in the cell library are adjacent to each other. When placed, the gap between the boundaries of each cell is either no, a constant amount, or a constant amount and a cell other than the above two cells is inserted into the gap, and this selection is between the adjacent two cells. A semiconductor integrated circuit device characterized by being determined by a combination of cells. 7. In a semiconductor integrated circuit device in which unit cells are connected by mutual wiring layers extending vertically and horizontally at a predetermined pitch on a semiconductor substrate, the unit cells include cells based on dynamic circuits and A clock signal wiring for the dynamic circuit is provided which is parallel to a cell row formed by one-dimensionally arranging unit cells and whose distance from the cell row is a certain amount determined by the unit cell, and A semiconductor integrated circuit device patented in that a cell is provided with a terminal for connection to the clock signal wiring. 8. The semiconductor integrated circuit device according to claim 7, wherein the line width of the clock signal wiring is set wider than that of other cell interconnections. 9. The cell rows are arranged parallel to each other, the area between the cell rows is used as an area for mutual wiring, the clock signal wiring is placed in the area together with other mutual wiring, and the clock signal wiring is connected to the other mutual wiring. 8. The semiconductor integrated circuit device according to claim 7, wherein the semiconductor integrated circuit device is provided at a position closer to the cell row. 10. A cell library of unit cells arranged and interconnected using the standard cell method contains multiple cells that have the same logical capability but differ in at least one of the following: delay time, circuit type, and elements used. A semiconductor integrated circuit device comprising: 11. A cell library of unit cells arranged and interconnected using the standard cell method includes cells that have internal bipolar transistors and cells that have the same logical capability as the cells but do not have internal bipolar transistors. A semiconductor circuit device comprising: 12. At least one of the unit cells arranged and interconnected by the standard cell method has only layout information regarding the first subcell and the interconnections between the elements within the cell, and only the layout information about the elements within the cell. 1. A semiconductor integrated circuit characterized in that the semiconductor integrated circuit is composed of a second subcell having a second subcell. 13. The semiconductor integrated circuit device according to claim 12, wherein the semiconductor integrated circuit device includes at least one of the unit cells using a dynamic circuit. 14. The semiconductor integrated circuit device according to claim 12, wherein the second subcell is commonly used for two or more types of unit cells. 15. The semiconductor integrated circuit device according to claim 12, wherein the first subcell has information on the position of a contact hole in the cell, the position of a through hole, and the position of a wiring connecting these. 16. Claim characterized in that the first subcell has a virtual lattice inside, the contact hole and the through hole are provided on the lattice points of the lattice, and the wiring is provided on the lattice. 16. The semiconductor integrated circuit device according to item 15. 17. The semiconductor integrated circuit device according to claim 12, wherein the second subcell includes one or both of a MOSFET and a bipolar transistor. 18. The semiconductor integrated circuit device according to claim 12, wherein the second subcell includes two or more types of MOSFETs having the same conductivity type and different gate widths. 19. The gate width of the MOSFET whose gate is input with a signal and whose source is grounded is larger than the gate width of a MOSFET whose gate is input with a signal and whose source is not grounded. Semiconductor integrated circuit device. 20. A cell library of unit cells arranged and interconnected using the standard cell method includes at least one type of cell using a dynamic circuit and at least a cell that outputs a clock signal input to the dynamic circuit. A semiconductor integrated circuit device comprising one type. 21. In a semiconductor integrated circuit device formed by connecting unit cells by mutual wiring layers extending vertically and horizontally at a predetermined pitch on a semiconductor substrate, the unit cells include cells using a dynamic circuit. Then, cell rows formed by arranging the unit cells one-dimensionally are arranged parallel to each other to form a block, and the clock input terminals of cells using dynamic circuits are divided into groups, and all cells in the same group are It has clock wires whose terminals are connected to each other, and the load capacitances attached to the clock wires are approximately equal,
A semiconductor integrated circuit device characterized in that each group is provided with the same number of clock buffer cells each having the clock wiring connected to an output terminal. 22. The semiconductor integrated circuit device according to claim 21, wherein the clock wiring is formed by dividing wiring layers laid parallel to the cell rows and connecting them to each other. 23. Claim 2, wherein the clock buffer cells are provided in cell columns, and one clock buffer cell is provided in each group.
1. The semiconductor integrated circuit device according to 1. 24. A semiconductor integrated circuit including a cell using a dynamic circuit in which unit cells are connected by mutual wiring layers extending vertically and horizontally at a predetermined pitch on a semiconductor substrate, and the unit cells require a clock signal. A method for designing a device, the clock signal power supply system being designed based on design information that does not include the clock signal power supply system consisting of circuits and wiring for the clock signal power supply, and arranged and wired together with other unit cells. A design method characterized by: 25. Based on the design information, unit cells are temporarily arranged using the standard cell method, and clock signal power supply wiring is laid in parallel to the cell rows for each cell row including cells using dynamic circuits; The clock signal input terminal of the cell using the dynamic circuit in the cell row is connected to the power supply wiring, and the power supply wiring is divided or combined so that the load capacitance of each power supply wiring is approximately equal. 25. The design method according to claim 24, further comprising allocating the same number of clock driver cells to each cell, inserting the clock driver cells into a cell column to obtain the main arrangement, and wiring connections between the cells based on this arrangement. 26. The design method according to claim 25, characterized in that one clock driver cell is allocated to each of the power supply wirings. 27. On a semiconductor substrate, a logic block including a logic circuit using at least one dynamic circuit and at least one clock buffer that supplies a clock signal to the circuit, and a logic block that supplies a clock signal to the clock buffer. In an LSI chip in which a clock block including at least one clock driver is arranged, all clock buffers on the chip are divided into groups, and the output of one clock driver is sent to the input terminal of the clock buffer in each group. 1. A semiconductor integrated circuit device characterized in that terminals are connected and the load capacitance of each clock driver is set to be substantially equal. 28. A method for designing a semiconductor integrated circuit device including a logic block including at least one logic circuit using a dynamic circuit and at least one clock buffer supplying a clock signal to the circuit, the method comprising: A design method characterized in that the clock block is designed based on design information that does not include information regarding a clock block for supplying clock signal power to a buffer and information regarding connections between both blocks, and is arranged and wired together with the logic block. 29. Temporarily place logic blocks in the LSI chip area based on the design information, and estimate the wiring length between the clock block and the logic block by calculating the Manhattan distance between the center point of the chip and the center point of the logic block for each logic block. value,
A clock block in which all clock buffers are divided into groups so that the sum of the wiring capacitance value calculated from the estimated value and the input capacitance of the clock buffer in the logic block is approximately equal, and the same number of clock drivers as the number of groups are arranged. 29. The design method according to claim 28, wherein the clock block is arranged approximately at the center of the LSI chip to obtain the main arrangement, and connections between the blocks are routed based on this arrangement. 30. A logic input signal and a clock input signal are input, a calculation output signal is output, a precharge operation and a calculation operation are performed alternately according to the clock input signal, and the device includes an internal FET and a node that can be in a floating state during the calculation operation. In a logic circuit consisting of a logic circuit network and a buffer circuit that receives an arithmetic output signal of the logic network and outputs an external output signal in accordance with the input signal, a logic input signal is applied to the gate and the source is fixed. a first type of logic circuit including at least one FET in the logic network connected to a potential; a first FET that does not include the FET and has a logic input signal applied to its gate; An input signal is applied, the source is connected to a fixed potential, and the drain is connected to the first
A second type of logic circuit that includes at least one set of logic circuit networks, a second FET that is connected to the source of the FET and becomes non-conductive during precharge operation, and both types of logic circuits are integrated on the same LSI chip. 1. A semiconductor integrated circuit device comprising: 31. A FET in the former logic network including the first and second types of logic circuits, the source of which is connected to a fixed potential;
31. The semiconductor integrated circuit device according to claim 30, wherein the logic input signal applied to the gate of is an output signal of one of the two logic circuits. 32. FET in the logic circuit network during the precharge operation
31. The semiconductor integrated circuit device according to claim 30, further comprising at least one logic circuit of the second type which is in a conductive state.