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JPH02137324A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

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Publication number
JPH02137324A
JPH02137324A JP29257388A JP29257388A JPH02137324A JP H02137324 A JPH02137324 A JP H02137324A JP 29257388 A JP29257388 A JP 29257388A JP 29257388 A JP29257388 A JP 29257388A JP H02137324 A JPH02137324 A JP H02137324A
Authority
JP
Japan
Prior art keywords
film
region
field
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29257388A
Other languages
Japanese (ja)
Inventor
Toshiro Nakanishi
俊郎 中西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP29257388A priority Critical patent/JPH02137324A/en
Publication of JPH02137324A publication Critical patent/JPH02137324A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔概 要〕 半導体装置の製造方法、特に選択酸化法によるフィール
ド絶縁膜を用いた素子間分離領域の形成方法に関し、 熱酸化によるフィールド絶縁膜の端部近傍の半導体結晶
に加わっている応力を緩和し、転位や結晶欠陥の発生を
抑制して、接合リーク電流の低減を図ることを目的とし
、 選択酸化法により形成されたフィールド絶縁膜〔産業上
の利用分野〕 本発明は半導体装置の製造方法、特に選択酸化法による
フィールド絶縁膜を用いた素子間分離領域の形成方法に
関する。
[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, particularly a method for forming an isolation region between elements using a field insulating film by selective oxidation, semiconductor crystals near the edge of a field insulating film by thermal oxidation are provided. Field insulating film formed by selective oxidation with the aim of reducing junction leakage current by relieving the stress applied to the junction, suppressing the occurrence of dislocations and crystal defects [Industrial application field] This book The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an isolation region between elements using a field insulating film by selective oxidation.

近年、半導体素子の微細化、高集積化に伴って、各素子
領域部ちセルにおける周辺部、即ち素子骨M8i域の端
部及び端部近傍に接する領域の歪みが素子特性に及ぼす
悪影響を無視できなくなってきており、上記領域の歪み
を緩和する必要が生じている。
In recent years, with the miniaturization and high integration of semiconductor devices, the negative effects on device characteristics caused by distortion in the periphery of each device region, that is, in the cell, i.e., the end of the device bone M8i region and the region adjacent to the end, have been ignored. It has become necessary to alleviate the distortion in the above region.

〔従来の技術〕[Conventional technology]

半導体装置に複数形成される半導体素子間の分離を行う
際に、LOCOS法と俗称される選択酸化法による素子
間分離領域の形成方法が多く用いられる。
When performing isolation between a plurality of semiconductor elements formed in a semiconductor device, a method of forming inter-element isolation regions using a selective oxidation method commonly referred to as a LOCOS method is often used.

従来、上記選択酸化による素子量分1itl 91域を
有する半導体装置は、以下に第5図(a)〜(d)を参
照して説明する方法で形成されていた。
Conventionally, a semiconductor device having an element quantity of 1 itl 91 region due to the above-mentioned selective oxidation has been formed by the method described below with reference to FIGS. 5(a) to 5(d).

第5図(a)参照 即ち、半導体基板例えばp型シリコン(Si)基板l上
にパッド用の二酸化シリコン(St(h)膜2を形成し
、その上に窒化シリコン(SiJ4)膜3を形成し、S
i3N4膜3上に素子領域に対応するレジストパターン
4を形成し、このレジストパターン4をマスクにして表
出する5iJ4膜3及びその下部のパッド用Si0g膜
2をエツチング除去し、図示のように素子形成領域上を
覆うパッド用Si0g膜2とSi3N4膜3とレジスト
パターン4との積層パターンを形成し、この積層パター
ンをマスクにしてチャネルカット領域形成用の硼素イオ
ン(B4)をイオン注入する(105はB°注入領域)
Refer to FIG. 5(a). That is, a silicon dioxide (St(h) film 2 for a pad is formed on a semiconductor substrate, for example, a p-type silicon (Si) substrate l, and a silicon nitride (SiJ4) film 3 is formed on it. S, S
A resist pattern 4 corresponding to the device area is formed on the i3N4 film 3, and using this resist pattern 4 as a mask, the exposed 5iJ4 film 3 and the Si0g film 2 for pads below it are removed by etching, and the device is formed as shown in the figure. A laminated pattern of the pad Si0g film 2, the Si3N4 film 3, and the resist pattern 4 covering the formation region is formed, and using this laminated pattern as a mask, boron ions (B4) for forming the channel cut region are ion-implanted (105). is B° injection area)
.

第5図(b)参照 次いで、レジストパターン4を除去した後、5iJa膜
3をマスクにして熱酸化を行い表出するS1基板1面に
厚さ5000〜6000人程度のフィールドSi0g膜
6を形成する。この際フィールドSin、膜6の端部は
5ilNa膜3の下部にバーズビーク状に食い込んで形
成される(6Aはバーズビーク部)。
Refer to FIG. 5(b) Next, after removing the resist pattern 4, thermal oxidation is performed using the 5iJa film 3 as a mask to form a field Si0g film 6 with a thickness of about 5000 to 6000 on the exposed S1 substrate 1 surface. do. At this time, the end of the field Sin and the film 6 is formed by digging into the lower part of the 5ilNa film 3 in a bird's beak shape (6A is a bird's beak part).

また前記B+注入領域105は活性化されてp゛゛チャ
ネルカット領域5になる。
Further, the B+ implanted region 105 is activated and becomes the p channel cut region 5.

なおここでSt基板1におけるフィールド5iOt膜6
のバーズビーク部6Aの近傍領域には、フィールドSi
0g膜6とSi基板1間の応力により結晶の転位や欠陥
りが発生する。
Note that the field 5iOt film 6 on the St substrate 1 is
In the vicinity of the bird's beak portion 6A, there is a field Si.
The stress between the 0g film 6 and the Si substrate 1 causes crystal dislocations and defects.

第5図(C)参照 次いで、上記熱酸化の際5i3Ni膜3の表面に形成さ
れたSiオキシナイトライド(SiON)、5iJn膜
3及びパッド用SiO□膜2をウェットエツチングによ
り除去する。
Refer to FIG. 5(C) Next, the Si oxynitride (SiON), 5iJn film 3 and pad SiO□ film 2 formed on the surface of the 5i3Ni film 3 during the thermal oxidation are removed by wet etching.

これによってフィールドSi0g膜6とその下部のチャ
ネルカット領域5によって画定分離された素子領域7が
形成される。
As a result, an element region 7 defined and separated by the field Si0g film 6 and the channel cut region 5 below the field Si0g film 6 is formed.

第5図(d)参照 次いで、例えばMOS ICにおいてはソース/ドレイ
ン領域となるn゛型領領域8、CCO撮像素子等におい
ては、光電変換領域となるn゛型領領域8、通常通りフ
ィールド5iOt膜6をマスクにし、素子領域7に選択
的に例えば砒素(As”)をイオン注入し、活性化処理
を施すことにより形成されていた。
Refer to FIG. 5(d) Next, for example, in a MOS IC, an n-type region 8 becomes a source/drain region, and in a CCO image sensor, an n-type region 8 becomes a photoelectric conversion region, and as usual, a field 5iOt is formed. It is formed by selectively implanting ions of, for example, arsenic (As'') into the element region 7 using the film 6 as a mask and performing an activation process.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし上記従来の方法によると、フィールド5i02膜
6の端部(エツジ部)及びその近傍、即ちバーズビーク
6A部に接する領域のSi基板1面には、フィールドS
i0g膜6とSi基基板色の熱膨張率の違いにより大き
な応力が加わっているためにその領域のSi基板内に転
位や結晶欠陥りが生じ易く、素子領域7に前記n°型の
光電変換領域8等によるpn接合を形成した際には、前
記フィールドSing膜6端部の近傍領域の空乏層内に
上記転位や結晶欠陥りにより発生するgenerati
on−recombination電流によって、この
接合に逆方向リーク電流が生ずる。
However, according to the above-mentioned conventional method, the field S
Because a large stress is applied due to the difference in thermal expansion coefficient between the i0g film 6 and the Si base substrate color, dislocations and crystal defects are likely to occur in the Si substrate in that region, and the n° type photoelectric conversion occurs in the element region 7. When a pn junction is formed by the region 8 etc., the generation caused by the dislocations and crystal defects in the depletion layer in the vicinity of the end of the field Sing film 6 is
The on-recombination current causes a reverse leakage current in this junction.

そしてこのpn接合の逆方向リークの電流密度は、逆方
向リーク電流密度と素子領域周辺長即ち接合の周辺長と
接合面積の比との関係を示す第6図カーブAから明らか
なように、周辺長と接合面積の比の値が増大するに伴っ
てリーク電流密度は急激に増大する傾向にある。これは
逆方向リーク電流が素子領域周辺部の転位や結晶欠陥に
大きく影響されていることを示し、将来、半導体素子が
更に一層微細化、高集積化されるに伴なって素子領域の
周辺長と接合面積の比の値が一層増大した際には、上記
リーク電流が素子出力のS/N比を大きく劣化せしめ、
例えばcco 盪像素子においては、上記リーク電流に
起因する暗電流不良が発生するという問題を生じていた
The reverse leakage current density of this pn junction is determined by the peripheral The leakage current density tends to increase rapidly as the ratio of length to junction area increases. This indicates that the reverse leakage current is greatly influenced by dislocations and crystal defects around the device region.In the future, as semiconductor devices become even smaller and more highly integrated, When the value of the ratio of the junction area to
For example, in the CCO image element, there has been a problem in that dark current failure occurs due to the above-mentioned leakage current.

そこで本発明は、熱酸化によるフィールド絶縁膜の端部
近傍の半導体結晶に加わっている応力を緩和し、転位や
結晶欠陥の発生を抑制して、接合リーク電流の低減を図
ることを目的とする。
Therefore, an object of the present invention is to alleviate the stress applied to the semiconductor crystal near the edge of the field insulating film due to thermal oxidation, suppress the generation of dislocations and crystal defects, and reduce junction leakage current. .

〔課題を解決するための手段〕[Means to solve the problem]

上記課題は、選択酸化法により形成されたフイールド絶
縁膜の端部及び端部近傍部に接する半導体基板面に選択
的にエネルギー線照射を行う工程を含む本発明による半
導体装置の製造方法によって解決される。
The above-mentioned problem is solved by a method for manufacturing a semiconductor device according to the present invention, which includes a step of selectively irradiating an energy beam to the edge of a field insulating film formed by a selective oxidation method and the semiconductor substrate surface in contact with the edge vicinity. Ru.

〔作 用〕[For production]

第1図は本発明の原理説明図である。 FIG. 1 is a diagram explaining the principle of the present invention.

本発明においては、同図に示されるように、半導体結晶
例えばSt基板1面に選択酸化法によりフィールド絶縁
膜即ち5iO115!6を形成した後、絶縁膜を透過し
、且つ半導体に吸収されるエネルギー線例えばレーザビ
ームLBによってフィールドSin、膜6の端部及び端
部近傍部例えばバーズビーク部6^に接する領域のSi
基板1上を、フィールドSiO□膜6を通し走査してこ
の領域を順次熱酸化時程度の高温に急熱・急冷し、これ
によってこの領域のSi基板1即ちSi結晶の格子定数
をフィールドSi0g膜6と整合している高温の状態の
まま凍結し、絶縁膜と半導体結晶間に生ずる応力を減少
させる。(図中、9はレーザ発生装置、10は集光レン
ズ) これによって、上記フィールド絶縁膜の端部及び端部近
傍部に接する半導体結晶に発生する転位や欠陥を殆ど皆
無にすることができるので、この領域に形成されるpn
接合のリーク電流は大幅に減少して半導体素子の信号出
力のS/N比が増大し、例えばCCD撮像素子等の半導
体装置の暗電流不良は減少する。
In the present invention, as shown in the figure, after a field insulating film, that is, 5iO115!6, is formed on one surface of a semiconductor crystal, for example, an St substrate, by selective oxidation, the energy transmitted through the insulating film and absorbed by the semiconductor is For example, by laser beam LB, the field Sin, the edge of the film 6 and the area near the edge, for example, Si in the region in contact with the bird's beak 6^, are
The substrate 1 is scanned through the field SiO□ film 6, and this region is sequentially rapidly heated and cooled to a high temperature comparable to that during thermal oxidation, thereby changing the lattice constant of the Si substrate 1, that is, the Si crystal in this region, to the field Si0g film. 6, and the stress generated between the insulating film and the semiconductor crystal is reduced. (In the figure, 9 is a laser generator, and 10 is a condenser lens.) This makes it possible to almost completely eliminate dislocations and defects that occur in the semiconductor crystals that are in contact with the ends and the vicinity of the ends of the field insulating film. , pn formed in this region
The leakage current of the junction is significantly reduced, the S/N ratio of the signal output of the semiconductor element is increased, and the dark current defects of the semiconductor device such as a CCD image pickup element are reduced.

(実施例〕 以下本発明を、図示実施例により具体的に説明する。(Example〕 The present invention will be specifically explained below with reference to illustrated embodiments.

第2図は本発明の一実施例の工程平面図、第3図は同実
施例のA−A矢視断面を示す工程断面図、第4図は歪み
の状態を示すラマンスペクトル図である。
FIG. 2 is a process plan view of an embodiment of the present invention, FIG. 3 is a process cross-sectional view taken along the line A-A of the same embodiment, and FIG. 4 is a Raman spectrum diagram showing the state of distortion.

第2図(a)、第3(a)参照 本発明の方法により例えばnチャネル型のMOSトラン
ジスタが多数個配列される半導体装置を形成するに際し
ては、先ず、P−型Si基板1上に熱酸化により厚さ1
000人程度0パッド用5iO1l12を形成した後、
その上にCVO法により厚さ2000人程度0Si3N
a膜3を形成し、5isNa膜3上にフォトプロセスに
より素子領域に対応するレジストパターン4を形成し、
このレジストパターン4をマスクにしてリアクティブイ
オンエツチングを行ってパッド用SiO□膜2と5iJ
La膜3とレジストパターン4よりなり素子領域7を覆
う積層パターンを形成し、この積層パターンをマスクに
して基板1面に硼素(B1)をイオン注入する。(10
5はB1注入領域) 第2図(b)、第3図(ロ)参照 次いで、レジストパターン4を除去した後、5isN4
膜3をマスクにし加湿酸素中で1000°C程度の温度
で熱酸化を行い素子領域7を画定する厚さ5000〜6
000人程度のフィールドSiOx膜6を形成すると同
時に、B゛注入領域105を活性化してp型チャネルカ
ット領域5を形成する。
Refer to FIGS. 2(a) and 3(a) When forming a semiconductor device in which a large number of n-channel MOS transistors are arranged, for example, by the method of the present invention, first, heat is applied onto a P-type Si substrate 1. Thickness 1 due to oxidation
After forming 5iO1l12 for about 000 pads,
On top of that, a thickness of about 2000 Si3N is applied using the CVO method.
A film 3 is formed, and a resist pattern 4 corresponding to the element region is formed on the 5isNa film 3 by a photo process.
Using this resist pattern 4 as a mask, reactive ion etching is performed to form the pad SiO□ film 2 and 5iJ.
A laminated pattern consisting of the La film 3 and the resist pattern 4 covering the element region 7 is formed, and boron (B1) ions are implanted into the surface of the substrate 1 using this laminated pattern as a mask. (10
5 is the B1 implantation region) See FIGS. 2(b) and 3(b). Next, after removing the resist pattern 4, 5isN4
Using the film 3 as a mask, thermal oxidation is performed in humidified oxygen at a temperature of about 1000°C to a thickness of 5000 to 6 to define the element region 7.
At the same time as forming the field SiOx film 6 of about 1,000 yen, the B implanted region 105 is activated to form the p-type channel cut region 5.

なおここでSi基板lにおけるフィールド5ift膜6
のバーズビーク部6Aの近傍領域には、フィールドSi
0g膜6とSt基板1間の応力により結晶の転位や欠陥
りが発生する。
Note that here, the field 5ift film 6 on the Si substrate l
In the vicinity of the bird's beak portion 6A, there is a field Si.
The stress between the 0g film 6 and the St substrate 1 causes crystal dislocations and defects.

第2図(C)、第3図(C)参照 次いで、上記熱酸化の際表面に形成されたSiオキシナ
イトライド(SiON)を含む5iJ4膜3を熱燐酸処
理で除去し、パッド用Si0g膜2を弗酸系液によりエ
ツチング除去して、フィールドSiOx膜6とその下部
のチャネルカット領域5によって画定分離された素子領
域7を形成する。ここで、フィールドSiO□膜6のバ
ーズビーク部6Aに接する領域には前記転位や欠陥りが
存在する。
Refer to FIG. 2(C) and FIG. 3(C) Next, the 5iJ4 film 3 containing Si oxynitride (SiON) formed on the surface during the above thermal oxidation is removed by hot phosphoric acid treatment, and the Si0g film for the pad is removed. 2 is removed by etching with a hydrofluoric acid solution to form an element region 7 defined and separated by the field SiOx film 6 and the channel cut region 5 below it. Here, the dislocations and defects are present in the region of the field SiO□ film 6 that is in contact with the bird's beak portion 6A.

第2図(d)、第3図(d)参照 次いで本発明の方法においては、上記転位や欠陥りを除
去するために、レーザ発生装置9で発生し集光レンズ1
0で所定のビームスポット径に集光したCWレーザ光L
Bにより、基板1全面上のフィールドSiO□膜6の端
部即ちバーズビーク部6八に接するSii板1面を、矢
印mに示すようにX方向、X方向に図示しないxyステ
ージを用いて順次照射し、フィールドSiO□膜6形成
時の温度に近い高温に急熱し且つ急冷して行き、この領
域のSi結晶の格子定数を5in2膜の格子定数に近い
値に凍結する。
Refer to FIG. 2(d) and FIG. 3(d) Next, in the method of the present invention, in order to remove the above-mentioned dislocations and defects, the dislocations and defects generated in the laser generator 9 and the condensing lens 1 are removed.
CW laser beam L focused to a predetermined beam spot diameter at 0
By B, the edge of the field SiO□ film 6 on the entire surface of the substrate 1, that is, the surface of the Sii plate in contact with the bird's beak portion 68 is sequentially irradiated in the X direction and the X direction using an xy stage (not shown) as shown by the arrow m. Then, it is rapidly heated to a high temperature close to the temperature at which the field SiO□ film 6 was formed and rapidly cooled, thereby freezing the lattice constant of the Si crystal in this region to a value close to the lattice constant of the 5in2 film.

なお、上記C−レーザの照射に際し、レーザには波長4
88nmのアルゴン(Ar)レーザを用い、ビームスポ
ット径は10μmφに集光した。またレーザ照射部のパ
ワー密度は10’W/cm”程度とし、走査速度は3c
m/秒に制御した。照射により得られるエネルギー密度
は数J/cm”程度となる。
In addition, when irradiating with the above C-laser, the laser has a wavelength of 4.
An 88 nm argon (Ar) laser was used, and the beam spot diameter was focused to 10 μmφ. The power density of the laser irradiation part is about 10'W/cm'', and the scanning speed is 3c.
The speed was controlled at m/sec. The energy density obtained by irradiation is approximately several J/cm''.

上記レーザ照射の結果、第4図に示すように、フィール
ドSin、膜6の端部近傍のSi結晶のラマンシフトが
、フィールドSing膜6形成後の値520.0/cm
伺から通常のSt基板の値520.5/cl’に近い値
の520.3/cm−’にまで回復し、応力に換算する
と1.lX109dyn/cm2から4.6xlO” 
dyn/cm”にまで緩和される。従って上記レーザ照
射後にフィールドSin、膜6の端部近傍に発生する転
位及び欠陥は殆ど皆無になる。
As a result of the above laser irradiation, as shown in FIG.
The stress recovered to 520.3/cm-', which is close to the value of the normal St substrate of 520.5/cl', and when converted to stress, the stress was 1. lX109dyn/cm2 to 4.6xlO”
dyn/cm''. Therefore, after the above laser irradiation, there are almost no dislocations or defects generated in the field Sin or near the end of the film 6.

なお、このエネルギー線照射には上記C−レーザに限ら
ずパルスレーザを用いてもよく、また電子線パルス、或
いは電子線走査を用いてもよい。
Note that this energy beam irradiation is not limited to the above-mentioned C-laser, and a pulsed laser may be used, and electron beam pulses or electron beam scanning may also be used.

第2図(e)、第3図(e)参照 以後、通常の方法により各素子領域7上にゲート酸化膜
11を形成し、次いで各素子領域7上に連通ずるゲート
電極12を形成し、ゲート電極12をマスクにしイオン
注入により各素子領域にソース/ドレイン領域13.1
4を形成し、図示しないソース/ドレイン配線の形成等
がなされて、基板上に多数のMOS )ランジスタが配
列された半導体装置が完成する。
After referring to FIG. 2(e) and FIG. 3(e), a gate oxide film 11 is formed on each element region 7 by a normal method, and then a communicating gate electrode 12 is formed on each element region 7, Source/drain regions 13.1 are implanted into each device region by ion implantation using the gate electrode 12 as a mask.
4 and forming source/drain wiring (not shown), etc., to complete a semiconductor device in which a large number of MOS transistors are arranged on the substrate.

なお前述したようにフィールドSiO2膜6の端部近傍
のSi基板1内に発生する転位及び欠陥は殆ど皆無にな
るので、フィールドSi0g膜6の端部に接して形成さ
れるソース/ドレイン領域13.14の接合リークは大
幅に減少し、これらトランジスタの信号出力のS/N比
が向上する。またCOD等においては暗電流の低減が図
れる。
As mentioned above, since almost no dislocations or defects occur in the Si substrate 1 near the edge of the field SiO2 film 6, the source/drain regions 13. The junction leakage of 14 is significantly reduced and the signal-to-noise ratio of the signal output of these transistors is improved. In addition, dark current can be reduced in COD and the like.

〔発明の効果〕〔Effect of the invention〕

以上説明のように本発明によれば、選択酸化により形成
されるフィールド絶縁膜によって素子領域が画定される
半導体装置において、フィールド絶縁膜の端部及び端部
近傍部に接する半導体結晶に発生する転位や欠陥を殆ど
皆無にすることができるので、この領域に形成されるp
n接合のリーク電流は大幅に減少し、半導体素子の信号
出力のS/N比の増大が図れ、例えばCCD等の半導体
装置の暗電流不良が減少する。
As described above, according to the present invention, in a semiconductor device in which an element region is defined by a field insulating film formed by selective oxidation, dislocations occur in the semiconductor crystal in contact with the edge and the vicinity of the edge of the field insulating film. Since it is possible to eliminate almost all defects and defects, the p
The leakage current of the n-junction is significantly reduced, the S/N ratio of the signal output of the semiconductor element is increased, and dark current defects in semiconductor devices such as CCDs are reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理説明図、 第2図(a)〜(e)は本発明の一実施例を示す工程平
面図、 第3図(a)〜(e)は同実施例のA−A矢視断面を示
す工程断面図、 第4図はSi結晶の歪みの状態を示すラマンスペクトル
図、 第5図(a)〜(d)は従来の方法の工程断面図第6図
は逆方向リーク電流と接合の周辺長/接合面積との関係
図 である。 図において、 1はP型Si基板、    2はパッド用SiO□膜、
3は5isNa膜、     4はレジストパターン、
5はチャネルカット領域、 6はフィールドSiO2膜、 6^はバーズビーク部、  7は素子領域、8はn°型
光電変換領域、 9はレーザ発生装置、 10は集光レンズ、11はゲー
ト酸化膜、  12はゲート電極、13.14はn+型
ソース/ドレイン領域、105はB9注入領域、 LB
はレーザビーム、Dは転位や欠陥 mはレーザビーム走査方向矢印 を示す。 2本、2 e月/l、9i、qt 説aR図第 1!!
l L/7>仄責」5.を、フラー1Tクマンス<yhル図
見 4  図 木克臼月の一史党イダ・]の工程平面図第Z図(イの2
) 本光明の一友扼イ列の工程平面図 第2図(勤1) 本発明司−突記e]f)工程町[有]図男 図 (予/)j) 5ネ、全gFJI/I−実方色争]めニオLぼα面図基 図 とイシ2) !yc米n方鷹nユ」呈、粕−面図 基 り 凹
Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 (a) to (e) is a process plan view showing one embodiment of the present invention, and Fig. 3 (a) to (e) is A of the same embodiment. -A process cross-sectional view showing the cross section in the direction of arrow A. Figure 4 is a Raman spectrum diagram showing the state of distortion of the Si crystal. Figures 5 (a) to (d) are process cross-sectional views of the conventional method. Figure 6 is the reverse. FIG. 3 is a relationship diagram between directional leakage current and junction peripheral length/junction area. In the figure, 1 is a P-type Si substrate, 2 is a pad SiO□ film,
3 is a 5isNa film, 4 is a resist pattern,
5 is a channel cut region, 6 is a field SiO2 film, 6 is a bird's beak portion, 7 is an element region, 8 is an n° type photoelectric conversion region, 9 is a laser generator, 10 is a condenser lens, 11 is a gate oxide film, 12 is a gate electrode, 13.14 is an n+ type source/drain region, 105 is a B9 injection region, LB
indicates a laser beam, D indicates a dislocation or defect, and m indicates a laser beam scanning direction arrow. 2 books, 2 e month/l, 9 i, qt theory aR diagram 1st! !
l L/7 > Responsibility” 5. , the process plan of Fuller 1
) Plan of the process of Honkomyo's Ichitomo Ai line Figure 2 (Work 1) Inventor's report e] f) Process town [Y] Zuo map (Project/) j) 5, all gFJI/ I-Real Color Conflict] Menio Lbo Alpha Plane Base Map and Ishi 2)! yc rice n direction hawk n yu” presentation, lees-side map based concave

Claims (1)

【特許請求の範囲】[Claims] 選択酸化法により形成されたフィールド絶縁膜の端部及
び端部近傍部に接する半導体基板面に選択的にエネルギ
ー線照射を行う工程を含むことを特徴とする半導体装置
の製造方法。
1. A method of manufacturing a semiconductor device, comprising the step of selectively irradiating an energy beam to an end of a field insulating film formed by a selective oxidation method and a surface of a semiconductor substrate in contact with the vicinity of the end.
JP29257388A 1988-11-18 1988-11-18 Manufacturing method of semiconductor device Pending JPH02137324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29257388A JPH02137324A (en) 1988-11-18 1988-11-18 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29257388A JPH02137324A (en) 1988-11-18 1988-11-18 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02137324A true JPH02137324A (en) 1990-05-25

Family

ID=17783523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29257388A Pending JPH02137324A (en) 1988-11-18 1988-11-18 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02137324A (en)

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