JPH02155239A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a MOS transistor of a semiconductor device.

[Conventional technology]

As semiconductor devices become smaller and more highly integrated, MOS transistors are also becoming smaller. However, miniaturization of element dimensions has led to the problem of deterioration of characteristics due to hot carriers.

To solve this problem, LDD (Light 1yD
A structure called "opened drain" has been proposed, and a structure that is a further improvement of this LDD is published in the following document. (R, IZAWA.

T, KURESE, TAKEDA, 'THE IMP
ACT OF GATE-DRAIN 0VER
LAPPED LDD (GOLD) FORDE
EP SUBMICRON VLSI'S'', IE
DM Tech, Dig, pp38-41 19
87,) The manufacturing method according to this document will be explained using FIG. In FIG. 3, 301 is a p-type semiconductor substrate, 302
303 is a gate oxide film, 303 is a polycrystalline silicon film, 304 is a natural oxide film, 305 is a polycrystalline silicon film, 306 is an oxide film, 307 is an n-type impurity layer with a thin impurity concentration, 308 is a side wall made of an oxide film, 309 310 is an n-type impurity layer with a high impurity concentration, and 310 is an oxide film.

First, a gate oxide film 302 is formed by thermally oxidizing a p-type semiconductor substrate 301. Next, after forming a thin polycrystalline silicon film 303, it is left in the air to form a natural oxide film 304 of 5 to 10 layers. Next, a polycrystalline silicon film 305
, an oxide film 306 is sequentially formed by the CVD method. Next, as shown in FIG. 3(a), unnecessary portions of the oxide film 306 are removed by photolithography. Next, as shown in FIG. 3(b), the oxide film 3
By performing dry etching using 06 as a mask, unnecessary portions of the polycrystalline silicon film 305 are removed.

Next, an n-type impurity layer 307 is formed by ion-implanting phosphorus, which is an n-type impurity, using the oxide film 306 and the polycrystalline silicon film 305 as a mask. Next, after forming an oxide film 308 by the CVD method, dry etching is performed to form a side wall 3 made of the oxide film as shown in FIG. 3(C).
08 is formed.

Next, as shown in Figure 3(d), the temperature is 800°C in a wet atmosphere.
An oxide film 310 is formed by oxidizing. Next, an n-type impurity layer 309 is formed by ion-implanting arsenic, which is an n-type impurity, using the gate electrodes 303 and 305, the oxide film 306, and the side walls 308 as masks.

[Problem to be solved by the invention]

However, in the prior art described above, the characteristics of the MOS transistor vary greatly depending on the lateral length of the oxide film 310, but this lateral length depends on the thickness of the polycrystalline silicon film 303 and the Dimensional control is difficult because it is determined by oxidation conditions, especially when the gate length of MOS transistors is miniaturized to the submicron region.
There is a problem in that transistor characteristics change significantly due to dimensional variations in the lateral length of the oxide film 310. Furthermore, in the prior art described above, oxidation [308
When forming the oxide film 3 on the gate electrodes 303 and 305
06 has an overhang, as shown in Figure 4, the coverage of the oxide film in this area is poor and the air/Fi
1411 will be created. As a result, there is a problem that the moisture resistance of the transistor deteriorates.

Furthermore, in the conventional technology described above, when a transistor is formed, the film thickness on the gate is the total thickness of the gate oxide film 302, polycrystalline silicon film 303, natural oxide film 304, polycrystalline silicon film 305, and oxide film 306. If a wiring layer is further formed on the gate electrode because of the increased thickness, if the wiring layer crosses the gate electrode, the step will become large, causing disconnection in the wiring layer on the gate electrode, or causing the wiring layer on the gate electrode to become thicker. When forming layers, wiring shorts may occur due to etching residue.

The present invention is intended to solve these problems, and its purpose is to provide a transistor with less variation in characteristics due to variations in transistor gate length, and with good moisture resistance.
The goal is to provide a semiconductor device with no disconnections or short circuits in the wiring layer above the gate electrode.

[Means to solve the problem]

(1) The method for manufacturing a semiconductor device of the present invention includes the steps of forming a first insulating film on a semiconductor substrate of a first conductivity type;
a step of forming a gate electrode of an MO8 type transistor using a first conductive film on an insulating film of the semiconductor substrate; a step of introducing an impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate using the gate electrode as a mask; forming a second insulating film on the substrate and the gate electrode;
forming a second conductive film on the insulating film, and then forming a sidewall of the second conductive film on the gate electrode by performing anisotropic ion etching; a step of etching the second insulating film above; a step of forming a third conductive film on the semiconductor substrate, the gate electrode, and the sidewall; and a step of etching the third conductive film by thermal oxidation. It is characterized by comprising a step of oxidizing the part.

(2) The method for manufacturing a semiconductor device of the present invention includes the steps of forming a first insulating film on a semiconductor substrate of a first conductivity type;
forming a gate electrode of an MO8 type transistor using a first conductive film on an insulating film; forming a second insulating film on the semiconductor substrate and the gate electrode; a step of introducing an impurity of a conductivity type opposite to that of the semiconductor substrate into the substrate;
forming a second conductive film on the insulating film, and then forming a sidewall of the second conductive film on the gate electrode by performing anisotropic ion etching; a step of etching the second insulating film above, a step of forming a third conductive film on the semiconductor substrate, the gate electrode, and the sidewall; and a step of partially etching the third conductive film by thermal oxidation. It is characterized by consisting of an oxidizing step.

〔Example〕

An embodiment of the present invention will be described in detail as a first embodiment with reference to FIG. First, as shown in FIG. 1(a), a first conductivity type semiconductor substrate, here a p-type silicon substrate 101 with boron diffused therein, is oxidized at 1000° C. in an oxidizing atmosphere to form a gate oxide film 102 of 150 layers. Then, CVD
2,500 to 8,000 polycrystalline silicon films are formed by a method, and unnecessary portions of the polycrystalline silicon films are removed by photolithography to form a gate electrode 103. Next, as shown in FIG. 1(b), using the gate electrode 103 as a mask, an n-type impurity, here phosphorus, is ion-implanted at a dose of Ix1012 to 1x10110l4' and an accelerating voltage of 40KeV to 150KeV. A concentrated n-type impurity region 104 is formed. Next, as shown in FIG. 1(C), a silicon oxide film 105 having a length of 150 mm is formed by the CVD method. Next, Figure 1 (
As shown in d), a polycrystalline silicon film with a thickness of 300 mm is deposited by the CVD method.
After forming 0 to 8,000 people, anisotropic ion etching is performed to form a sidewall 106 of a polycrystalline silicon film. Next, as shown in FIG. 1(e), anisotropic ion etching is performed to remove the oxide film on the gate electrode, the oxide film on the silicon substrate, and a part of the oxide film between the gate electrode and the sidewalls. . Next, as shown in Figure 1(f), CVD
When a polycrystalline silicon film with a thickness of 300 Å is formed by the method, a structure is formed in which the groove of the oxide film between the gate electrode and the sidewall is filled with polycrystalline silicon 107. Next, Figure 1 (g)
A part of the polycrystalline silicon 107 is converted into a silicon oxide film 108 by oxidizing the polycrystalline silicon 107 at 850° C. in a wet atmosphere. Next, as shown in FIG. 1(h), using the gate electrode 103 and sidewalls 106 as masks, an n-type impurity, here arsenic, is ionized at a dose m of 1 x 1015 to 1 x 1016 cm-2 and an accelerating voltage of 60 KeV to 180 KeV. A high concentration n-type impurity layer 109 is formed by implantation.

In addition to the first embodiment, a semiconductor device having similar effects can be formed according to the following embodiments. This will be explained as a second embodiment using FIG. 2.

First, the formation is performed in the same manner as in the first embodiment until the gate electrode is formed as shown in FIG. 2(a). Next, as shown in FIG. 2(b), a silicon oxide film 205 of 1 to 5
Form people. Next, as shown in FIG. 2(c), the gate electrode 10
Using 3 as a mask, the n-type impurity, here phosphorus, is 1 x 1012 ~
At a dose of 1 x 10!4 cm-2, 40 KeV ~ 15
A low concentration n-type impurity region 204 is formed by ion implantation at an acceleration voltage of 0 KeV. The subsequent steps from FIG. 2(d) to FIG. 2(h) are formed in the same manner as in the first embodiment.

In the MOS transistor formed by the above process, the sidewall 106 on the low concentration n-type impurity layer 104 is connected to the gate electrode 103, so when a voltage is applied to the gate, a voltage is also applied to the sidewall 106. This electric field lowers the resistance of the lightly doped n-type impurity layer 104, and the lateral electric field within the lightly doped n-type impurity layer 104 is relaxed. As a result, the drain current of the transistor increases, and deterioration of conductance due to hot carriers can be avoided.

Furthermore, according to this embodiment, the characteristics of the MOS transistor vary greatly depending on the width of the sidewall 106 on the lightly doped n-type impurity layer 104;
By changing the thickness of the polycrystalline silicon film and the thickness of the polycrystalline silicon film when forming the sidewall 106, it is possible to easily and accurately control the thickness of the polycrystalline silicon film. For example, if the sidewall 106 is formed with the thickness of the gate electrode 103 being 4000 mm and the thickness of the polycrystalline silicon film used to form the side wall 106 being 5000 mm, the width thereof will be approximately 0.25 μm. In addition, the intra-wafer to wafer variations in the sidewalls 106 are within ±0.03 μm, and can be controlled with high precision and with little variation.

Further, in this embodiment, since there is no overhang, no cavity is formed and the moisture resistance of the transistor is not deteriorated.

In addition, in this example, the film thickness on the gate is 1
02, the gate electrode 103, and the oxide film 108. Therefore, if a wiring layer is further formed on the gate electrode, even if the wiring layer crosses the gate electrode, the difference in level is small, so There will be no disconnections in the wiring layer, and no wiring shorts due to etching residue when forming the wiring layer on the gate electrode.

In this example, the gate electrode was formed of polycrystalline silicon, but it may also be formed of polycide made of polycrystalline silicon and a high-melting point metal such as titanium, tungsten, or molybdenum, or of high-melting point metal silicide. .

Further, in this example, phosphorus was used as the n-type impurity in the low concentration n-type impurity layer, but arsenic or antimony may also be used, or a combination of these impurities such as phosphorus and arsenic may be introduced. . Furthermore, in this example, arsenic was used as the n-type impurity in the high concentration n-type impurity layer, but phosphorus or antimony may also be used, or a combination of these impurities such as phosphorus and arsenic may be introduced. . Furthermore, although boron was used as an impurity for the p-type semiconductor substrate in this embodiment, gallium, aluminum, or indium may also be used.

In this embodiment, an N-channel MO8) transistor has been described, but it goes without saying that the same effect can be obtained even when applied to a P-channel MOS transistor.

〔Effect of the invention〕

According to the present invention, the drain current of a MOS transistor increases, and deterioration of conductance due to hot carriers can be avoided.

Further, according to the present invention, the width of the sidewall connected to the gate electrode, which influences the characteristics of the MOS transistor, can be processed with high precision and with less variation, so that variations in the drain current and conductance of the MOS transistor can be reduced.

Further, according to the present invention, the moisture resistance of the MOS transistor does not deteriorate.

Further, according to the present invention, disconnections and short circuits in the wiring layer on the gate electrode are reduced.

From the above, the method for manufacturing a semiconductor device according to the present invention has the advantage of being able to provide a high-speed, high-quality, high-yield semiconductor device.

[Brief explanation of the drawing]

FIGS. 1(a) to (h) and FIGS. 2(a) to (h) are step-by-step cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS. 3(a) to 3(d) are process-order sectional views showing an example of a conventional semiconductor device. FIG. 4 is a sectional view of a conventional semiconductor device. 109.209.309 . . . Highly concentrated impurity layer 101 of the conductivity type opposite to that of the silicon substrate. 102. 103. 104. 105. 08.31 106. 201.301 ... Silicon substrate of first conductivity type 202.302 ... Gate oxide film 203.303.305 ... Gate electrode 204.307 ... Low concentration impurity layer of conductivity type opposite to the silicon substrate 205.108.208 .306.3 0.Silicon oxide film 206.107.207...Polycrystalline silicon film Applicant Seiko Epson Co., Ltd. Agent Patent attorney Masayoshi Kamiyanagi (and 1 other person) Figure (Working Figure 1 (b) 2 Figure (α) Figure 2 (b) Figure (this) Figure 1 (d) Figure 2 (c) Figure 2 (Force Figure 1 (e) Figure 1 rh Figure 2 (e) Figure 2 (f) Figure 2 (9) Figure 2 (h) -1 loco m Figure 3 (It) Figure 3 (b) Figure 3 (C) Figure 3 (d) Figure 4

Claims (2)

[Claims] (1) Forming a first insulating film on a semiconductor substrate of a first conductivity type, and forming a first conductive film on the first insulating film to form an M
a step of forming a gate electrode of an OS type transistor; a step of introducing an impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate using the gate electrode as a mask; and a step of forming a second insulating film on the semiconductor substrate and the gate electrode. and forming a sidewall of the second conductive film on the gate electrode by performing anisotropic ion etching after forming a second conductive film on the second insulating film. , etching the second insulating film on the semiconductor substrate and the gate electrode, forming a third conductive film on the semiconductor substrate, the gate electrode, and the sidewalls, and thermal oxidation. A method of manufacturing a semiconductor device, comprising the step of oxidizing a part of the third conductive film. (2) Forming a first insulating film on a semiconductor substrate of a first conductivity type, and forming a first conductive film on the first insulating film to form an M
a step of forming a gate electrode of an OS type transistor; a step of forming a second insulating film on the semiconductor substrate and the gate electrode; and an impurity having a conductivity type opposite to that of the semiconductor substrate on the semiconductor substrate using the gate electrode as a mask. and forming a sidewall of the second conductive film on the gate electrode by forming a second conductive film on the second insulating film and performing anisotropic ion etching. a step of etching the second insulating film on the semiconductor substrate and the gate electrode; a step of forming a third conductive film on the semiconductor substrate, the gate electrode, and the sidewall; Third
1. A method of manufacturing a semiconductor device, comprising a step of oxidizing a part of a conductive film.