JPH02166761A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a latch-up, to reduce the area of an element and to improve the degree of integration by forming a trench in depth reaching a semiconductor substrate to a well shaped to the semiconductor substrate and separating the well into a plurality of mutually insulated wells. CONSTITUTION:A ring-shaped trench 6 is formed in an N-well 2 between a P-type diffused layer 3 and an N-type diffused layer 5. The trench 6 is deeper than the well 2 and filled with insulating material so that it serves as an insulator. The N-well 2 is separated into two wells 2a and 2b. The well 2a contains the P-type diffused layer 3 while the well 2b does not. According to the constitution, electrons being diffused in a P-type semiconductor substrate 1 are absorbed by the N-well 2b, and the number of carriers introduced to the N-well 2b is decreased, thus preventing a latch-up. Consequently, the latch-up can be obviated by the width of 1-2mum of the trench 6, and the latch-up can be prevented by an area remarkably smaller than width of 20mum required in a conventional guard ring, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device having a complementary MO3 transistor structure (CMO3 structure), and particularly to a semiconductor device that prevents parasitic silica operation.

[Conventional technology]

Conventionally, in order to prevent parasitic silicon risk operation (hereinafter referred to as latch-up) in a CMO3 structure semiconductor device,
The structure shown in FIGS. 5, 6, and 7 is adopted. FIG. 5 is an overall view of the semiconductor chip 11, in which a guard ring area 13 is provided to separate an input/output area 12 where an extended fltN connected to an external terminal exists and an internal area 14 having a logic function. . Figure 6 shows the guard ring area 13.
7 is an enlarged vertical sectional view taken along the line C--C in FIG. 5, showing the vicinity thereof, and FIG. 7 is an equivalent circuit thereof. In these figures,
Ql, Q3 are P-channel type MO3 transistors, Q2.
Q4 is an N-channel MO3 transistor, and these constitute a two-stage inverter having a CMO3 structure.

Next, the latch-up prevention mechanism will be explained using FIG. 8. Note that FIG. 8 is an enlarged view of a part of FIG. 6, and corresponding symbols are assigned to each part.

In this example, an N-type island region (hereinafter referred to as a well) 22 is provided on a P-type semiconductor substrate 21, and a P-type diffusion layer 23. An N-type diffusion layer 24 and the like are formed to constitute a P-channel MOS transistor Q3. Also, this N well 2
An N well 25 is provided adjacent to 2 and is connected to a power source through an N type diffusion layer 26. In addition, 28 is an N-channel MO
3I - N type diffusion layer constituting transistor Q4, 29 is G
This is an ND-connected P-type diffusion layer.

At this time, consider the case where electrons are injected as minority carriers from the N-type diffusion layer 27 connected to the external terminal.

First, when the potential of the external terminal becomes lower than GND due to noise or the like, the junction between the N-type diffusion layer 27 and the P-type semiconductor substrate 21 is biased in the forward direction, and electrons are injected into the P-type semiconductor substrate 21 as a minority gear. These electrons move through the P-type semiconductor substrate 21 by diffusion, but are eventually neutralized by recombination or
．． 22 and act as a majority carrier.

Next, the electrons entering the N-well 22 lower the potential of the N-well near the P-type diffusion layer 23, and this time, the junction between the P-type diffusion layer 23 and the N-well 22 is biased in the forward direction. Holes are injected from the P-type diffusion layer 23 into the N-well 22, and the injected holes pass through the N-well 22, enter the P-type semiconductor substrate 21, and further penetrate into the nearby P-type diffusion layer 2.
Going into 9th.

As a result, the potential of the semiconductor substrate near the N-type diffusion layer 28 increases, the junction between the N-type diffusion layer 28 and the P-type semiconductor substrate 21 is biased in the forward direction, and electrons are injected into the P-type semiconductor substrate 21. Eventually, a positive feedback loop is created and it becomes a latch amplifier.

Here, if the N-well 25 exists as a guard ring, a considerable amount of the electrons injected from the N-type diffusion layer 27 will be absorbed by the N-well 25. Therefore, assuming that a latch amplifier occurs when a certain amount of electrons are injected into the N well 22, and 50% of the electrons are absorbed in the N well 25, when a latch amplifier occurs, the latch amplifier is injected from the external terminal. The number of electrons is approximately doubled by providing the guard ring. In other words, there is twice the latch-up tolerance.

[Problem to be solved by the invention]

By the way, so far we have explained the case where electrons are injected from the outside/terminal, but due to the short channel of the gate of MOS transistors in recent years, during normal operation, holes are caused by the collision electric disturbance phenomenon due to the high electric field between the source and drain.・Electrons are generated and the latch amplifier caused by this is causing problems.

To solve this problem, if the latch-up countermeasure using the N-well guard ring described above is used as is, the
It is configured as shown in FIG. FIG. 9 is a plan view of a part of the element, and FIG. 10 is a slightly enlarged vertical sectional view taken along the line DD.

That is, an N well 32 is provided in a P type semiconductor substrate 31, and a P type diffusion layer 32. An N-type diffusion layer 33 is formed. Then, an N well 35 as a guard ring is formed around this N well 32 and connected to a power supply through an N type diffusion layer 36.

According to this configuration, the guard ring of the N well 35 can increase the latch-up resistance as shown in FIG. However, in this configuration, it is necessary to arrange the N-well 35 around the N-well 32 with appropriate isolation.
A space of about 20 μm is usually required for this purpose. This causes a problem in that the area required for the element increases by this space, and the degree of integration of the semiconductor device decreases.

An object of the present invention is to provide a semiconductor device that can not only prevent latch-up but also reduce the element area and increase the degree of integration.

[Means to solve the problem]

In the semiconductor device of the present invention, a groove deep enough to reach the semiconductor substrate is formed in a well formed in a semiconductor substrate, and the groove separates the well into a plurality of mutually insulated wells.

[Effect]

In the above configuration, there is no need to provide a guard ring around the well, and there is also no need to provide a space between the guard ring and the well, reducing the area of the device.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Fig. 1 is a plan view of the first embodiment of the present invention, and Fig. 2 is its A.
- It is a longitudinal cross-sectional view along the A line. In the figure, ■ is a P semiconductor substrate, 2 is an N well, 3 is a P diffusion layer connected to a power supply, and 4 and 5 are N diffusion layers connected to a power supply. here,
N well 5 between the P diffusion layer 3 and the N diffusion layer 5
A ring-shaped groove 6 is formed therein, deeper than the N-well 5.

An insulator is buried in this trench 6 to maintain insulation, and as a result, at least the N well 2 is separated into a well 2a containing the P-type diffusion layer 3 and a well 2b not containing it. Become.

According to this configuration, the N well 2b absorbs electrons diffusing in the P semiconductor substrate 1, and latch-up can be prevented by reducing the number of carriers entering the N well 2b.

Therefore, in this structure, the width of the groove 6 is 1 to 2 μm.
Width 2 that can be achieved with m and is required for conventional guard rings, etc.
Latch-up can be prevented with a much smaller area than 0 μm.

FIG. 3 is a plan view of the second embodiment of the present invention, and FIG. 4 is its B.
- It is a longitudinal cross-sectional view along the B line. Note that parts equivalent to those in the first embodiment are given the same reference numerals.

In this embodiment, there is an N well 2a in which a P type diffusion layer 3 connected to a power supply exists, and an N well 2a as a guard ring.
b are insulated and separated by a groove 7. In this case, the groove 7 is formed linearly along one side of the N-well 2, thereby enclosing only the inner four sides of the N-well 2.

This embodiment is used when it is clear where minority carriers are likely to occur, for example, when considering only the direction where a transistor with a large channel width is located. In this embodiment as well, latch-up can be prevented with a small area as in the first embodiment.

Although the case where an N-well is formed on a P-type semiconductor substrate has been described above, it is obvious that the same effect can be expected when a P-well is formed on an N-type semiconductor substrate.

〔Effect of the invention〕

As explained above, according to the present invention, a groove deep enough to reach the semiconductor substrate is formed in a well, and the groove separates the well into a plurality of mutually insulated wells, so a guard ring is placed around the well. There is also no need to provide a space for this purpose, making it possible to prevent latch-up with a small area and achieving high integration.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a plan view of a first embodiment of the present invention, FIG. 2 is a longitudinal sectional view taken along line A-A in FIG. 1, and FIG. 3 is a second embodiment of the present invention. A plan view of the example, FIG. 4 is a vertical cross-sectional view taken along the line B-B in FIG. 3, FIG. 5 is an overall plan view of a conventional semiconductor chip with latch-up countermeasures, and FIG. An enlarged vertical cross-sectional view taken along line C-C, FIG. 7 is an equivalent circuit of FIG. 6, and FIG. 8 schematically shows a part of FIG. 9 is a plan view of a part of the element when the conventional latch-up countermeasure is applied to the internal region, and FIG. 10 is a longitudinal sectional view taken along the line DD in FIG. 9. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2.2a, 2b... N-well, 3... P-type diffusion layer, 4.5... N-type diffusion layer, 6
．． 7... Groove, If... semiconductor chip, 12... input/output area, 13... guard ring area, 14... internal area, 21... P type semiconductor substrate, 22... N Well, 23... P type diffusion layer, 24... N type diffusion layer, 2
5...N type well (guard ring), 26...N type diffusion layer, 27...N type diffusion layer, 2nd...N type diffusion layer, 29...P type diffusion layer, 31 ...P-type semiconductor substrate,
32...N well, 33...P type diffusion layer, 34...
・N-type diffusion layer, 35...N-type well (guard ring)
, 36...N type diffusion layer. Figure 1 ZFJ destination I Figure 2 Figure 5 Figure 6 Figure 3 Figure 4 Figure 9 Figure 10

Claims (1)

[Claims] 1. In a semiconductor device in which an island-like region of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, and a MOS transistor is formed on each of the semiconductor substrate and the island-like region, the semiconductor substrate is formed in the island-like region. What is claimed is: 1. A semiconductor device characterized in that a groove is formed with a depth of up to 100 cm, and the groove separates an island region into a plurality of mutually insulated island regions.