JPH02163940A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02163940A JPH02163940A JP63317836A JP31783688A JPH02163940A JP H02163940 A JPH02163940 A JP H02163940A JP 63317836 A JP63317836 A JP 63317836A JP 31783688 A JP31783688 A JP 31783688A JP H02163940 A JPH02163940 A JP H02163940A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- intrinsic semiconductor
- conductivity type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 description 8
- 238000002955 isolation Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置特にトランジスタの構造に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, particularly a transistor.
第２図の様に、従来半導体集積回路に用いられるこの種
のトランジスタは、−導電型半導体基板の上に他の導電
型のエピタキシャル層を有し、前記エピタキシャル層内
に基板より電気的に分離される様に前記−導電型ベース
領域と該ベース領域内に他の導電型エミッタ領域を有す
る構造となっていた。As shown in FIG. 2, this type of transistor conventionally used in semiconductor integrated circuits has an epitaxial layer of another conductivity type on a -conductivity type semiconductor substrate, and the epitaxial layer is electrically isolated from the substrate. As shown in FIG. 2, the structure has a base region of the negative conductivity type and an emitter region of another conductivity type within the base region.
上述した従来の構造のトランジスタは、低濃度エピタキ
シャル層（不純物濃度： １０ ”ｃｍ−３前後）を有
していたために、前記エピタキシャル層内の他の素子と
の電気的分離のために分離領域を設ける必要があり、集
積回路の集積度が上がらないという欠点がある。Since the transistor with the conventional structure described above has a lightly doped epitaxial layer (impurity concentration: around 10"cm-3), an isolation region is required for electrical isolation from other elements in the epitaxial layer. However, the disadvantage is that the degree of integration of the integrated circuit cannot be increased.
本発明では、エピタキシャル層（不純物濃度：１０１ｓ
ｃｍ−”程度）を用いず真性半導体（不純物濃度：０〜
１０ ”ｃｍ−３程度）中にトランジスタを形成するこ
とにより各素子間の抵抗率は、従来のエピタキシャル層
を用いた場合の無限大〜１０″倍まで大きくなるため素
子間に電位差が生じても、そこに流れる電流は回路動作
に影響をおよぼさない程小さくなる。又、真性半導体を
用いることにより真性半導体中のキャリア（自由電子、
正孔）の数が極めて少なくなるため、通常不純物濃度層
をこの中においても、従来技術で生じていた寄生素子も
生じることはない。この様に、本発明は分離領域を設け
ることなく、電気的分離を実現するものである。In the present invention, an epitaxial layer (impurity concentration: 101s
cm-”) without using an intrinsic semiconductor (impurity concentration: 0~
By forming a transistor in a 10" cm-3 layer, the resistivity between each element increases from infinity to 10" times that when a conventional epitaxial layer is used, so even if a potential difference occurs between elements, , the current flowing there becomes so small that it does not affect the circuit operation. In addition, by using an intrinsic semiconductor, carriers (free electrons,
Since the number of holes (holes) is extremely small, the parasitic elements that occur in conventional techniques do not occur even in a normal impurity concentration layer. In this way, the present invention realizes electrical isolation without providing an isolation region.
以下、本発明について図面を参照して説明する。 Hereinafter, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例の構造断面図である。FIG. 1 is a structural sectional view of an embodiment of the present invention.
第１図に示すように、Ｐ型基板１の上にシランガス（Ｓ
ｉＨ＋）と塩素ガス（Ｃβ２）を用いて真性半導体層２
を成長させた後、真性半導体層２０表面よりＰ型不純物
（不純物濃度：１０１″Ｃ１１１””前後）を拡散し、
ベース領域３を形成する。次にＮ＋型不純物（不純物濃
度：ｘｏ２０前後）をベース領域３の両側面に重なる様
に拡散し、コレクタ領域４及びエミッタ領域５を形成す
る。次に、エミッタ、ベース、コレクタの各領域の所定
コンタクト回航領域を酸化膜６をエツチングして各電極
パターン７．８．９を形成する。この様にしてＮＰＮト
ランジスタを製造する。As shown in FIG. 1, silane gas (S
Intrinsic semiconductor layer 2 is formed using iH+) and chlorine gas (Cβ2).
After growing P-type impurities (impurity concentration: around 101"C111"") from the surface of the intrinsic semiconductor layer 20,
A base region 3 is formed. Next, N+ type impurities (impurity concentration: around xo20) are diffused so as to overlap both side surfaces of the base region 3 to form a collector region 4 and an emitter region 5. Next, the oxide film 6 is etched in predetermined contact regions of the emitter, base, and collector regions to form respective electrode patterns 7, 8, and 9. In this way, an NPN transistor is manufactured.
〔発明の効果〕
以上説明した様に、本発明は真性半導体領域２の中にベ
ース領域３．コレクタ領域４．エミッタ領域５を形成し
、トランジスタを構成することにより、真性半導体の性
質（高抵抗）を利用して、分離領域を設けることなく素
子間の電気的分離を可能にする。このことにより集積回
路の集積度向上、拡散工程の削減を実現できる。[Effects of the Invention] As explained above, the present invention includes a base region 3. in the intrinsic semiconductor region 2. Collector area 4. By forming the emitter region 5 and configuring a transistor, it is possible to electrically isolate between elements without providing an isolation region by utilizing the properties of an intrinsic semiconductor (high resistance). This makes it possible to improve the degree of integration of the integrated circuit and reduce the number of diffusion steps.
第１図は本発明の一実施例の構造断面図であり、第２図
は従来例の構造断面図である。
ｌ・・・・・・Ｐ型基板、２・・・・・・真性半導体領
域、３・・・・・・Ｐ型ベース領域、４・・・・・・Ｎ
型コレクタ領域、５・・・・・・Ｎ型エミッタ領域、６
・・・・・・酸化膜、７・・・・・・コレクタ電ｔｆｆ
ｉ、 ８・・・・・・ベース電Ｌ ９・・・・・・
エミッタ電極、１０・・・・・・Ｎ型埋込層、１１・・
・・・・Ｐ型分離領域、１２・・・・・・Ｎ型エピタキ
シャル層。
代理人 弁理士 内 原 晋FIG. 1 is a structural sectional view of one embodiment of the present invention, and FIG. 2 is a structural sectional view of a conventional example. 1...P-type substrate, 2...Intrinsic semiconductor region, 3...P-type base region, 4...N
type collector region, 5...N type emitter region, 6
...Oxide film, 7...Collector electric tff
i, 8...Base electric L 9...
Emitter electrode, 10...N-type buried layer, 11...
...P type isolation region, 12...N type epitaxial layer. Agent Patent Attorney Susumu Uchihara
Claims (1)
、前記真性半導体表面近傍に一導電型の第１領域と、該
第１領域の両側面に重なる様に構成される他の導電型の
第２領域を有することを特徴とする半導体装置。It has an intrinsic semiconductor layer formed on a semiconductor substrate of one conductivity type, and has a first region of one conductivity type near the surface of the intrinsic semiconductor, and another conductivity type configured to overlap on both sides of the first region. A semiconductor device characterized by having a second region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63317836A JPH02163940A (en) | 1988-12-16 | 1988-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63317836A JPH02163940A (en) | 1988-12-16 | 1988-12-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02163940A true JPH02163940A (en) | 1990-06-25 |
Family
ID=18092593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63317836A Pending JPH02163940A (en) | 1988-12-16 | 1988-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02163940A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8759191B2 (en) | 2006-01-19 | 2014-06-24 | Cadeka Microcircuits, Llc | Tunable semiconductor component provided with a current barrier |
-
1988
- 1988-12-16 JP JP63317836A patent/JPH02163940A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8759191B2 (en) | 2006-01-19 | 2014-06-24 | Cadeka Microcircuits, Llc | Tunable semiconductor component provided with a current barrier |
| US9076809B2 (en) | 2006-01-19 | 2015-07-07 | Cadeka Microcircuits, Llc | Tunable semiconductor component provided with a current barrier |
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