JPH02188944A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device suitably implemented in a large-scale integrated circuit (LSI) using a so-called mask-slicing method.

Conventional technology Generally speaking, new logic LSI (so-called full custom LSI)
Because it takes a huge amount of development time and cost to create an integrated circuit integrated circuit (SI), high-mix, low-volume production is not possible.Therefore, we developed a semi-custom LSI that can quickly and inexpensively produce large-scale integrated circuits that meet the diverse needs of users. To achieve this, we have traditionally used mask and slice type semiconductors! An integrated circuit device is used. Such a semiconductor integrated circuit device has a so-called gate array L.
Although it is slightly inferior to the above-mentioned full custom LSI in terms of integration and high speed, it is advantageous for high-mix, low-volume production because mask development is easy.

In such a mask-sliced semiconductor integrated circuit device, a desired logic circuit is constructed and manufactured by appropriately performing metal wiring for various gates (masters) formed in advance using multiple transistors, etc. be done.

Problems to be Solved by the Invention Semiconductor integrated circuit devices manufactured in this way are assembled into the semiconductor integrated circuit device by analyzing the connection configuration of metal wiring and the like with a metal smith after shipping. It becomes possible to reproduce logic circuits. In order to prevent such acts that are disadvantageous to manufacturers,
When designing logic circuits using manual layout, redundant circuits are added separately to make it difficult for others to analyze, but mass-produced masks and
Slice-type semiconductor integrated circuit devices are not provided with such redundant circuits and are easily imitated by others.

An object of the present invention is to provide a semiconductor integrated circuit device that can prevent its circuit configuration from being imitated by others by making it difficult to analyze the incorporated circuit configuration from the outside.

Means for Solving the Problems The present invention provides a semiconductor integrated circuit device in which a plurality of semiconductor circuit elements are formed, in which a second semiconductor circuit element of a specific type is connected to a predetermined first semiconductor circuit element. , the second semiconductor circuit element is selected such that the operation achieved by the second semiconductor circuit element and the first semiconductor circuit element to which it is connected is equal to the operation of the first semiconductor circuit element. This is a semiconductor integrated circuit device characterized by:

According to the present invention, the second semiconductor circuit element connected to the first semiconductor circuit element
The semiconductor circuit element is selected so that the operation achieved by the second semiconductor circuit element and the first semiconductor circuit element to which it is connected is the same as the operation of the first semiconductor circuit element. has a redundant circuit configuration that does not substantially contribute to operation. Therefore, it is difficult to analyze the configuration of such a semiconductor AM circuit device from the outside, and imitation by others can be prevented.

Embodiment FIG. 1 is a plan view of a semiconductor circuit element 1 constituting a part of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a P-type MO with a redundant design used in the semiconductor circuit element 1.
FIG. 3 is a sectional view showing the structure of a 3 (metal-oxide film-semiconductor) transistor, and FIG. 3 is a sectional view showing the structure of an N-type MO3) transistor.

The semiconductor circuit element 1 of this embodiment is used in a so-called mask slice type semiconductor integrated circuit device, and a redundant pseudo-operation circuit, which will be described later, is added, and from the wiring thereof, an 0R-NAND type composite gate is connected. It is designed to be visible, and in effect realizes the operation of a two-person NAND circuit.

An equivalent circuit of this semiconductor circuit element 1 is shown in FIG. The configuration of the semiconductor circuit element 1 will be explained with reference to FIG. 4. The semiconductor circuit element 1 includes two P-type MO3
'rL field effect transistor (FET) 2.3, two N type MO8 field effect transistors 4.5, and pseudo P type M
It is composed of an O9 field effect transistor 6 and a pseudo N-type MOS field effect transistor 7. The P-type MO3 field effect transistor (hereinafter referred to as P-type transistor) 2
and an N-type MO3 field effect transistor (hereinafter referred to as an N-type transistor) 4 constitute a complementary transistor, and a P-type transistor 3 and an N-type transistor 5 constitute a complementary transistor.

One input terminal 11 is commonly connected to the gates of the P-type transistor 2 and the N-type transistor 4.
The other input terminal 12 is commonly connected to the gates of the N-type transistor 3 and the N-type transistor 5, respectively. A DC power supply is connected to the sources of the P-type transistor 2 and the pseudo-P-type transistor 6, respectively. The drain of the similar P-type transistor 6 is connected to the source of the P-type transistor 3. Each train of P-type transistors 2.3 and N
The sources of the type transistors 4 are connected to the output terminal 1 in common.
5, the drain of N-type transistor 4 and N
The source of type transistor 5 is connected to the source of pseudo N type transistor 7, and the drains of N type transistor 5 and pseudo N type transistor 7 are each commonly grounded. A pseudo input terminal 16 is commonly connected to the gates of the pseudo P-type transistor 6 and the pseudo N-type transistor 7, respectively.

The semiconductor circuit element 1 having such a configuration constitutes an 0R-NAND type composite gate due to its wiring as shown in FIG. That is, the other input terminal 12 and the pseudo input terminal 16 are each input terminal of the OR circuit 20,
The one input terminal 11 is used as one input terminal of the AND circuit 21, and the output terminal 15 is connected to this 0R-NA.
It is used as an output terminal of an ND type composite gate.

The pseudo P-type transistor 6 is set to always be in a conductive state by an ion implantation technique described later. That is, by setting the threshold voltage relatively high using ion implantation technology, the pseudo input terminal 16
It is set so that it is always in a conductive state regardless of the level of the signal input from the terminal. Similarly, the pseudo N-type transistor 7 is also set to always be in a cut-off state by ion implantation technology.

Therefore, this semiconductor circuit element 1 becomes substantially an equivalent circuit as shown in FIG. That is, regardless of the level of the input signal from the pseudo input terminal 16, the pseudo P-type transistor 6 is in a conductive state and the pseudo N-type transistor 7 is in a cutoff state, so that these two transistors 6 and 7 are connected to the semiconductor circuit element. It does not contribute to the substantial operation of 1.

Therefore, if we focus on the actual operation of this semiconductor circuit element 1, as shown in FIG.
It is equivalent to a circuit.

Next, the configuration of this semiconductor circuit element 1 will be explained with reference to FIGS. 1 to 3.

Referring to FIG. 1, semiconductor circuit element 1 is roughly divided into P-type transistor region 31 and N-type transistor region 32. Referring to FIG. Each transistor region 31, 32 includes a P” diffusion region 33 for the source/drain of a P-type transistor.
and N0 diffusion regions 34 for source trains of N-type transistors. Each diffusion area 33.3
Gate polysilicon layers 35, 36, 37; 38, 39, and 40 are formed on 4 at intervals, respectively.

Polysilicon 3 for gate on P-type transistor region 31 side
5, 36.37 and gate polysilicon 38, 39.40 of the N-type transistor region 32 are connected to metal wirings 47, 48, 49 made of aluminum via contact holes 41.42, 43.44, 45.46, respectively. are electrically connected to each other by. These metal wiring 47, 48
．． 49 are the one input terminals 11 shown in FIG.
, the other input terminal 12, and the pseudo input terminal 16, respectively.

In the P° diffusion region 33, polysilicon 35.3 for the gate is formed.
Contact holes 51, 5 are formed in mutually opposite parts of 7.
2; Metal wirings 55 and 56 are electrically connected via 53 and 54. These metal interconnections 55 and 56 correspond to the sources of the P-type transistor 2 and pseudo-P-type transistor 6, respectively. Further, one end of a metal wiring 59 is connected to a portion of the P1 diffusion region 33 between the gate polysilicon 35 and 36 via contact holes 57 and 58. One end of this metal wiring 59 corresponds to each drain of the P-type transistor 2.3 whose gate electrode is the gate polysilicon 35.36.

The other end of the metal wiring 59 is also connected to the N diffusion region 34.
It is connected to the left side portion of the gate polysilicon 44 in FIG. 1 through contact holes 60 and 61. That is, the other end of the metal wiring 59 serves as the source of the N-type transistor 4. A metal layer is formed between the gate polysilicon 38 and 39 of the N0 diffusion region 34 through contact holes 62 and 63. ! One end of 64 is connected. The other end of the metal wiring 64 is connected to the right side portion of the gate polysilicon 4o in the N° diffusion region 34 in FIG. 1 via a contact hole 65, 66.

That is, one end of the metal wiring 64 serves as the drain and source of the N-type transistors 4 and 5, and the other end serves as the source of the pseudo N-type transistor 7. Polysilicon 45.4 for gate of N° diffusion region 34
Metal wiring 69 is connected to the portion between 6 through contact holes 67 and 68. This metal wiring 69 serves as each drain of the N-type transistor 5 and the pseudo-N-type transistor 7, and is grounded.

Next, the configuration of the pseudo P-type transistor 6 will be explained with reference to FIGS. 1 and 2.

Pseudo P-type transistor 6 has P-type transistors on both sides of gate polysilicon 37 on N--well layer 70.

Diffusion regions 71,72 are formed. A portion of the N--well layer 70 between the P' diffusion regions 71 and 72 is a channel region 73. Boron ions are implanted onto this channel region 73 to form a P1 diffusion region 74. The gate polysilicon 37 is formed on this P' diffusion region 74 with a gate oxide film 75 interposed therebetween.

By forming such a P° diffusion region 74,
The threshold voltage of the pseudo P-type transistor 6 can be shifted, and it can always be kept conductive regardless of the level of the gate voltage applied to the gate polysilicon 37. Note that if the P° diffusion region 75 is not formed by this boron ion implantation, the transistor becomes a normal P-type transistor. The pseudo N-type transistor 7 shown in FIG. 3 is also produced in the same manner. That is, boron ions are implanted onto the channel region 84 formed between the N° diffusion regions 81 and 82 of the P-well N80 to form the P° diffusion region 85.
form. By forming this P diffusion region 85, the threshold voltage of the pseudo N-type transistor 7 is shifted, and the gate polysilicon 40 on the gate oxide film 86 is
Regardless of the level of the gate voltage applied to the gate, the circuit can be kept in a cut-off state at all times. In addition, in Figure 1,
P diffusion region 748 formed by implanting boron ions
5 are indicated by two-dot chain lines 11 and 12, respectively.

In the semiconductor circuit element 1 formed in this manner, the P° diffusion region 74.85 is formed by the boron ion implantation described above.
Since it is difficult to analyze with a metallurgical microscope, it looks like an 0R-NAND circuit from the wiring. Therefore, from the structure of this layout AIW, it cannot be known that this semiconductor circuit element 1 essentially operates as a NAND circuit, and its secrecy is maintained. Note that when performing the ion implantation described above, a mask is used to specify the location.

Although a relatively simple circuit configuration has been described in this embodiment, in an actually used semiconductor integrated circuit device, the secrecy can be further improved by using a large number of semiconductor circuit elements having a more complicated circuit configuration. be able to. Note that even in circuit configurations that achieve the same operation, the secrecy can be further improved by changing the location where ions are implanted.

Therefore, even in mask-sliced integrated circuit devices in which the semiconductor portion of the semiconductor circuit element is preformed and the desired circuit configuration is realized by metal wiring, the advantage is that the number of manufacturing steps and the number of masks are small. It is possible to improve confidentiality and make analysis by others difficult without sacrificing security.

Effects of the Invention As described above, according to the present invention, the contents of the incorporated circuit configuration can be prevented from being imitated by others, and confidentiality can be improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the structure of a semiconductor circuit element 1 constituting a part of a semiconductor integrated circuit device used in an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the structure of a pseudo P-type transistor 6. FIG. 3 is a cross-sectional view showing the configuration of the pseudo N-type transistor 7, FIGS. 4 and 5 are equivalent circuit diagrams as seen from above the wiring structure of the semiconductor circuit element 1, and FIGS. 6 and 7 are the semiconductor circuit elements. FIG. 1 is a substantially equivalent circuit diagram of FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor circuit element, 2, 3... P-type transistor, 4, 5... N-type transistor, 6... Pseudo-P-type transistor, 7... Pseudo-N-type transistor, 33°74. 85...P0 diffusion area agent Patent attorney Number of strokes

Claims (1)

[Scope of Claims] In a semiconductor integrated circuit device formed with a plurality of semiconductor circuit elements, a second semiconductor circuit element of a specific type is connected to a predetermined first semiconductor circuit element, A semiconductor characterized in that the circuit element is selected such that the operation achieved by the second semiconductor circuit element and the first semiconductor circuit element to which it is connected is equal to the operation of the first semiconductor circuit element. Integrated circuit device.