JPH02196469A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary of the Invention] Semiconductor device, especially P-channel MO3! - Regarding the substrate bias of the transistor, P-channel MO3I - leakage current and expansion of the transistor
For the purpose of reducing capacitance, a voltage from an external power supply is applied to the substrate (substrate or well) of a P-channel MOS transistor, and a lower internal or external voltage is applied to the source and drain of the transistor. Configure.

[Industrial application field]

The present invention relates to a back bias to the substrate (or well) of a semiconductor device, particularly a P-channel MOS transistor.

In recent years, MOS ICs have been faced with the challenge of reducing leakage current and diffusion layer capacitance of each MOS transistor due to demands for higher speeds and lower power consumption.

[Conventional technology]

Conventional semiconductor devices are equipped with a substrate bias generator that applies a negative bias to the substrate or well of an N-channel MOS transistor section to reduce leakage current and diffusion layer capacitance of the transistor.

[Problem to be solved by the invention]

However, in order to apply a substrate bias in the P-channel MO3) transistor section, it is necessary to stably supply a voltage higher than the power supply voltage applied to the source and the zero to power supply voltage applied to the drain, and this must be applied inside the IC. It is actually impossible for this to occur.

FIG. 5 is an explanatory diagram of the substrate bias of a P-channel MOS transistor, in which 11 is a P-type substrate, 12 is an N-type well, 1
3 is a source (S), 14 is a drain (D), and 15 is a gate (G). This is the case when starting from a P substrate, but if an N substrate is used, an N well is not formed and the source,
The drain is formed directly on the substrate. Normally, the external power supply VCC is directly applied to the source 13, and the voltages of the drain 14 and gate 15 are set in the range of O''''Vcc.

Generally, ■ and c are applied to the well 12, but since this is at the same potential as the source 13, no substrate bias effect occurs. In order to create a substrate bias effect, well 1
The applied voltage in step 2 must be set to VCC + α (this applies a substrate bias of αV to the source), but this
It is difficult to generate this voltage stably inside C (it is difficult to configure a booster circuit that operates stably).

The present invention is intended to enable substrate biasing of a P-channel MOS transistor section using the existing external power supply.

[Means to solve the problem]

Figure 1 is a diagram of the principle of the present invention, where Qp is a P-channel MOS transistor, G is its gate, S is its source, D is its drain, SUB is an N-type substrate (or N-type well), and VCC.
I+ ■CCZ has two types of power supplies (however, V cc+ >
V ccz).

[Effect]

The first electric current tXvcc+ is supplied from the outside, and this is connected to the N-type substrate SUB (including the well, but hereinafter simply referred to as the substrate).
to be applied. A second power supply V ccz lower than this is applied to the P-type source S, and a voltage of 0 to 0 to the gate G and drain D is applied.
Apply an appropriate voltage of V CC2.

In this way, the transistor Qp can operate normally, and the substrate SUB, source S, and drain D
A bank bias of (Vcc+Vccz) or less is applied between them. As a result, the leakage current of the P-channel MOS transistor Qp is reduced, and the capacitance between the P''' diffusion layers of the source S and drain D and the N-type substrate SUB is also reduced.

The second power supply v ccz can be supplied externally, but it is 0. If the problem occurs in the internal circuit, there is no need to increase the number of external power supplies or IC power supply terminals. In particular, the first power supply ■66. If the voltage is the same as in the past, there is an advantage that there is no need to increase the burden on the user regarding the power supply.

[Embodiment] Figure 2 is a circuit diagram of an embodiment of the present invention. 'lOS
IC12 is connected to the second power supply V CC from the external power supply VCCI.
2 is an internal voltage step-down circuit, and 3 is an N-channel part substrate bias generation circuit that applies a negative substrate bias to the P-type substrate of the N-channel MOS transistor Q.

Negative substrate bias generation circuit 3 can be easily constructed using a known charge pump circuit or the like.

FIG. 2 illustrates a C-MOS inverter in which a P-channel MOS transistor Qp and an N-channel MOS transistor Q are formed on the same chip, connected in series, and a common input voltage is applied to the gates. 2nd power supply v
cez becomes the power source for the inverter. A negative bias voltage lower than the ground potential Vss is applied from the substrate bias generation circuit 3 to the P-type substrate of the N-channel MOS transistor Q of this inverter, and a negative bias voltage lower than the ground potential Vss is applied to the N-type substrate of the P-channel MOS transistor Qp. A second power supply V applied to an external power supply V higher than CC2. 9. is applied.

Therefore, a substrate bias effect can be expected not only in the N-channel but also in the P-channel, so leakage current and diffusion layer capacitance are reduced in both transistors, making it possible to achieve higher speeds and lower power consumption.

In general, the problems of lower breakdown voltage and lower reliability that occur as transistors become smaller can be prevented by lowering the voltage of the operating power supply. Therefore, as in this circuit, the power supply voltage V ccz of the circuit inside the chip is supplied from the outside.
Setting the value to be lower than the CCI is effective in this respect. In addition, by using the internal step-down circuit 2, the external power supply VCCI is left as it is (for example, 5V), and instead, a lower power supply Vccz (for example, 3V) is set inside the IC by the internal step-down circuit.
By creating V), it is possible to avoid increasing the burden on the user regarding the power supply device. Figure 3 shows the internal step-down circuit 2.
A specific example is shown below.

This is a MOS transistor Ql whose gate is connected to its drain, and a voltage lower than the power supply voltage VCC by the threshold voltage V of the transistor Q1 is obtained. This is a very simple circuit, but it is practical.

The substrate bias of the P-channel MOS transistor section of the present invention is effective when applied to a DRAM. A dynamic memory cell consists of a transistor and a capacitor C as shown in FIG. 4(b), and this transistor is generally an N-channel MOS transistor. However, as is known, N-channel memory cells have the problem of soft errors occurring due to alpha ray irradiation. In this regard, P-channel memory cells have the advantage of being strong in soft error resistance.

However, since the P-channel memory cell has a buried channel, the leakage current between the source and drain is large (and it could not be put into practical use).

In a P-channel type memory cell, if there is no back bias, leakage of drain current 1d occurs even when the gate voltage Vg=0, as shown in FIG. 4(C). However, if back bias can be applied to the N-Well as in the present invention, the Vg-1d characteristic becomes as shown by the broken line, and leakage current can be prevented.

If P-channel DRAM can be realized in this way,
Since it is more resistant to soft errors than N-channel DRAM, the reliability of retained data can be improved.

[Effects of the Invention] As described above, according to the present invention, it is possible to apply a substrate bias to the P-channel MOS transistor section, thereby reducing the leakage current and diffusion layer capacitance of the transistor, thereby increasing the speed and reducing the It is possible to reduce power consumption. Further, since the external power supply for this purpose can basically be left as is, there is an advantage that the burden on the user does not increase.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, Fig. 3 is a circuit diagram showing a specific example of an internal step-down circuit, Fig. 4 is an explanatory diagram of a dynamic type memory, Figure 5 shows P channel M
FIG. 2 is an explanatory diagram of an OS transistor. Ver. Figure 11: Principle diagram of the present invention Figure 2: Circuit diagram of an embodiment of the present invention

Claims (1)

[Claims] 1. A voltage from an external power supply (
V_C_C_1) is applied, and the source of the transistor (
A semiconductor device characterized in that a lower internally or externally generated voltage (V_C_C_2) is applied to the drain (D) and the drain (D). 2. Voltage (V) applied to source (S) and drain (D)
_C_C_2) is generated by an internal voltage down converter (2) formed in the same chip as the transistor (Qp). 3. The semiconductor device according to claim 1, wherein the P-channel MOS transistor (Qp) is a transistor of a memory cell of a dynamic random access memory.