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JPH0220192B2 - - Google Patents

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Publication number
JPH0220192B2
JPH0220192B2 JP17922383A JP17922383A JPH0220192B2 JP H0220192 B2 JPH0220192 B2 JP H0220192B2 JP 17922383 A JP17922383 A JP 17922383A JP 17922383 A JP17922383 A JP 17922383A JP H0220192 B2 JPH0220192 B2 JP H0220192B2
Authority
JP
Japan
Prior art keywords
branch
line
circuit
intra
significant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP17922383A
Other languages
Japanese (ja)
Other versions
JPS6072446A (en
Inventor
Yoshibumi Kato
Ikuo Tokizawa
Osamu Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP17922383A priority Critical patent/JPS6072446A/en
Publication of JPS6072446A publication Critical patent/JPS6072446A/en
Publication of JPH0220192B2 publication Critical patent/JPH0220192B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks

Landscapes

  • Small-Scale Networks (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Description

【発明の詳細な説明】 本発明はデイジタル・データ網に於ける、親端
末(主局)と複数の子端末(従局)との間でポー
リング・セレクテイング方式により通信を行なう
所謂多点間通信の分岐接続方式に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to so-called multipoint communication in which communication is performed between a parent terminal (main station) and a plurality of slave terminals (slave stations) using a polling/selecting method in a digital data network. The present invention relates to a branch connection method.

従来デイジタル・データ網では、加入者の端末
速度のデータは、宅内回線終端装置(DSU)に
おいて(6+2)エンベロープ構成のベアラ信号
に変換される。この加入者線伝送されたベアラ信
号は局内回線終端部(OCU)で終端され、X−
CONNと称する回線編集用端子接続部に出力さ
れる。このX−CONNには先の局内回線終端部
の局側の入出力線と分岐接続機能を有する分岐接
続部(MJU)の入出力線が接続されており、接
続ケーブルを用いて上記相互の接続を行つてい
る。なお前記の分岐接続部はあとに図面を用いて
示すが、1つの主局に対し複数の従局を1つの単
位として構成されており、所謂ポーリング・セレ
クテイング方式による主局指向形の片方向分岐を
構成するものである。
In conventional digital data networks, subscriber terminal speed data is converted into bearer signals in a (6+2) envelope configuration at a residential line termination unit (DSU). This bearer signal transmitted through the subscriber line is terminated at the intra-office circuit terminating unit (OCU), and
It is output to the line editing terminal connection section called CONN. This X-CONN is connected to the input/output lines on the station side of the intra-office line termination section and the input/output lines of the branch connection unit (MJU) that has a branch connection function, and the above mutual connections are made using a connection cable. is going on. The above-mentioned branch connection section will be shown later in the drawings, but it is configured with multiple slave stations as one unit for one master station, and is a unidirectional branch oriented to the master station using the so-called polling/selecting method. It constitutes.

以上のような構成により従来は2点間通信(非
分岐回線)と多点間通信(分岐回線)の回線編集
を空分割スイツチ形式のX−CONNで行い、か
つ分岐生成を片方向分岐のみ可能な分岐接続部で
行い、分岐回線数が増えた時(Nより大)複数の
分岐接続部を縦続接続する方式を採り、而も主局
と従局は固定されて用いる構成となつていた。
With the above configuration, line editing for point-to-point communication (non-branch line) and multi-point communication (branch line) was conventionally performed using X-CONN in the form of a space division switch, and branch generation was possible only in one direction. When the number of branch lines increases (greater than N), multiple branch connections are connected in cascade, and the main station and slave stations are fixed.

このため従来装置においては構成が複雑になる
ばかりでなく、任意の回線につき任意の回線数で
主局従局間の片方向および両方向の分岐を2つな
がら行なうことができず、また分岐回線数が多く
なつたときに特に構造が複雑になるという欠点が
あつた。
For this reason, in conventional equipment, not only is the configuration complicated, but it is not possible to perform two unidirectional and bidirectional branches between the master station and the slave station using any number of lines for any given line, and the number of branch lines is large. The disadvantage was that the structure became particularly complex as it aged.

従つて本発明の目的は任意の回線につき任意の
回線数で主従局任意の片方向および両方向分岐を
可能とする分岐接続方式を得ようとするものであ
る。
Accordingly, an object of the present invention is to provide a branching connection system that enables arbitrary unidirectional and bidirectional branching of master and slave stations with an arbitrary number of lines for an arbitrary line.

本発明によれば、デイジタル通信網における主
局と従局間で回線編集手段を介してポーリング・
セレクテイング方式の通信を行なう場合の分岐接
続手段において、前記回線編集手段として時分割
多重ハイウエイを用い、前記主局および従局の、
前記時分割多重ハイウエイとの間に送受すべきデ
ータ信号を収容する局内回線終端部が、該収容さ
れたデータ信号が有意であるかどうかを判定して
状態信号を発する有意状態検出回路および速度変
換機能を有するメモリから成りチヤネルパルスに
より制御されるタイムスロツト変換回路を備えて
おり、且つ、前記局内回線終端部のすべてを共通
に制御する手段であつて、前記時分割多重ハイウ
エイのタイムスロツトを管理するタイムスロツト
発生回路、前記タイムスロツトにどの局内回線終
端部のデータ信号を収容するか又該データ信号が
主局か従局かの回線設定情報を蓄積するアドレス
制御メモリ、当該局内回線終端部の発する有意の
状態信号を時分割に選択する選択回路、および分
岐回路の従局から主局へ向う挿入の回線において
当該局内回線終端部の発する状態信号が有意であ
るときにのみ前記パルスチヤネルを発する分岐回
路挿入パルス制御手段を有する共通制御手段を備
え、任意速度のデータを任意の回線数組合わせて
分岐回線を構成するようにしたことを特徴とする
分岐接続方式が得られる。
According to the present invention, polling and processing are performed between a master station and a slave station in a digital communication network via line editing means.
In the branch connection means for performing selecting type communication, a time division multiplex highway is used as the line editing means, and the main station and slave station
A significant state detection circuit and a speed converter, in which an intra-office line termination section that accommodates data signals to be transmitted and received with the time division multiplex highway determines whether the accommodated data signals are significant and issues a status signal. A means for commonly controlling all of the intra-office line terminals, and managing the time slots of the time division multiplex highway. a time slot generation circuit for accommodating the data signal of which intra-office line termination in the time slot, and an address control memory for storing line setting information as to whether the data signal is a master station or a slave station; A selection circuit that selects a significant status signal in a time-division manner, and a branch circuit that emits the pulse channel only when the status signal generated by the intra-office line termination section of the branch circuit is significant on the inserted line from the slave station to the main station. A branch connection system is obtained, which is characterized in that it includes a common control means having an insertion pulse control means, and a branch line is formed by combining data at an arbitrary speed with an arbitrary number of lines.

次に図面を参照して詳細に説明する。 Next, a detailed explanation will be given with reference to the drawings.

第1図は従来方式における局内回線終端部と分
岐接続部の接続方式(回線編集方法)を示したも
のであり、分岐接続部11の主局および従局1〜
4はX−CONN12を介して局内回線終端部1
3と接続される。なお14は接続コードをあらわ
す。
FIG. 1 shows the connection method (line editing method) between the in-office line termination section and the branch connection section in the conventional system.
4 is the in-office line termination section 1 via X-CONN12
Connected to 3. Note that 14 represents a connection code.

第2図は第1図で設定された分岐接続部の回線
構成例の一部を詳細にあらわした図であり、分岐
接続部11は主局と従局1〜4の入出力端子を有
し、主局からの信号は分岐回線19で4分岐され
従局1〜4に、すなわち局内回線終端部13−1
ないし13−4に送出される。従局1〜4からの
有意状態信号は全て該当するSビツト制御回路1
5により、その信号が有意であるか否かをモニタ
され、すなわちデータ通信中であるかどうかを判
定され、もし有意であるば該当する挿入ゲート1
6が開放され、その信号は論理和回路17を経て
挿入回線18に出力され、送出される。
FIG. 2 is a diagram showing in detail a part of an example of the line configuration of the branch connection section set in FIG. The signal from the main station is branched into four by the branch line 19 and sent to the slave stations 1 to 4, that is, the in-office line termination section 13-1.
to 13-4. All significant status signals from slave stations 1 to 4 are sent to the corresponding S bit control circuit 1.
5, it is monitored whether the signal is significant, that is, it is determined whether data communication is in progress, and if it is significant, the corresponding insertion gate 1
6 is opened, and the signal is output to the insertion line 18 via the OR circuit 17 and sent out.

第3図は加入者線を終端する局内回線終端部1
3の構成を示す図であり、加入者線終端用アナロ
グ回路24と加入者線終端用デイジタル回路25
とから成つている。
Figure 3 shows the in-office line termination unit 1 that terminates the subscriber line.
3, which includes a subscriber line terminating analog circuit 24 and a subscriber line terminating digital circuit 25.
It consists of.

第4図は以上のような従来の構成で成し得る多
点間通信における主局と従局の接続を概念的にあ
らわした図であつて、常に主局が固定した所謂ポ
ーリング・セレクテイング方式による片方向分岐
であることを示している。つまり第2図に於ては
主局からポーリングされた従局のみが、主局ヘア
ンサーを返し、そのアンサー信号中の有意状態信
号を有意状態に設定する事により上述の回路動作
で挿入が達成され、主局ヘアンサーが返される事
と成る。
Figure 4 is a diagram conceptually showing the connection between the master station and slave stations in multipoint communication that can be achieved with the conventional configuration as described above, and is based on the so-called polling/selecting method in which the master station is always fixed. This indicates a one-way branch. In other words, in FIG. 2, only the slave station polled by the master station returns the master station hair answerer and sets the significant state signal in the answer signal to the significant state, thereby achieving insertion by the circuit operation described above. The main hairdresser will be returned.

第4A図は以上のような構成と特性を有する従
来装置で分岐回線数が増えたときの分岐接続部を
縦続接続した状態を示した図である。この場合第
1段の分岐接続部11−1の従局13−1の代り
に第2段の分岐接続部11−2を設け、合計7個
の従局が接続されることを示す。更に分岐接続部
を増設するときは従局13−5の代りに分岐接続
部を設ければよい。以下同じ。従つて先にも記し
たように、全体としての構造が複雑になり、又、
任意の回線につき任意の回線数で主局従属間の片
方向および両方向の分岐を行なうことができなか
つたのである。
FIG. 4A is a diagram showing a state in which branch connections are connected in cascade when the number of branch lines increases in a conventional device having the above configuration and characteristics. In this case, the second stage branch connection section 11-2 is provided in place of the slave station 13-1 of the first stage branch connection section 11-1, and a total of seven slave stations are connected. Furthermore, when adding a branch connection section, a branch connection section may be provided in place of the slave station 13-5. same as below. Therefore, as mentioned earlier, the overall structure becomes complicated, and
It was not possible to perform unidirectional and bidirectional branching between the master station and subordinates using any number of lines for any given line.

第5図は本発明のポーリング・セレクテイング
方式の通信を行う場合の分岐接続方式の構成をあ
らわす図であつて、時分割多重ハイウエイ20
と、加入者線終端部(一般的には局内回線終端部
ともいう)21と、これら両者を制御信号22
(22−1ないし22−n)で制御する制御部2
3とから成つている。加入者線終端部21はNo.1
からNo.nまであるが、その番号は従局だけでなく
主局を含めて付けてあり、第2図とは異なつてい
る。なお鎖線で示した加入者線終端部のNo.n+1
ないしNo.n+n′についてはあとに説明する。そし
て各加入者線終端部の間で、上記の制御信号の外
に送信データ及び受信データがやり取りされる。
FIG. 5 is a diagram showing the configuration of a branch connection method when performing polling/selecting method communication according to the present invention, in which the time division multiplex highway 20
, a subscriber line termination section (generally referred to as an in-office line termination section) 21, and a control signal 22 that controls both of them.
Control unit 2 controlled by (22-1 to 22-n)
It consists of 3. Subscriber line termination section 21 is No.1
to No. n, but the numbers include not only the slave stations but also the master station, which is different from the one in Figure 2. No.n+1 at the end of the subscriber line indicated by the chain line
to No. n+n' will be explained later. In addition to the above-mentioned control signals, transmission data and reception data are exchanged between each subscriber line terminal.

第6図は上記の加入者線終端部21の構成をあ
らわした図であつて、加入者線終端用アナログ回
路24と、加入者線終端用デイジタル回路25
と、チヤネルパルスCHSとCHRで制御され、時
分割多重された時系列上で当該信号が重畳されて
いるタイムスロツト位置を変換するタイムスロツ
ト変換回路26と、信号が有意であるか否かを判
定し、すなわちデータ通信中であるかどうかを判
定し、有意状態信号Sを出力する有意状態検出回
路15とから構成される。なおチヤネルパス
CHSとCHRおよび出力信号SはまとめてCであ
らわしている。
FIG. 6 is a diagram showing the configuration of the subscriber line terminating section 21, which includes a subscriber line terminating analog circuit 24 and a subscriber line terminating digital circuit 25.
and a time slot conversion circuit 26 that is controlled by channel pulses CHS and CHR and converts the time slot position where the signal is superimposed on the time-division multiplexed time series, and a time slot conversion circuit 26 that determines whether the signal is significant. , that is, a significant state detection circuit 15 that determines whether data communication is in progress and outputs a significant state signal S. Furthermore, channel pass
CHS, CHR, and output signal S are collectively represented by C.

第7図は第5図の制御部23の構成を詳しく示
した図であり、時分割多重ハイウエイ20のタイ
ムスロツトを管理するタイムスロツト発生回路2
7と、そのタイムスロツトにどの局内回線終端部
の信号を収容するか、又その信号が分岐回線であ
れば主局であるか従局であるかの回線設定情報を
蓄積するアドレス制御メモリ28および29と、
当該の局内回線終端部から送出された有意状態信
号Sを時分割に選択する選択回路30と、分岐回
線の従局から主局へ向う回線(挿入)に於て、当
該の局内回線終端部の信号が有意であればそのチ
ヤネルアドレスを発生し、有意でなければそのチ
ヤネルアドレスをインヒビツトする分岐回線挿入
パルス制御回路31と、その出力信号をデコード
し、チヤネルパルス(Cの一部)を発生するデコ
ード回路32から構成される。なお33はアドレ
スコントロールメモリ28,29に回線設定情報
を外部から書き込む時の入力端子である。
FIG. 7 is a diagram showing in detail the configuration of the control section 23 shown in FIG.
7, and address control memories 28 and 29 that store line setting information about which intra-office line end signal is to be accommodated in the time slot, and whether the signal is from the main station or slave station if the signal is from a branch line. and,
A selection circuit 30 that time-divisionally selects the significant state signal S sent out from the intra-office line termination section, and a signal from the intra-office line termination section on the line (insertion) from the slave station to the main station of the branch line. A branch line insertion pulse control circuit 31 that generates a channel address if it is significant and inhibits that channel address if it is not significant, and a decoder that decodes the output signal and generates a channel pulse (part of C). It is composed of a circuit 32. Note that 33 is an input terminal for writing line setting information into the address control memories 28 and 29 from the outside.

以下に本発明の動作を一例に示して説明する。 The operation of the present invention will be explained below using an example.

先づ信号の情報速度をmビツト/秒とし、時分
割多重ハイウエイの速度をN・mビツト/秒とす
る。さて、加入者線伝送されたmビツト/秒情報
は局内回線終端部21内のタイムスロツト変換回
路26でN・mビツト/秒の速度のバースト的な
信号に変換される。従つて先のハイウエイ20上
での信号の処理数はNと成る。このハイウエイ上
のN個のタイムスロツトの内のどこに先のバース
ト的な信号を出力するか、又は逆にどこのタイム
スロツトのバースト的な信号を取り込むかを制御
するのがタイムスロツト交換回路26の制御用チ
ヤネルパルスCHSS・CHRである。
First, let us assume that the information rate of the signal is m bits/second, and that the speed of the time division multiplex highway is N·m bits/second. Now, the m bits/second information transmitted through the subscriber line is converted into a burst signal at a speed of N·m bits/second by the time slot conversion circuit 26 in the intra-office line termination section 21. Therefore, the number of signals processed on the highway 20 is N. The time slot exchange circuit 26 controls which of the N time slots on the highway should output the first burst signal, or conversely which time slot should the burst signal be taken in. Control channel pulse CHSS/CHR.

ここで第8図に示す様なn個の局内回線終端部
で構成される1つの分岐回線を考え、No.1を主
局、No.2〜No.nを従局としてみる。そこで分岐と
挿入のタイムスロツトをTSiとTSj(但しi≠j)
とし、装置の機能を分岐機能と挿入機能に分けて
考える。
Let us now consider one branch line consisting of n intra-office line terminals as shown in FIG. 8, with No. 1 as the master station and Nos. 2 to 2 as slave stations. Therefore, we set the branch and insertion time slots as TSi and TSj (where i≠j).
The functions of the device are divided into a branch function and an insertion function.

第9図および第10図は第8図の分岐回線の分
岐時(TSi)における分岐機能の構成および挿入
時(TSj)における挿入機能の構成をそれぞれあ
らわした図である。
FIGS. 9 and 10 are diagrams showing the configuration of the branch function at the time of branching (TSi) and the configuration of the insertion function at the time of insertion (TSj) of the branch line in FIG. 8, respectively.

第9図に於ては、TSi時、No.1は主局であるの
でCHSに、又No.2〜No.nは従局であるので当該
のCHRに、それぞれチヤネルパルスを制御部2
3から分配する。これによりNo.1の信号はNo.2〜
No.nへ分岐される。
In Fig. 9, in the case of TSi, channel pulses are sent to the control unit 2 to the CHS because No. 1 is the master station, and to the corresponding CHR since No. 2 to No. n are slave stations.
Distribute from 3. As a result, the signal of No. 1 is changed from No. 2 to
Branched to No.n.

第10図に於ては、TSj時、No.3がポーリング
されたとすれば、そのNo.3のみ有意信号が有意で
他のNo.2、No.4〜No.nは非有意状態であり(複数
の従局が同時に有意にはならない。)、上述の説明
より従局のNo.2〜No.nについては、No.3のみ
CHSにチヤネルパルスが制御部23から分配さ
れ、かつ同時にNo.1の主局にCHRのチヤネルパ
ルスが同様に分配される。これによりNo.3の信号
のみNo.1へ挿入される。
In Fig. 10, if No. 3 is polled at TSj, only No. 3 has a significant signal, and the other No. 2, No. 4 to No. n are in a non-significant state. (Multiple slave stations cannot become significant at the same time.) From the above explanation, for slave stations No. 2 to No. n, only No. 3
Channel pulses are distributed to the CHS from the control unit 23, and at the same time, channel pulses of the CHR are similarly distributed to the No. 1 main station. As a result, only the No. 3 signal is inserted into No. 1.

第11図は以上の様子をあらわした図である。 FIG. 11 is a diagram showing the above situation.

さて上記例ではNo.1を主局とし、n回線の分岐
回線を生成したが、制御部23内のアドレスコン
トメモリ28,29の内容を必要により更新ある
いは切替る事により、主局の設定位置および分岐
数を随時可能とする事が出来、所謂両方向分岐も
達成しうる。
Now, in the above example, No. 1 is the main station and n branch lines are generated, but by updating or switching the contents of the address control memories 28 and 29 in the control unit 23 as necessary, the setting position of the main station can be changed. The number of branches can be changed at any time, and so-called bidirectional branching can also be achieved.

第12図は上記のような動作の一例として、No.
3を主局にNo.1が有意状態の場合を示した図であ
る。
Figure 12 shows No. 1 as an example of the above operation.
3 is a diagram showing a case where No. 3 is the main station and No. 1 is in a significant state. FIG.

又、No.1〜No.nの回線につきTSiとTSjを用い
て1つの分岐回線を構成しているのと同様に、別
の複数の回線につき別のタイムスロツトを用いて
同一時分割多重ハイウエイ20上に分岐回線を構
成する事ができる。第5図に鎖線で示した加入線
用終端部21のNo.n+1ないしNo.n+n′がこれを
示している。なおn′はnと同じであつてもよいこ
とはいうまでもない。
In addition, in the same way that TSi and TSj are used to configure one branch line for lines No. 1 to No. n, the same time division multiplex highway is configured using different time slots for multiple lines. A branch line can be configured on 20. This is illustrated by No. n+1 to No. n+n' of the joining line termination portion 21 indicated by chain lines in FIG. It goes without saying that n' may be the same as n.

以上本発明によれば、従来空分割スイツチ形式
で分岐回線の回線編集と分岐挿入部1による片方
向分岐を行つていたのを、時分割スイツチとアド
レスコントロールメモリ制御により制御する事に
より、任意の回線につき任意の回線数で主従局任
意の片方向及び両方向分岐を実現できる。
As described above, according to the present invention, the line editing of the branch line and the one-way branching by the branch/insertion unit 1 were performed in the conventional air division switch format, but by controlling it with the time division switch and address control memory control, it is possible to perform arbitrary branching. It is possible to realize arbitrary unidirectional and bidirectional branching of master and slave stations using any number of lines.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来方式による局内回線終端部と分岐
接続部の接続方式を示した図、第2図は第1図で
設定された分岐接続部の回線構の一例を示した
図、第3図は加入者を終端する局内回線終端部の
構成の一例を示す図、第4図は従来方式における
主局と従局の接続を概念的にあらわした図、第4
A図は従来方式で分岐回線数が増大したときの接
続状態をあらわした図、第5図は本発明の分岐接
続方式の構成の一例を示した図、第6図は第5図
における加入者終端部の構成の一例をあらわした
図、第7図は第5図における制御部の構成を詳し
くあらわした図、第8図はn個の局内回線終端部
で構成される1つの分岐回線をあらわした図、第
9図は第8図の分岐回路の分岐時における分岐機
能の構成をあらわした図、第10図は第8図分岐
回路の挿入時における挿入機能の構成をあらわし
た図、第11図は分岐回路の挿入時におけるチヤ
ネルパルスの分配の状態をあらわした図、第12
図は両方向分岐におけるチヤネルパルス分配の状
態を示す図である。 記号の説明:11は分岐接続部、12はX−
CONN、13は局内回線終端部、14は接続コ
ード、20は時分割多重ハイウエイ、21は加入
者線終端部、22は制御信号、23は制御部、2
4は加入者線終端用アナログ回路、25は加入者
線終端用デジタル回路、26はタイムスロツト変
換回路、27はタイムスロツト発生回路、28は
CHS用アドレス制御メモリ、29はCHR用アド
レス制御メモリ、30は選択回路、31は分岐回
線挿入パルス制御回路、32はデコード回路をそ
れぞれあらわしている。
Figure 1 is a diagram showing a conventional method for connecting an in-office line termination part and a branch connection part, Figure 2 is a diagram showing an example of the line configuration of a branch connection part set in Figure 1, and Figure 3. 4 is a diagram showing an example of the configuration of an in-office line termination section that terminates a subscriber; FIG.
Figure A is a diagram showing the connection state when the number of branch lines increases in the conventional system, Figure 5 is a diagram showing an example of the configuration of the branch connection system of the present invention, and Figure 6 is a diagram showing the connection state when the number of branch lines increases in the conventional system. FIG. 7 is a diagram showing an example of the configuration of the termination section, FIG. 7 is a diagram showing in detail the configuration of the control section in FIG. 5, and FIG. 8 is a diagram showing one branch line composed of n intra-office line termination sections. Figure 9 is a diagram showing the configuration of the branch function when branching the branch circuit in Figure 8, Figure 10 is a diagram showing the configuration of the insertion function when the branch circuit in Figure 8 is inserted, Figure 11 The figure shows the state of channel pulse distribution when a branch circuit is inserted.
The figure shows the state of channel pulse distribution in bidirectional branching. Explanation of symbols: 11 is branch connection, 12 is X-
CONN, 13 is an in-office line termination section, 14 is a connection code, 20 is a time division multiplex highway, 21 is a subscriber line termination section, 22 is a control signal, 23 is a control section, 2
4 is an analog circuit for subscriber line termination, 25 is a digital circuit for subscriber line termination, 26 is a time slot conversion circuit, 27 is a time slot generation circuit, and 28 is a time slot generation circuit.
Reference numeral 29 represents an address control memory for CHS, numeral 29 represents an address control memory for CHR, numeral 30 represents a selection circuit, numeral 31 represents a branch line insertion pulse control circuit, and numeral 32 represents a decoding circuit.

Claims (1)

【特許請求の範囲】 1 デイジタル通信網における主局と従局間で回
線編集手段を介してポーリング・セレクテイング
方式の通信を行なう場合の分岐接続手段におい
て、前記回線編集手段として時分割多重ハイウエ
イを用い、前記主局および従局の、前記時分割多
重ハイウエイとの間に送受すべきデータ信号を収
容する局内回線終端部が、該収容されたデータ信
号が有意であるかどうかを判定して状態信号を発
する有意状態検出回路および速度変換機能を有す
るメモリから成りチヤネルパルスにより制御され
るタイムスロツト変換回路を備えており、且つ、
前記局内回線終端部のすべてを共通に制御する手
段であつて、前記時分割多重ハイウエイのタイム
スロツトを管理するタイムスロツト発生回路、前
記タイムスロツトにどの局内回線終端部のデータ
信号を収容するか又該データ信号が主局か従局か
の回線設定情報を蓄積するアドレス制御メモリ、
当該局内回線終端部の発する有意の状態信号を時
分割に選択する選択回路、および分岐回路の従局
から主局へ向かう挿入の回線において当該局内回
線終端部の発する状態信号が有意であるときにの
み前記パルスチヤネルを発する分岐回路挿入パル
ス制御手段を有する共通制御手段を備え、任意速
度のデータを任意の回線数組合わせて分岐回線を
構成するようにしたことを特徴とする分岐接続方
式。 2 前記分岐回路が同一時分割多重データハイウ
エイ上に設けられた複数の分岐回路であるような
特許請求の範囲1の分岐接続方式。
[Scope of Claims] 1. In a branch connection means for performing polling/selecting communication between a master station and a slave station in a digital communication network via a line editing means, a time division multiplex highway is used as the line editing means. , intra-office line termination units of the master station and the slave station that accommodate data signals to be transmitted and received with the time division multiplex highway determine whether the accommodated data signals are significant and send a status signal. It is equipped with a time slot conversion circuit that is controlled by channel pulses and is made up of a significant state detection circuit that generates a signal and a memory that has a speed conversion function, and
Means for commonly controlling all of the intra-office line terminals, which includes a time slot generation circuit for managing the time slots of the time division multiplex highway, and a means for determining which intra-office line terminal section's data signal is accommodated in the time slot. an address control memory that stores line setting information on whether the data signal is a master station or a slave station;
A selection circuit that time-divisionally selects a significant status signal emitted by the intra-office line termination section, and only when the status signal emitted by the intra-office line termination section is significant in the inserted line from the slave station to the main station of the branch circuit. A branch connection system comprising a common control means having a branch circuit insertion pulse control means for emitting the pulse channel, and a branch line is configured by combining data of an arbitrary speed with an arbitrary number of lines. 2. The branch connection system according to claim 1, wherein the branch circuit is a plurality of branch circuits provided on the same time division multiplex data highway.
JP17922383A 1983-09-29 1983-09-29 Branch connecting system Granted JPS6072446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17922383A JPS6072446A (en) 1983-09-29 1983-09-29 Branch connecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17922383A JPS6072446A (en) 1983-09-29 1983-09-29 Branch connecting system

Publications (2)

Publication Number Publication Date
JPS6072446A JPS6072446A (en) 1985-04-24
JPH0220192B2 true JPH0220192B2 (en) 1990-05-08

Family

ID=16062084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17922383A Granted JPS6072446A (en) 1983-09-29 1983-09-29 Branch connecting system

Country Status (1)

Country Link
JP (1) JPS6072446A (en)

Also Published As

Publication number Publication date
JPS6072446A (en) 1985-04-24

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