JPH02215125A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02215125A JPH02215125A JP1035054A JP3505489A JPH02215125A JP H02215125 A JPH02215125 A JP H02215125A JP 1035054 A JP1035054 A JP 1035054A JP 3505489 A JP3505489 A JP 3505489A JP H02215125 A JPH02215125 A JP H02215125A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- layer
- film
- heat treatment
- thermal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000010438 heat treatment Methods 0.000 claims abstract description 21
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000010408 film Substances 0.000 abstract description 65
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 239000010409 thin film Substances 0.000 abstract description 6
- 238000004380 ashing Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000007789 gas Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 238000011109 contamination Methods 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 125000001153 fluoro group Chemical group F* 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000000356 contaminant Substances 0.000 description 4
- 239000002253 acid Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052736 halogen Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- -1 tungsten halogen Chemical class 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 239000003513 alkali Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 101100256026 Drosophila melanogaster meigo gene Proteins 0.000 description 1
- 235000002918 Fraxinus excelsior Nutrition 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000002956 ash Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に係り、特に異方性ドラ
イエツチング法によって加工されたトレンチのエツチン
グ面を改質する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for modifying the etched surface of a trench processed by an anisotropic dry etching method.
近年、半導体記憶装置は記憶容量の増大の要求に伴って
素子の微細化が促進されている。素子の微細化に伴う選
択酸化法による素子間分離は、Ｓｉ基板表面に深い溝を
形成しこの溝によって素子間分離を行なうトレンチ素子
分離が有望となっている。又、記憶情報を蓄えるキャパ
シタ部でも面積の縮少により蓄積電荷容量の減少を補う
ためのトレンチキャパシタが有望となっている。ところ
で、シリコン基板に微細な溝を形成する方法としては、
異方性ドライエツチング法が用いられ、溝は概ね垂直側
壁をもって形成される。然るに、異方性ドライエツチン
グ法により溝を形成すると、溝の側壁及び底部のシリコ
ンの表面層にエツチングによる損傷やエツチングガスと
シリコンとの反応生成物による汚染層が生じる。そこで
、異方性ドライエツチング後の処理として、０！アツシ
ング、酸及びアルカリ処理又は加工されたシリコン゛表
面を一旦熱酸化した後、エツチング除去する方法が行な
われている。In recent years, miniaturization of elements in semiconductor memory devices has been promoted in response to demands for increased storage capacity. Trench element isolation, in which deep grooves are formed on the surface of a Si substrate and the grooves are used to isolate elements, has become promising for element isolation by selective oxidation as devices become smaller. Furthermore, trench capacitors are becoming promising for compensating for the reduction in storage charge capacity due to the reduction in area of the capacitor section that stores stored information. By the way, as a method of forming fine grooves in a silicon substrate,
An anisotropic dry etching process is used and the grooves are formed with generally vertical sidewalls. However, when grooves are formed by anisotropic dry etching, damage due to etching and a contamination layer due to reaction products between etching gas and silicon occur on the side walls and bottom silicon surface layer of the grooves. Therefore, as a treatment after anisotropic dry etching, 0! A method of thermally oxidizing the surface of silicon that has been subjected to ashes, acid and alkali treatment, or processing, and then removing it by etching is used.
従来、この種のトレンチ形成法は「特開昭６２−２８１
４２９号；第４８回応用物理学会学術講演会、予稿集１
９ａ−Ｍ−６．第５６１頁」に開示されるものがある。Conventionally, this type of trench forming method was disclosed in ``Japanese Patent Application Laid-Open No. 62-281.
No. 429; 48th Japan Society of Applied Physics Academic Conference, Proceedings 1
9a-M-6. There is something disclosed on page 561.
これを第５図乃至第７図に基づいて説明する。尚、第５
図は工程図、第６図は二次イオン質量分析（ＳＩＭＳ）
によるＦ原子の濃度プロファイル特性図、及び第７図は
トレンチの断面図である。This will be explained based on FIGS. 5 to 7. Furthermore, the fifth
The figure is a process diagram, and Figure 6 is secondary ion mass spectrometry (SIMS)
FIG. 7 is a sectional view of a trench.
先ず、第５図ｔａ＋に示すように、Ｐ型Ｓｉ基板ｌの非
能動領域にフィールド絶縁膜２を形成する。その後、全
面に０．８μ程度のＣＶＤ酸化膜３を形成する。そして
、このＣＶＤ酸化膜３をパターン化し、これをマスクと
してＣＣ１ｚＰｔガスを用いた反応性イオンエツチング
（ＲＩＥ）を行ない、基板ｌの能動領域に垂直な側壁を
有する＄４を形成する。First, as shown in FIG. 5 ta+, a field insulating film 2 is formed in a non-active region of a P-type Si substrate 1. Then, as shown in FIG. Thereafter, a CVD oxide film 3 of about 0.8 μm is formed on the entire surface. Then, this CVD oxide film 3 is patterned, and using this as a mask, reactive ion etching (RIE) is performed using CC1zPt gas to form a $4 having sidewalls perpendicular to the active region of the substrate 1.
このとき、第５図（ｂｌに示す如く、上記′ａ４のエツ
チング面、所謂シリコン表面にＦ原子等の汚染層５及び
損傷層６が夫々形成される。At this time, as shown in FIG. 5 (bl), a contamination layer 5 such as F atoms and a damaged layer 6 are respectively formed on the etched surface 'a4', the so-called silicon surface.
そこで、第５図ｆｃｌに示すように、電気炉中で酸素及
び水素の混合ガスを燃焼して９００℃以下の低温で約１
０分間熱酸化を行ない、溝４表面に熱酸化膜７を形成す
る。その際、上記汚染層５及び損傷層６は熱酸化膜７内
に含まれる。又、この場合、熱酸化膜７は９００℃以下
の低温で形成されるため、酸化時における損傷層６の拡
張が抑制される。Therefore, as shown in FIG.
Thermal oxidation is performed for 0 minutes to form a thermal oxide film 7 on the surface of the groove 4. At this time, the contaminated layer 5 and the damaged layer 6 are included in the thermal oxide film 7. Further, in this case, since the thermal oxide film 7 is formed at a low temperature of 900° C. or lower, expansion of the damaged layer 6 during oxidation is suppressed.
その後、第５図ｆｄｌに示すように、上記熱酸化膜７及
びＣＶＤ酸化膜３をフン酸でエツチング除去する。この
とき、熱酸化膜７に含まれる汚染層５及び損傷層６も同
時に除去され、トレンチを完成していた。Thereafter, as shown in FIG. 5fdl, the thermal oxide film 7 and the CVD oxide film 3 are removed by etching with hydronic acid. At this time, the contaminated layer 5 and damaged layer 6 included in the thermal oxide film 7 were also removed at the same time, completing the trench.
（発明が解決しようとする課題）
然し乍ら、上述した従来のトレンチ形成法においては、
熱酸化膜７の酸化温度が９００℃以下の低温であるため
、酸化時間を長くとらなければならない、そのため、第
６図に示すように、熱酸化膜７内は勿論、Ｓｉ基板１中
へもＦ原子が拡散する。(Problems to be Solved by the Invention) However, in the conventional trench forming method described above,
Since the oxidation temperature of the thermal oxide film 7 is a low temperature of 900° C. or lower, the oxidation time must be long. Therefore, as shown in FIG. F atoms diffuse.
即ち熱酸化膜７形成時に、溝４のシリコン表面に付着し
た汚染層５がＳｔ基Ｆｉｌ中に拡散されてしまう、この
ため、後工程で熱酸化膜７を除去しても汚染層５が充分
に除去できず、残存する不純物のため、耐圧不良等が発
生し、良好な素子特性が得られないという問題点があっ
た。That is, when the thermal oxide film 7 is formed, the contamination layer 5 attached to the silicon surface of the groove 4 is diffused into the St-based film. Therefore, even if the thermal oxide film 7 is removed in a later process, the contamination layer 5 is not sufficient. There was a problem in that impurities that could not be removed and remained would cause poor breakdown voltage and the like, making it impossible to obtain good device characteristics.
又、第７図に示すように、９００℃以下の低温で熱処理
を行なうため、溝４の上部コーナ一部４ａの熱酸化膜７
の酸化速度が遅くなり、溝４の上部コーナ一部４ａが凸
状に変形すると共に、溝４の下部コーナ一部４ｂでは周
囲から圧縮応力を受けて凹状に変形する。このため、キ
ャパシタの容量変動又は絶縁特性の著しい劣化等が発生
するという問題点があった。Further, as shown in FIG. 7, since the heat treatment is performed at a low temperature of 900° C. or less, the thermal oxide film 7 on the upper corner portion 4a of the groove 4 is
The oxidation rate of the groove 4 becomes slower, and the upper corner portion 4a of the groove 4 is deformed into a convex shape, and the lower corner portion 4b of the groove 4 is deformed into a concave shape by receiving compressive stress from the surroundings. Therefore, there have been problems in that capacitance fluctuations of the capacitor or significant deterioration of insulation properties occur.
本発明の目的は上述の問題点に鑑み、溝のシリコン表面
の汚染層及び損傷層が効果的に除去でき、シリコン表面
に形成される素子の特性が向上できる半導体装置の製造
方法を提供するものである。SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that can effectively remove the contamination layer and damaged layer on the silicon surface of the trench and improve the characteristics of elements formed on the silicon surface. It is.
本発明は上述した目的を達成するため、異方性ドライエ
ツチングにより基板上に溝を形成する工程と、急速熱処
理装置を用い、高温且つ短時間の急速熱処理を行ない、
上記溝のエツチング面に犠牲熱酸化膜を形成する工程と
、上記急速熱処理装置を用い、上記犠牲熱酸化膜を、急
速熱処理により還元して除去する工程と、上記急速熱処
理装置を用い、上記溝の表面に絶縁膜を形成する工程と
を含むものである。In order to achieve the above-mentioned object, the present invention includes a process of forming grooves on a substrate by anisotropic dry etching, and rapid heat treatment at high temperature and in a short time using a rapid heat treatment apparatus.
a step of forming a sacrificial thermal oxide film on the etched surface of the groove; a step of reducing and removing the sacrificial thermal oxide film by rapid thermal processing using the rapid thermal processing apparatus; The method includes a step of forming an insulating film on the surface of the substrate.
本発明においては、犠牲熱酸化膜は急速熱処理により形
成されるので、基板内への汚染層の拡散が抑制される。In the present invention, since the sacrificial thermal oxide film is formed by rapid thermal processing, diffusion of the contaminant layer into the substrate is suppressed.
更に、犠牲熱酸化膜は、高温熱処理による粘性流動によ
りストレスが緩和され、均一膜厚に形成される。又、犠
牲熱酸化膜は急速熱処理による拡散係数の増大により薄
膜に形成される。更に又、犠牲熱酸化膜の除去工程及び
絶縁膜の形成工程が同一装置内で連続して行なわれるの
で、シリコン表面の大気接触等による自然酸化膜の形成
が防止される。更に、犠牲熱酸化膜は均一の薄膜に形成
されるので、トレンチ形状の変形が防止される。Further, the stress of the sacrificial thermal oxide film is alleviated by viscous flow caused by high-temperature heat treatment, and the film is formed to have a uniform thickness. Further, the sacrificial thermal oxide film is formed into a thin film due to an increase in the diffusion coefficient due to rapid heat treatment. Furthermore, since the step of removing the sacrificial thermal oxide film and the step of forming the insulating film are carried out consecutively in the same apparatus, the formation of a natural oxide film on the silicon surface due to contact with the atmosphere or the like is prevented. Furthermore, since the sacrificial thermal oxide film is formed into a uniform thin film, deformation of the trench shape is prevented.
本発明方法の一実施例を第１図乃至第４図に基づいて説
明する。尚、第１図は工程図、第２図は急速熱処理装置
の構成図、第３図はＳＩＭＳによるＦ原子の濃度プロフ
ァイル特性図、第４図はトレンチの断面図である。An embodiment of the method of the present invention will be described based on FIGS. 1 to 4. In addition, FIG. 1 is a process diagram, FIG. 2 is a block diagram of a rapid heat treatment apparatus, FIG. 3 is a characteristic diagram of F atom concentration profile obtained by SIMS, and FIG. 4 is a cross-sectional view of a trench.
先ず、第１図（ａｔに示すように、電気炉を用い、１０
００℃の乾燥した酸素雰囲気中で熱酸化を行ない、抵抗
率が１〜２０Ω・１のＰ型シリコン基板２１上に１００
０〜５０００人厚のシリコン酸化膜２２を形成する。次
に、このシリコン酸化膜２２上にレジスト２３を約１μ
厚スピンコーテイングする。続いて、ホトリソグラフィ
ーによりレジスト２３をバターニングする。この場合、
将来トレンチとなる部分のパターニング巾は、例えば０
．５〜１．５ｐｍとする。又、上記シリコン酸化膜２２
は化学気相成長法（ＣＶＤンによって形成しても良い。First, as shown in Figure 1 (at), using an electric furnace,
Thermal oxidation is carried out in a dry oxygen atmosphere at 00°C, and 100%
A silicon oxide film 22 having a thickness of 0 to 5,000 layers is formed. Next, a resist 23 of about 1 μm is applied on this silicon oxide film 22.
Thick spin coating. Subsequently, the resist 23 is patterned by photolithography. in this case,
The patterning width of the part that will become a trench in the future is, for example, 0.
．． 5 to 1.5 pm. Moreover, the silicon oxide film 22
may be formed by chemical vapor deposition (CVD).
その後、第１図（ｂｌに示す如く、反応性イオンエツチ
ング（ＲＩ Ｒ）によりレジスト２３をマスクにして、
シリコン酸化膜２２をエンチングする。Thereafter, as shown in FIG. 1 (bl), the resist 23 is used as a mask by reactive ion etching (RIR).
The silicon oxide film 22 is etched.
その後、０□アフシング及び硫酸通水によりレジスト２
３を除去する。After that, resist 2 is applied by 0□afthing and passing sulfuric acid.
Remove 3.
次いで、第１図１０１に示すように、ＲＩＥ法によりシ
リコン酸化膜２２をマスクにして、例えば５ｒＣ１，、
ＣＣ１，又はＣＣＩ！Ｆｔ等の塩素を含んだガス若しく
はこのＣｔ系ガスとＯ！又はＮｔ等の混合ガスを用いて
、基板２１を異方性エツチングして、３〜５ ／Ｉ＠の
深さの溝２４を形成する。このとき、？ａ ２４のシリ
コン表面２４ａには、エツチングガスとシリコンとの反
応生成物が汚染層２５として蓄積すると共に、エツチン
グ時の損傷層２６が生じる。Next, as shown in FIG. 1 101, using the silicon oxide film 22 as a mask, for example, 5rC1, .
CC1 or CCI! A gas containing chlorine such as Ft or this Ct-based gas and O! Alternatively, the substrate 21 is anisotropically etched using a mixed gas such as Nt to form the groove 24 with a depth of 3 to 5/I@. At this time,? A reaction product between the etching gas and silicon accumulates as a contamination layer 25 on the silicon surface 24a 24, and a damaged layer 26 is generated during etching.
その後、第１図１０１に示すように、溝２４のシリコン
表面２４ａをＯ！アッシング又は酸・アルカリ処理する
０次に、後述する急速熱処理装置を用い、Ｏｔ雰囲気中
において、基板２１を例えば１００℃／ｗｉｎＯ昇温速
度で１１００℃迄昇温し、３分間の急速熱処理を行ない
、溝２４のシリコン表面２４ａに１００〜５００人厚の
熱酸化膜２７を被着形成する。このとき同時に、汚染層
２５は熱酸化膜２７中に拡散し、損傷層２６はアニール
効果により消滅する。Thereafter, as shown in FIG. 1 101, the silicon surface 24a of the groove 24 is heated to O! Ashing or acid/alkali treatment Next, the substrate 21 is heated to 1100° C. at a heating rate of 100° C./winO in an Ot atmosphere using a rapid thermal processing device described later, and rapid thermal processing is performed for 3 minutes. A thermal oxide film 27 having a thickness of 100 to 500 layers is deposited on the silicon surface 24a of the groove 24. At the same time, the contaminant layer 25 diffuses into the thermal oxide film 27, and the damaged layer 26 disappears due to the annealing effect.
次に、第１図（ｅｌに示すように、同一の急速熱処理装
置を用い、Ｃｒｔ雰囲気中において、基板２１を１００
℃／ｓｉｎの昇温速度で１０００℃迄昇温し、２０秒間
加熱し、この工程で熱酸化膜２７の大部分を除去する。Next, as shown in FIG. 1 (el), the substrate 21 was heated at
The temperature is increased to 1000° C. at a temperature increase rate of° C./sin and heated for 20 seconds, and most of the thermal oxide film 27 is removed in this step.
Ｖｔいて、同じく急速熱処理装置を用い、Ｈ！雰囲気中
において、基板２１を１００’Ｃ／腸ｉｎの昇温速度で
１０００℃迄昇温し、約３０秒間加熱する。これによっ
て、残存する熱酸化膜２７はｈガスにより還元され、全
て除去される。Vt, using the same rapid heat treatment equipment, H! In an atmosphere, the temperature of the substrate 21 is increased to 1000° C. at a rate of 100° C./in, and heated for about 30 seconds. As a result, the remaining thermal oxide film 27 is reduced by the h gas and is completely removed.
このとき、汚染層２５も熱酸化膜２７と共に完全に除去
され、清浄化されたシリコン表面２４ａが得られる。斯
くして、トレンチが完成する。At this time, the contaminant layer 25 is also completely removed together with the thermal oxide film 27, and a cleaned silicon surface 24a is obtained. In this way, the trench is completed.
しかる後、第１図（「）に示すように、同一急速熱処理
装置内の０３雰囲気を１００℃／ｓｉｎの昇温速度で１
１００℃迄昇温した後、熱処理を行ない、溝２４を含む
基板２１表面に酸化膜２８を被着形成する。この場合、
急速熱処理装置内の反応ガス交換は真空中で行なわれる
。以後、周知技術によりトレンチ素子が形成される。Thereafter, as shown in Figure 1 (), the 03 atmosphere in the same rapid heat treatment equipment was heated at a temperature increase rate of 100°C/sin.
After raising the temperature to 100° C., heat treatment is performed to form an oxide film 28 on the surface of the substrate 21 including the grooves 24. in this case,
Reactant gas exchange within the rapid thermal processing apparatus takes place in a vacuum. Thereafter, trench elements are formed using well-known techniques.
次に、第２図を参照してかかる急速熱処理装置について
述べる。Next, such a rapid heat treatment apparatus will be described with reference to FIG.
即ら、３１は反応炉であり、この反応炉３１は反応炉本
体３１ａと蓋部３１ｂとから成っている。That is, 31 is a reactor, and this reactor 31 consists of a reactor main body 31a and a lid part 31b.
反応炉本体３１ａは断面Ｕ字形を呈し、側部に反応ガス
のガス供給部３２が連結されると共に、底部に不要ガス
を排気するための真空排気装置３３が連結されている。The reactor main body 31a has a U-shaped cross section, and a gas supply section 32 for a reaction gas is connected to the side thereof, and a vacuum evacuation device 33 for exhausting unnecessary gas is connected to the bottom thereof.
上記蓋部３１ｂは赤外線を容易に透過する石英材から成
り、反応炉本体３１ａの上部開口部３１ｃに冠着されて
いる。そして、これら反応炉本体３１ａと蓋部３１ｂと
で密閉された反応室３１ｄが形成されている。更に、蓋
部３１ｂの上方には複数のタングステンハロゲンランプ
３４を規則正しく配列し、これらタングステンハロゲン
ランプ３４は反応炉本体３１ａ上部に固定されたランプ
支持体３５によって支持されている。又、反応炉本体３
１ａの底面上には、基板２１を支持するウェハ支持体３
６及び基板２１の温度を検知するオプティカルパイロメ
ータ３７が夫々装着されている。The lid portion 31b is made of a quartz material that easily transmits infrared rays, and is attached to the upper opening 31c of the reactor main body 31a. A sealed reaction chamber 31d is formed by the reactor main body 31a and the lid portion 31b. Further, a plurality of tungsten halogen lamps 34 are regularly arranged above the lid part 31b, and these tungsten halogen lamps 34 are supported by a lamp support 35 fixed to the upper part of the reactor main body 31a. In addition, the reactor main body 3
On the bottom surface of 1a is a wafer support 3 that supports the substrate 21.
6 and an optical pyrometer 37 for detecting the temperature of the substrate 21, respectively.
従って、かかる装置では、反応室３１ｄ内において、ガ
ス供給部３２から供給される反応ガスを用い、タングス
テンハロゲンランプ３４から発する赤外線を加熱源とし
て、基板２１が熱処理される。そして、熱処理後の不要
ガスは真空排気装置３３により反応室３１ｄ外部に真空
排気される。Therefore, in this apparatus, the substrate 21 is heat-treated in the reaction chamber 31d using the reaction gas supplied from the gas supply section 32 and the infrared rays emitted from the tungsten halogen lamp 34 as a heat source. Then, the unnecessary gas after the heat treatment is evacuated to the outside of the reaction chamber 31d by the evacuation device 33.
よって、本発明のトレンチ形成法によれば、急速熱処理
装置を用い、高温急速酸化により溝２４のシリコン表面
２４ａに犠牲熱酸化膜２７を短時間で形成するので、第
３図に示すように、基板２１へのＦ原子等の汚染層２５
の拡散が抑制されると共に、犠牲熱酸化膜２７の拡散係
数が大きくなる。よって、犠牲熱酸化膜２７は薄膜に形
成でき、汚染層２５及びｔ員傷Ｊｉ２６は犠牲熱酸化膜
２７と共に確実に除去される。更に、高温熱処理による
粘性流動によりストレスが緩和するので、第４図に示す
ように、犠牲熱酸化膜２７は均一膜厚に形成され、而も
薄膜であるため、トレンチ形状の変形が防止できる。又
、酸化膜２８は犠牲熱酸化膜２７の除去工程に続いて同
一装置内で形成されるので、シリコン表面２４ａを含む
基板２１表面は大気に接触することはない。よって、基
板２１表面での自然酸化膜の形成が防止できる。Therefore, according to the trench forming method of the present invention, the sacrificial thermal oxide film 27 is formed on the silicon surface 24a of the trench 24 in a short time by high-temperature rapid oxidation using a rapid thermal processing apparatus, so that as shown in FIG. Contamination layer 25 of F atoms etc. on the substrate 21
At the same time, the diffusion coefficient of the sacrificial thermal oxide film 27 increases. Therefore, the sacrificial thermal oxide film 27 can be formed into a thin film, and the contamination layer 25 and the T-shaped scratches Ji 26 are reliably removed together with the sacrificial thermal oxide film 27. Furthermore, since the stress is alleviated by the viscous flow caused by the high-temperature heat treatment, the sacrificial thermal oxide film 27 is formed to have a uniform thickness as shown in FIG. 4, and since it is a thin film, deformation of the trench shape can be prevented. Further, since the oxide film 28 is formed in the same apparatus following the step of removing the sacrificial thermal oxide film 27, the surface of the substrate 21 including the silicon surface 24a does not come into contact with the atmosphere. Therefore, formation of a natural oxide film on the surface of the substrate 21 can be prevented.
〔発明の効果〕
以上説明したように本発明によれば、高温で短時間の急
速熱処理により溝のシリコン表面に犠牲熱酸化膜を形成
するので、基板内への汚染層の拡散が抑制でき、逆に、
同酸化膜の拡散係数は太き（なる、このため、犠牲熱酸
化膜は薄膜に形成でき、汚染層はこの犠牲熱酸化膜と共
に確実に除去できる。更に、高温熱処理により薄膜の犠
牲熱酸化膜は均一膜厚に形成されるため、トレンチ形状
の変形が防止できる。又、犠牲熱酸化膜及び素子の構成
部となる酸化膜の形成が、同一装置内ご連続的に行なわ
れるので、溝を含む基板表面の大気接触による自然酸化
膜の形成が防止できる。従って、これらによりトレンチ
素子の容！変動及び耐圧不良が防止できる他、絶縁特性
が向上でき、十分な素子特性が得られる等の特有の効果
により上述の課題を解決し得る。[Effects of the Invention] As explained above, according to the present invention, since a sacrificial thermal oxide film is formed on the silicon surface of the trench by rapid heat treatment at high temperature for a short time, the diffusion of the contaminant layer into the substrate can be suppressed. vice versa,
The diffusion coefficient of the oxide film is large (because of this, the sacrificial thermal oxide film can be formed into a thin film, and the contamination layer can be reliably removed together with this sacrificial thermal oxide film. Furthermore, by high-temperature heat treatment, a thin sacrificial thermal oxide film can be formed. Since the film is formed to have a uniform thickness, deformation of the trench shape can be prevented.Furthermore, since the sacrificial thermal oxide film and the oxide film that will become the component parts of the element are formed continuously in the same equipment, the trench can be easily formed. This prevents the formation of a natural oxide film due to contact with the atmosphere on the surface of the substrate containing the substrate.Therefore, these can prevent variations in the capacitance and breakdown voltage of the trench element, as well as improve insulation properties and provide sufficient element characteristics. The above-mentioned problem can be solved by this effect.
第１図乃至第４図は本発明方法に係わる実施例を示すも
ので、第１図は工程図、第２図は急速熱処理装置の構成
図、第３図はＦ原子の濃度プロファイル特性図、第４図
はトレンチの断面図、第５図乃至第７図は従来例を示す
もので、第５図は工程図、第６図はＦ原子の濃度プロフ
ァイル特性図、第７図はトレンチの断面図である。
２１・・・Ｐ型シリコン基板、２２・・・シリコン酸化
膜、２３・・・レジスト、２４・・・溝、２４ａ・・・
シリコン表面、２５・・・汚染層、２６・・・損傷層、
２７・・・犠牲熱酸化膜、２８・・・酸化膜。
第７図
本を明号店で工程図
第１図
魁【部畑揺褒１゜積爪図
第２図1 to 4 show an example of the method of the present invention, in which FIG. 1 is a process diagram, FIG. 2 is a configuration diagram of a rapid heat treatment apparatus, and FIG. 3 is a concentration profile characteristic diagram of F atoms. Figure 4 is a cross-sectional view of the trench, Figures 5 to 7 show conventional examples, Figure 5 is a process diagram, Figure 6 is a characteristic diagram of F atom concentration profile, and Figure 7 is a cross-section of the trench. It is a diagram. 21... P-type silicon substrate, 22... silicon oxide film, 23... resist, 24... groove, 24a...
Silicon surface, 25... Contaminated layer, 26... Damaged layer,
27... Sacrificial thermal oxide film, 28... Oxide film. Fig. 7 The book was sold at the Meigo store.Process diagram Fig. 1
Claims (1)
程と、 急速熱処理装置を用い、高温且つ短時間の急速熱処理を
行ない、上記溝のエッチング面に犠牲熱酸化膜を形成す
る工程と、 上記急速熱処理装置を用い、上記犠牲熱酸化膜を、急速
熱処理により還元して除去する工程と、上記急速熱処理
装置を用い、上記溝の表面に絶縁膜を形成する工程とを
含むことを特徴とする半導体装置の製造方法。[Claims] A process of forming a groove on a substrate by anisotropic dry etching, and performing rapid heat treatment at a high temperature and in a short time using a rapid heat treatment apparatus to form a sacrificial thermal oxide film on the etched surface of the groove. a step of reducing and removing the sacrificial thermal oxide film by rapid thermal processing using the rapid thermal processing device; and a step of forming an insulating film on the surface of the groove using the rapid thermal processing device. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1035054A JPH02215125A (en) | 1989-02-16 | 1989-02-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1035054A JPH02215125A (en) | 1989-02-16 | 1989-02-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02215125A true JPH02215125A (en) | 1990-08-28 |
Family
ID=12431324
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1035054A Pending JPH02215125A (en) | 1989-02-16 | 1989-02-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02215125A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100335122B1 (en) * | 1999-09-10 | 2002-05-04 | 박종섭 | Isolation method for semiconductor device |
| KR100367405B1 (en) * | 2000-06-29 | 2003-01-10 | 주식회사 하이닉스반도체 | Method For Manufacturing The Wafer |
| JP2004327644A (en) * | 2003-04-24 | 2004-11-18 | Fuji Electric Device Technology Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2007165925A (en) * | 1997-12-02 | 2007-06-28 | Toshiba Corp | Manufacturing method of semiconductor device |
| US8963205B2 (en) | 2007-11-09 | 2015-02-24 | SK Hynix Inc. | Method for fabricating a semiconductor device |
-
1989
- 1989-02-16 JP JP1035054A patent/JPH02215125A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007165925A (en) * | 1997-12-02 | 2007-06-28 | Toshiba Corp | Manufacturing method of semiconductor device |
| KR100335122B1 (en) * | 1999-09-10 | 2002-05-04 | 박종섭 | Isolation method for semiconductor device |
| KR100367405B1 (en) * | 2000-06-29 | 2003-01-10 | 주식회사 하이닉스반도체 | Method For Manufacturing The Wafer |
| JP2004327644A (en) * | 2003-04-24 | 2004-11-18 | Fuji Electric Device Technology Co Ltd | Semiconductor device and method of manufacturing the same |
| US8963205B2 (en) | 2007-11-09 | 2015-02-24 | SK Hynix Inc. | Method for fabricating a semiconductor device |
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