JPH022157A - semiconductor element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to semiconductor devices, and particularly relates to high-speed bipolar transistors, and provides a semiconductor device that can operate at high speed by reliably discharging the charges accumulated in the base-collector junction capacitance during switching operations. With the purpose of providing bipolar transistors,
MOS FET, the source electrode of the MO8FET is connected to the base electrode of the bipolar transistor, the drain electrode of the MO3FE'I' is connected to the emitter electrode of the bipolar transistor, and the source electrode of the MO8FET is connected to the base electrode of the bipolar transistor;
The gate electrode of O3FE'f' is connected to the base electrode of the bipolar transistor, and the MOSFE'f' is connected to the base electrode of the bipolar transistor.
The substrate portion of the T is connected to the collector electrode of the bipolar I transistor.

[Industrial application field]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to high-speed piborar transistors.

With the recent increase in the amount of information and the increasing density of information,
Transistors used in various electronic devices are required to have high speed. Bipolar transistor itself is MOS
Although they are superior in high speed compared to FETs, they are still far from being sufficient, and various improvements have been made to increase speed.

[Conventional technology]

TTL (Transistor Transistor) using a bipolar transistor as an output buffer circuit.
stor Logic) is used. FIG. 7 shows an explanatory diagram of a general npn type bipolar transistor. This bipolar!・The collector-emitter voltage VCESζ of transistor Q is expressed as ``VBE 'BC''' (1). Here, VB2: 'Base-emitter voltage, VB
c: Base-collector voltage.

Since the 'T'TL circuit operates this bipolar transistor Q in a deep saturation region, it has the disadvantage that the switching time is slow. When operated in the saturation region, the base
This is because the time required for charging and discharging excess minority carriers to the collector junction capacitance becomes longer.

Therefore, as an example of increasing the speed of the bipolar transistor Q by preventing it from entering the deep saturation region, a Schottky barrier diode (SBD: 5chottky Ba
Schottky transistors (so-called Schottky transistors) are known. An example of this is shown in Figure 8. As shown in Figure 8, the base and collector of the bipolar transistor Q are connected in the forward direction by an SBD to clamp the forward voltage VBo between the base and collector. be. According to this circuit, the forward voltage drop V of SBD is lower than the base-collector voltage VBc (about 0.6 V) of the bipolar transistor Q.

(approximately 0.4V) is lower, so the excess base current is
It can be bypassed by the BD, and therefore does not enter a deep saturation region, making high-speed operation possible.

[Problem to be solved by the invention]

The above-mentioned Schottky transistor can achieve much higher speed than a simple bipolar transistor. However, as is the case with semiconductor devices in general, complete high-speed operation cannot be guaranteed in a high-temperature environment.
... is expressed as (2). Here, V is the forward voltage drop of the SBD. As the temperature rises, the base-emitter voltage VB[ becomes smaller, and the base-emitter voltage VCES also becomes smaller. This means that the cut-off of the bipolar transistor Q becomes slower at high temperatures, and the drawback of temperature characteristics still remains.

The above problem becomes more serious in the case of a large-capacity bipolar transistor because the base-collector junction capacitance becomes large.

In addition, in order to increase the speed, it is known that the operation of an npn bipolar transistor is controlled by each gate of a MOS FET and a junction type FET (Japanese Patent Laid-Open No. 57
-186833).

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can operate at high speed by reliably discharging the charges accumulated in the base-collector junction capacitance during switching operations.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention is characterized in that a bipolar transistor is combined with a MOS FEi' so that the accumulated charge in the base-collector junction capacitance is rapidly discharged at turn-off.

FIG. 1 shows a diagram explaining the principle of the present invention. An npn-type bipolar transistor (hereinafter simply referred to as a transistor) Q as a first conductivity type, and a p-channel type MOS FE'l' (hereinafter simply referred to as a MOS transistor) PM as a second conductivity type. configured.

MOS) The source S of the transistor PM is the transistor Q
is connected to base B of MOS transistor PM
The drain D of the 0M0S transistor PM is connected to the emitter E of the transistor Q, and the gate G of the 0M0S transistor PM is connected to the base B of the transistor Q. And MoS
A substrate portion (hereinafter referred to as back channel) SUB of the transistor PM is connected to the collector of the transistor Q. Note that the above configuration is based on 11 p as the first conductivity type.
Although the combination of the n-type transistor Q and the ρ-channel type MO3I-transistor PM as the second conductivity type is shown, this combination is reversible, and a combination of a pnpl-transistor and an n-channel MOS transistor may be used. .

Cfi′, for] Next, the effect will be explained.

In FIG. 1, when transistor Q is turned on,
The base-emitter voltage of base B■BE is °'II”
level, and collector C becomes "L" level. At this time, the gate G of MO3I-transistor PM also goes to H" level, and since it is a p-channel type, MOS transistor PM is turned off. The potential of back channel SUB is also at "L" level.

Next, when a "1-" level is applied to the base B to turn off the transistor Q, the collector C rises to the "tobi" level. When rising from this "L" level to the "H" level, the MOS transistor PM turns off. Turn off transiently. This means that the Mos transistor PM has reached the "L" level by 11 relative to the gate G, and the MO3+- transistor PM is turned on. As a result, transistor Q
The charge accumulated in the base-collector junction capacitance of G
released into ND. Thereafter, the potential of the back channel SUB rises sufficiently and the M OS +- transistor PM is turned off.

In this way, when the transistor Q changes from ON to OFF, the MO3I-transistor PM is turned ON by the "I" level of the collector C, and the m charge accumulated in the base-collector junction capacitance can be discharged, so that the excess minority carriers can be discharged. It is possible to prevent the delay in turn-off time caused by the presence of the metal and to speed up the turn-off time.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

The basic circuit configuration of the semiconductor device according to the present invention is as shown in FIG. 1, and the connection relationship is as explained above, so FIG. 1 and its explanation will be used as reference. Therefore, the explanation here will be omitted, and the structure will be explained below.

1 ~ Structure of transistor When forming a bipolar transistor on an IC substrate,
Is it necessary to electrically isolate adjacent transistors from each other? This electrical isolation is performed by an isolation region. There are various types of 4111 structures in the isolation region, but here, the structure of the transistor of the present invention will be explained using an example of an oxide film isolation type transistor and an example of a PN junction isolation type transistor.

FIG. 2 shows a cross-sectional view of an oxide film isolation type (deep groove isolation type) npn bipolar transistor. As shown in Figure 2,
Isolation regions 2 and 3 are formed in the p-substrate 1 in the form of deep grooves. The isolation regions H2 and H3 are formed of polysilicon PSi inside and silicon oxide 5IO2 surrounding it. An n + buried layer 5 is formed in an n epitaxial land 4 formed by two isolation regions 2 and 3 . moreover,
In the n- epitaxial land 4, from the left side in the figure, a drain D and a gate G of the p diffusion region are formed.

A source S (base B) of the P+ diffusion region, an emitter E of the n+ diffusion region, and a collector C of the n′ diffusion region are formed, respectively.

In the above structure, the base B, emitter E, and collector C constitute a bipolar transistor Q.

In addition, the drain D, gate G and source S provide MO
The base B region of the transistor Q and the source S of the MOS transistor PM use the same P+ diffusion region, so the base B and the sort S In addition, since the n4 buried layer 5 extends directly under the gate G, the back channel SUh
is formed. Since the n+ buried layer 5 is the same conductive layer as the collector C, it is equivalent to the collector C and back channel SUB being substantially connected. Therefore, the circuit shown in FIG. 1 can be realized by connecting the gate G and the base B by A (wiring, etc.).

In this way, the bipolar transistor Q and the MOS1-transistor PM can be formed in the same epitaxial land in the circuit state shown in FIG.

Next, the operation will be explained.

“L” from the turn-on state to the base B of transistor Q
When a base voltage of this level is applied, transistor Q turns off. Then, the collector C rises from the "L" level to the "H" level. The voltage from this “L” level to the “)” level is applied to the back channel SU through the n+ buried layer 5.
The potential of B is also changed from "L" level to "H" level. Then, when the potential of the back channel SUB is at "L" level, a channel is formed between the back channel SUB and the gate G, and the MOS transistor PM is turned on.
The charges accumulated in the base-collector junction capacitance are extracted to GND through the drain D. in this way,
Since the charge in the base-collector junction capacitance can be discharged following the turn-off of the transistor Q, the turn-off time of the transistor Q can be shortened. the result,
As shown in FIG. 4, the rising waveform of the output voltage of the transistor Q is improved. In the figure, 100 is the case of the present invention and 200 is the conventional case.

Next, FIG. 3 shows a cross-sectional view of a PN junction G-type npn bipolar transistor. This PN junction isolated transistor differs from the oxide film isolated transistor shown in FIG. 2 in the isolation region.

That is, an isolation region 6.7 formed by a P+ diffusion region is diffused into the n 2 epitaxial growth layer to form an n 2 epitaxial land 4. An n+ buried layer 5 is buried in the n epitaxial land 4, and a gate G is further formed on the n+ buried layer 5.

A source S (base B) of the P+ diffusion region, an emitter E of the n+ diffusion region, and a collector C of the n+ diffusion region are formed. Isolation m 1 adjacent to gate G! U6
forms the drain D.

In the above structure, the base B (source S), emitter E, and collector C constitute a bipolar transistor Q. Furthermore, a drain D, a gate G, and a source S constitute a MOS transistor PM. Here, since the base B region of the transistor Q and the source S of the MOS transistor PM use the same P+ diffusion region, the base B and the source S are equivalent to being substantially connected. In addition, since the n'' buried layer 5 extends directly below the gate, a back channel SUB is formed in this portion, and this is equivalent to the fact that the collector C and the back channel SUB are substantially connected here. Therefore, in this case as well, the circuit shown in FIG. 1 can be realized by coupling the gate G and base B by A, 11 wiring, etc.

The operation is the same as the example in Figure 2, so the explanation will be omitted, but in the case of this embodiment, at the rise of the output voltage waveform of the transistor Q, an undershoot occurs due to the PN junction between the drain D of the MOS transistor PM and the back channel SUB. As shown in FIG. 5, the falling waveform is improved. In FIG. 5, 100 is the case of the present invention and 200 is the conventional case.

FIG. 6 shows an example of an 'f' T L circuit using the above semiconductor element, that is, a bipolar transistor with MO3FET, in which the transistor Q is used as an output transistor.

The TTL circuit includes a timing adjustment circuit 8 and an off-buffer transistor Q. ff and output transistors Q and M
It consists of an OS transistor PM.

The timing adjustment circuit 8 includes three stages of CMOS transistors CM, CM, and CM3, including a third buffer transistor Q. ff and the output transistor Q, and also adjusts the timing of applying the gate voltage to the gate G of the MO3I transistor PM.
Depending on circuit characteristics such as circuit current and parasitic capacitance, the gate of the MOS transistor PM is connected to the base B of the output transistor Q as shown by the solid line, or to the connection point of the first stage CMOS transistor CM1 as shown by the broken line. Wire. Since the OFF timing differs depending on the circuit, the A is adjusted appropriately according to the circuit used.

Off-buffer transistor Q. ff is transistor Q1
and Q2, the collector of the output transistor Q is connected to the emitter of the transistor Q2, and its emitter is connected to GND. The connection between transistor Q1 and MOS transistor PM is as described above.

In the above circuit, when the input signal (■) and the "I" level are applied to the input terminal IN, the output of the first stage CMO3)-transistor CM1 is "L" level, and the output of the second stage CMOS transistor CM2 is " H” level, 3rd stage CMO
The output of the S transistor CM3 is applied to the base B of the output transistor Q at "L" level, and the output transistor Q is turned off. At this time, the output signal V of the output terminal OUT. ut changes from "L" level to "H" level. Following this “H” level, the MOS transistor P
The potential of the M back channel 5UI3 also changes from the "HI" level to the "TR" level, and the MOS transistor PM is turned on transiently.

As a result, the accumulated charge at the base-collector junction of the output transistor Q is discharged, and the output transistor Q is turned off at high speed. When the input signal V, or n is at "L" level, it is sufficient to consider the level opposite to the above.

〔Effect of the invention〕

As described above, according to the present invention, the second conductive type MO3F attached to the first conductive type bipolar transistor follows the signal change at the output terminal of the first conductive type bipolar transistor.
By changing the substrate potential of E'r'', the accumulated charge in the base-collector junction capacitance of the bipolar transistor can be discharged, so even if the bipolar transistor is operated in saturation, high-speed switching operation is possible. can.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a cross-sectional view of an oxide film-separated npn bipolar transistor, Fig. 3 is a signal rise characteristic diagram in the case of Fig. 2, and Fig. 4 is a P
5 is a signal fall characteristic diagram for the case of FIG. 4, and FIG. 6 is a circuit diagram showing an example of application of the present invention to a T'I'L circuit. , FIG. 7 is an explanatory diagram of an npn type bipolar transistor, and FIG. 8 is an explanatory diagram of a Schottky bipolar transistor. Q: bipolar transistor, PM: p-channel MOSFET, C: collector, B: base, E: emitter, S: source, G: gate, D... drain. 25 Figure 5 Figure 6

Claims (1)

[Claims] Comprising an npn-type bipolar transistor (Q) and a p-channel type MOSFET (PM), the MOSFET
The source electrode (S) of the MOSFET (PM) is connected to the base electrode (B) of the bipolar transistor (Q), and the drain electrode (D) of the MOSFET (PM) is connected to the emitter electrode (E) of the bipolar transistor (Q). ), the gate electrode (G) of the MOSFET (PM) is connected to the base electrode (B) of the bipolar transistor (Q), and the substrate part (SUB) of the MOSFET (PM) is connected to the bipolar transistor (Q). ) A semiconductor device characterized in that it is connected to a collector electrode (C) of a semiconductor device.