JPH02246138A - Semiconductor device - Google Patents

Abstract

PURPOSE:To install a logic library on a master chip in a channelfree wiring system without a need for a separate power-supply wiring part by a method wherein a power-supply line extended to nearly the center of a library cell from a power-supply wiring part feeding a power supply is installed at the library cell. CONSTITUTION:In addition to power-supply wiring parts 20 used to supply a power supply to library cells 32 constituted of fundamental cells 15A, 15B, power-supply lines (22A, 22B) 22 extended to nearly the center of the library cells 32 from the power-supply wiring parts 20 used to supply power supplies Vdd, Vss are installed, at the individual library calls 32, at a lower-side end part of the power-supply wiring parts 20. Accordingly, when the library cells 32 are arranged in a channelfree manner and the library cells are arranged so as to be shifted by one piece of said fundamental cells 15A, 15B, the power- supply lines 22 are connected to one out of the power-supply wiring parts 20 via connection parts 23A, 23B. Thereby, when the library cells are arranged in a channelfree manner, it is not required to install a separate power-supply wiring part.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a semiconductor device, and more particularly, it is formed from a group of MOS transistors of a first conductivity type and a group of MOS transistors of a second conductivity type, each transistor group having a source region and a gate electrode. A Sea Of Ga cell has a plurality of basic cells arranged in a symmetrical shape with respect to a line crossing the drain region, and these basic cells constitute a library cell that emits a predetermined tS ability.
The present invention relates to a tes type master type star slice type device.

[Conventional technology]

Conventionally, various master slice type semiconductor devices having gate arrays have been developed and put into practical use, and the one shown in FIG. 3 is known as the semiconductor device. Reference numeral 1 in FIG. 3 indicates a master chip. As shown in FIG. 3, on this master chip 1, a plurality of basic cell rows 2 as a logic creation section are arranged in a wiring area where wiring for connecting between the basic cell rows 2.2 is installed. 3 in the row direction (horizontal direction). As shown in FIG. 4(A), this basic cell row 2 includes a first transistor pair consisting of P-channel MOS transistors 4A and 4B, and an N-channel MO8 transistor 5.
Basic cells 6 each having a second transistor pair consisting of transistors A and 5B are arranged in one row in the column direction (vertical direction). In addition, in Fig. 4 (A) and (B), the solid line (-)
(Symbol 7) is the IFwth aluminum (Aλ) wiring, 8
A, 8B, and 8C are the Ai wirings of the second layer, x marks 9 are contacts to the source, drain, and gate of the Ai wiring 7 of the first layer, and O marks 10 are the contacts of the A1 wirings 7 of the first layer and the 2 This is a contact with the Ai wirings 8A to 8C in the second layer. Further, GA is the transistor 4 in the first and second transistor pair.
This is a gate electrode made of polycrystalline silicon for each of transistors A and 5A, and is common to transistors 4A and 5A. Further, GAI and GA2 are gate electrodes of transistors 4B and 5B. Further, the basic cell 6 is, for example, shown in FIG. 4 (
As shown in B), a two-person NAND circuit is constructed. Currently, when developing semiconductor devices using the mask slicing method as described above, logic such as NAND and NOR (hereinafter referred to as a library that constitutes the logic) is determined by the master chip and the wiring pattern overlaid on it (prepared as library data). A unit called a library cell) is prepared for the user. However, the conventional semiconductor device having the structure shown in FIG. 3 had the following drawbacks. One of the drawbacks is that there is a lot of wasted area within the wiring area 3 that is not used. That is, the basic cell 6 has the first transistor pair and the second transistor pair as a set. Therefore, NOR, NAN
Logic gates such as D can only be configured within the basic cell column 2, and a wiring area 3 is required to make connections between each basic cell column 2. Normally, the wiring in this wiring area 3 is The number of channels is determined in consideration of the need for a large number of wiring lines, so the wiring area 3 requires a relatively large area. Therefore, when producing a product Wi from the semiconductor device shown in FIG.
This results in a wasted area that does not actually contribute to wiring. Another drawback is that in the semiconductor device, the numbers of basic cell rows 2 and 6 are predetermined, resulting in a system that cannot be realized physically. be. In addition, for such drawbacks, master chip 1
It is conceivable to increase the number of basic cells 6 by increasing the area of , but in this case, the wiring area between the basic cell rows 2... will also increase at the same time, making the master chip 1 larger than necessary. It ends up. To address the above-mentioned drawbacks, Japanese Patent Laid-Open No. 59-44859 discloses a basic cell constituting a master slice type semiconductor device. As shown in FIG. 5, the technique disclosed in the above-mentioned publication is such that basic cells are sequentially arranged side by side as basic cell rows 13A and 13B on the master chip 10 without interruption.
As shown in FIG. 6, the gate electrodes are separated from each other.
First conductivity type transistor group (first basic cell) 1 consisting of P-channel MO8 type transistors 14A and 14B
5A and N channel MO3 type transistors 16A, 16
A second conductivity type transistor group (second basic cell) 15B consisting of B is formed, and each basic cell 15A, 15B is aligned left and right with center lines A, B crossing the source region, gate electrode, and drain region. By having a symmetrical structure, the first basic cell 15A and the second basic cell 1
5B can be used either left or right (for example, if the left and right sides are reversed, the library data is used upside down).
The second basic cells 15A and 15B are formed without exception, and the fifth
As shown by reference numeral 12 in the figure, the wiring area can be placed at a desired position at 1/2 the pitch of the conventional basic cell having P-channel and N-channel, and the basic cell row that becomes the logic creation section can be placed at a desired position. It can be installed in any desired area. Furthermore, when designing a master chip, the possibility that the system that can be realized is determined by the size of the master chip is minimized. Note that the above-mentioned publication also discloses a technique in which pairs of P-channel and N-channel transistors are arranged in order to form a cell row. However, when the basic cells are arranged in a straight line to form a cell column as shown in FIG. 5, there may be a portion without wiring in the wiring area depending on the circuit of the library. Therefore, if library cells are provided in areas where there are no wiring lines, it becomes possible to mount even more logic circuits on the master chip. This arrangement method of library cells is a technique called channel free arrangement. On the other hand, the power supply wiring 20 for applying the voltages Vdd and VSS to the basic gate in the conventional library cell is as follows.
As shown in FIG. 7, the basic cells 15A and 15B are provided along the lateral ends of the cell rows,
Therefore, if the basic cells are arranged in a straight line to form a cell column, the power supply wirings 20 are designed to be naturally connected.

[Problem to be solved by the invention]

However, if the library cells are not arranged in a straight line and are arranged partially offset as shown in FIG. There is a problem in that the connection requires separate wiring as shown by reference numeral 21 in FIG. 8, which is complicated. The present invention has been made to solve the above-mentioned conventional problems, and is a master slice type semiconductor device in which a logic library can be provided on a master chip using a channel-free wiring type without requiring separate power supply wiring. The challenge is to provide the following.

[Means to achieve the task]

The present invention is formed of a first conductivity type transistor group and a second conductivity type transistor group whose gate electrodes are separated from each other, and each transistor group is centered on a line that crosses a source region, a gate electrode, and a drain region. In a master slice type semiconductor device that has a basic cell having a left-right symmetrical shape and can configure a library cell that performs a predetermined function using this basic cell, for each library cell,
The above-mentioned problem is achieved by providing a power line extending from a power line for supplying power to approximately the center of the library cell at an end of the library cell in a direction along the power line.

[Operation and effects of the invention]

When configuring a master slice type semiconductor device by channel-free arrangement of library cells, as in the past,
If the power supply wiring is placed only at the horizontal ends of the library cells, when the library cells are shifted by one basic cell and placed, there will be parts that cannot be wired as is, and it will be necessary to route the power supply separately. Ta. On the other hand, as a result of various considerations made by the inventors, for example, as shown in FIG. , the power supply wiring 20 of the library cell
It has been found that it can be provided at the end in the direction along the . Also, when multiple library cells are provided on a chip,
When the power line is installed at any end in the power wiring direction,
Since there are some places where wiring cannot be done, it is necessary to uniformly provide the power supply line for each library cell. The present invention has been made based on the above findings. According to the present invention, it is possible to provide a logic library on a master chip using a channel-free wiring method without requiring separate power supply wiring. The advantageous effect is that a large number of library cells and thus logic gates can be easily provided, and that the size of the system that can be realized is minimized from being determined by the size of the master chip.

【Example】

Embodiments of the present invention will be described in detail below with reference to the drawings. In this embodiment, the first and second basic cells 15A and 15B shown in FIGS. 6A and 6B are arranged on the master chip 10 as shown in FIG. As shown in FIG. 1, the basic cell 15A,
A power supply wiring 20 similar to that shown in FIG. 7 above for supplying power to the library cell 32 composed of 15B.
In addition, for each library cell 32, power supplies Vdd, V
A power line 22 (indicated by 22A and 22B in FIG. 1) extending from the power line 20 for supplying ss to approximately the center of the live cell 32 is provided at the lower end along the power line 20. Furthermore, this power supply is! 22 is the power supply wiring 20
On the opposite side of the power supply wiring 20, connecting portions 23A and 23B are provided for connecting to the power supply wiring 20 of other library cells 32 when arranged in a channel free arrangement. In FIG. 1, the symbol S is the center line of the library cell 32, and the power line 22 extends from the power supply wiring 20 to the vicinity of this center line S. Therefore, in the embodiment, when arranging the library cell 32 in a channel free manner, the basic cells 15A, 15
If the library cell is shifted by one of B, as shown in FIG.
2 will be connected. Therefore, when placing library cells in a channel-free manner, there is no need to separately conduct power supply wiring. In addition, the other power supply wiring 20 to which the power supply line 22 is not connected
Regarding this, power is always applied to the power supply wiring 20 by arranging the library cells to which the power supply wiring 20 and the power supply line 22 are wired in all the basic cells other than the one in which the library cell 32 is arranged as described above. be able to. In addition, in the above embodiment, the power supply! 122 is provided at the lower end of the library cell 32 as shown in FIG. 1, but the power supply line according to the present invention is not limited to being provided as shown in the figure. is provided at the lower end of the library cell 32 and extends to the opposite side from the center line S as shown in FIG. 1, and the Vss power supply line 22 is provided at the upper end of the library cell 32 and extends to the opposite side from the center line S. You can do it like this.

[Brief explanation of drawings]

FIG. 1 is a plan view of a main part showing in detail a library cell of a semiconductor device according to the embodiment ζ of the present invention, and FIG. 2 is a plan view showing the state of the library cell connected to a power supply in the embodiment. 3 is a plan view showing a cell array in a conventional semiconductor device, FIGS. 4A and 4B are a plan view and a circuit diagram showing details of basic cells in the semiconductor device, and FIG. FIG. 6 is a plan view showing the configuration of the basic cell of the second conventional example; FIG. 7 is a plan view showing a conventional example of the power supply wiring in the library cell. Main Part Plan View FIG. 8 is a plan view showing an example of power supply wiring when library cells are arranged using the channel free wiring method. 32...Library cell, S...Center line.

Claims (1)

[Claims] (1) It is formed from a first conductivity type transistor group and a second conductivity type transistor group whose gate electrodes are separated from each other, and each transistor group is symmetrical about a line that crosses the source region, gate electrode, and drain region. In a master slice type semiconductor device, which has a basic cell in the shape of , and in which a library cell is constructed that performs a predetermined function using this basic cell, each library cell is connected from the power supply wiring that supplies power to the library. A semiconductor device characterized in that a power supply line extending approximately to the center of the cell is provided at an end of the library cell in a direction along the power supply wiring.