JPH02260650A - chip carrier - Google Patents
chip carrierInfo
- Publication number
- JPH02260650A JPH02260650A JP1082081A JP8208189A JPH02260650A JP H02260650 A JPH02260650 A JP H02260650A JP 1082081 A JP1082081 A JP 1082081A JP 8208189 A JP8208189 A JP 8208189A JP H02260650 A JPH02260650 A JP H02260650A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- chip carrier
- potting
- semiconductor element
- potting resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、樹脂あるいはセラミック外囲器を使用し液状
樹脂により搭載した半導体素子をポツテングするチップ
キャリアに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a chip carrier that uses a resin or ceramic envelope to pot semiconductor elements mounted with liquid resin.
(従来の技術)
tClあるいはトランジスタなどの半導体素子を取付用
電極を有する樹脂あるいはセラミック外囲器に搭載し、
ダイボンデング接合してから金線などでワイヤーボンデ
ング接合し、接着性の良好な耐候性液状エポキシ樹脂を
ポツテングするチップキャリアがある。(Prior art) A semiconductor element such as tCl or a transistor is mounted on a resin or ceramic envelope having mounting electrodes,
There is a chip carrier that is bonded by die bonding, then wire bonded with gold wire, etc., and then potted with a weather-resistant liquid epoxy resin with good adhesion.
(発明が解決しようとする課題)
従来のこの種のチップキャリアは回路パターンを有する
樹脂基板へ半田付は接合する際、ポツテング樹脂と樹脂
あるいはセラミック外囲器との接合部分に微視的剥離現
象を発生し、内部にWr截した半導体素子が微視的剥離
部分を介して侵入したクラック成分あるいは放置に伴う
大気中の水分の侵入により破損する不具合を有していた
。即ち、エポキシ樹脂ポツテング樹脂はチップキャリア
本体への接着性が良好で機械的性質が優れている反面、
熱膨張係数が大きい。このためシリコンなど半導体素子
への熱的衝撃に伴う破損防止を目的としてエポキシ樹脂
へ酸化硅素の微粉末をフィラーとして多量に添加してポ
ツテング樹脂の熱膨張係数の少値化を促す。しかしなが
ら、ポツテング樹゛脂を半導体素子を搭載したチップキ
ャリアへ滴下した際、ポツテング樹脂の滴下先端部分は
フィラー剤の含有値が少なく、樹脂成分の多い組織、樹
脂富裕層を形成する。この結果、熱膨張係数の抑制効果
が減少し、熱膨張係数の小値域との相違により基板から
微視的剥離を生じ易い。この構造となったチップキャリ
アをPC板などチップキャリアを他の回路基板ヘフラッ
クスを使用した半田付けを行う場合、昇温時ロジン系の
フラックスではアビエチン酸など活性化された成分の蒸
気あるいは液体がこの剥離部分へ侵入し、内部半導体素
子を破損する不具合を有していた。第3図は従来の実施
例の説明図で、ポツテング樹脂先端部分の拡大図である
。図において1はチップキャリア、5はポツテング樹脂
、5°は樹脂成分、5”は酸化硅素の微粉末のフィラー
である。添加したフィラー5”は樹脂の表面張力粉末粒
径、形試の選定などで大部分の領域と均一に混合される
が端部においては流動性の良い樹脂のみが毛細管現象に
よりチップキャリア面へと拡散し樹脂成分の多い樹脂富
裕層8を形成する。(Problems to be Solved by the Invention) When this type of conventional chip carrier is soldered to a resin substrate having a circuit pattern, microscopic peeling occurs at the joint between the potting resin and the resin or ceramic envelope. The Wr-cut semiconductor element was damaged by crack components that entered through the microscopically peeled portions or by moisture from the atmosphere that occurred when left unused. That is, while epoxy resin potting resin has good adhesion to the chip carrier body and excellent mechanical properties,
Large coefficient of thermal expansion. For this reason, in order to prevent damage to semiconductor elements such as silicon due to thermal shock, a large amount of silicon oxide fine powder is added to the epoxy resin as a filler to reduce the coefficient of thermal expansion of the potting resin. However, when the potting resin is dropped onto a chip carrier on which a semiconductor element is mounted, the tip of the dropping of the potting resin has a low filler content and forms a structure containing a large amount of resin component, a resin-rich layer. As a result, the effect of suppressing the coefficient of thermal expansion is reduced, and microscopic peeling from the substrate is likely to occur due to the difference in the coefficient of thermal expansion from the small value range. When soldering a chip carrier with this structure to another circuit board, such as a PC board, using a flux, when the temperature rises, the vapor or liquid of activated components such as abietic acid is released using a rosin-based flux. There was a problem in that it invaded this peeled part and damaged the internal semiconductor element. FIG. 3 is an explanatory view of a conventional embodiment, and is an enlarged view of the tip of the potting resin. In the figure, 1 is the chip carrier, 5 is the potting resin, 5° is the resin component, and 5" is the silicon oxide fine powder filler. The added filler 5" is the surface tension of the resin, the particle size of the powder, the selection of the shape sample, etc. Although the resin is uniformly mixed in most of the region, only the resin with good fluidity at the end portions diffuses to the chip carrier surface by capillary action, forming a resin-rich layer 8 containing a large amount of resin component.
(課題を解決するための手段)
本発明は、これらの欠点を解決するため、チップキャリ
ア内にポツテング樹脂の先端部分が薄く伸長することを
抑制するための層を構成することを特徴とし、その目的
は、ポツテング樹脂の先端部分の濡れ角度を一定値以上
に太くすることにより、充填したフィラーの含有成分の
少ない領域の発生を防止し、熱衝撃が基板へチップキャ
リアを取付け、半田付けする時のフラックス成分に曝さ
れても半導体素子に破損のないチップキャリアを提供す
るにある。(Means for Solving the Problems) In order to solve these drawbacks, the present invention is characterized by configuring a layer in the chip carrier for suppressing the thin extension of the tip portion of the potting resin. The purpose is to increase the wetting angle at the tip of the potting resin to a certain value or more to prevent the occurrence of areas with low filler content, and to prevent thermal shock from occurring when attaching and soldering the chip carrier to the board. To provide a chip carrier that does not damage semiconductor elements even when exposed to flux components.
(実施例)
第1図は本発明の詳細な説明図で、半導体素子を搭載し
、樹脂をポツテングしたチップキャリアの斜視図である
。図において1はチップキャリア、2は外部回路基板と
の取付用半田接合部分、3は半導体素子、4は半導体素
子をチップキャリアに配線接合するためのボンデング線
、5はポツテング樹脂、6はポツテング樹脂の先端部分
に、例えば、シリコン樹脂あるいはフルオロカーボン系
樹脂から成る堤防試の凸部である。第2図は本発明の詳
細な説明図で、第1図のポツテング樹脂5のチップキャ
リア接合部の先端部分の拡大図である。7はポツテング
樹脂5の濡れ角度である。(Example) FIG. 1 is a detailed explanatory diagram of the present invention, and is a perspective view of a chip carrier on which a semiconductor element is mounted and resin is potted. In the figure, 1 is a chip carrier, 2 is a solder joint for attachment to an external circuit board, 3 is a semiconductor element, 4 is a bonding wire for wiring and bonding the semiconductor element to the chip carrier, 5 is a potting resin, and 6 is a potting resin. At the tip thereof, there is a convex portion of a dike made of, for example, silicone resin or fluorocarbon resin. FIG. 2 is a detailed explanatory diagram of the present invention, and is an enlarged view of the tip portion of the chip carrier joint portion of the potting resin 5 of FIG. 1. 7 is the wetting angle of the potting resin 5.
前述のようにポツテング樹脂5を半導体素子3へ圧力式
デイスペンサなどで被覆する。この際ポツテング樹脂5
の作業性を改善するため、例えば、樹脂5°およびチッ
プキャリア1を数十度(一般に40℃から55℃)に加
温して行う。予めポツテング樹脂5はジャーローラなど
で樹脂5°とフィラー5”を充分に攪拌混合し、真空中
で減圧脱泡を行う。その後、ポツテング樹脂5にデイス
ペンサで半導体素子3と金線などのボンデング線4を完
全に被覆する。チップキャリア1には予めフルオロカー
ボン系樹脂のようにエポキシ樹脂に対して濡れ性が低く
、狭い範囲内でポツテング樹脂5の流出を抑制する樹脂
を印刷あるいは転写法などにより凸部6を構成しておく
。このように構成することによりポツテング樹脂5のチ
ップキャリア接合の先端部分のフィラー含有量の少ない
樹脂領域がなくなる。As described above, the semiconductor element 3 is coated with the potting resin 5 using a pressure dispenser or the like. At this time, potteng resin 5
In order to improve workability, for example, the resin and the chip carrier 1 are heated to several tens of degrees (generally from 40 to 55 degrees Celsius). In advance, the potting resin 5 is sufficiently stirred and mixed with the resin 5° and the filler 5'' using a jar roller or the like, and degassed under reduced pressure.Then, the potting resin 5 is coated with a semiconductor element 3 and a bonding wire such as a gold wire using a dispenser. Completely cover the chip carrier 1 with a resin such as fluorocarbon resin that has low wettability with epoxy resin and suppresses the outflow of the potting resin 5 within a narrow range by printing or transferring. 6. By configuring in this manner, a resin region with a low filler content at the tip portion of the potting resin 5 for bonding the chip carrier is eliminated.
この結果、ポツテング樹脂被iff全体が均一にフィラ
ー5”が分散し部分的に熱膨張係数の変・動の少ない値
を得ることが出来、熱衝撃に対しても微視的亀裂のない
チップキャリアを得ることが出来る。更に付は加えて説
明すると、この凸部の効果はチップキャリアのように搭
載密度の高い回路において得られる。熱膨張係数の抑制
に効果的な酸化硅素の微粉末フィラー充填含有率が比重
比で25%を越すポツテング樹脂の場合、チップキャリ
アへのポツテング樹脂の濡れ角度が45度以上の場合は
先端部分の樹脂とフィラーが分離せず目的のポツテング
樹脂構成を得ることが出来る。As a result, the filler 5" is uniformly distributed throughout the potted resin coating, making it possible to obtain a value with little variation in the coefficient of thermal expansion in some parts, and a chip carrier that does not have microscopic cracks even when subjected to thermal shock. As an additional explanation, the effect of this convex portion can be obtained in circuits with high mounting density, such as chip carriers.Fine powder filler of silicon oxide is effective in suppressing the coefficient of thermal expansion. In the case of a potten resin whose content exceeds 25% in terms of specific gravity, if the wetting angle of the potten resin to the chip carrier is 45 degrees or more, the resin at the tip and the filler will not separate and it will not be possible to obtain the desired potten resin composition. I can do it.
凸部の作成は、前述のようにフルオロカーボン系樹脂を
チップキャリアへ印刷するが小規模の場合、筆による塗
布も可能である。また、チップキャリアの材質は熱膨張
係数の小さい酸化アルミニウムなどのセラミック基板に
おいて特に著しい効果を示すが、本発明による方法によ
れば樹脂系材質においても同様の効果を得ることが出来
る。The protrusions are created by printing the fluorocarbon resin on the chip carrier as described above, but in the case of small-scale applications, application with a brush is also possible. In addition, although a particularly remarkable effect is exhibited when the material of the chip carrier is made of a ceramic substrate such as aluminum oxide, which has a small coefficient of thermal expansion, the method according to the present invention can also obtain the same effect when using a resin-based material.
(発明の効果)
以上説明したように、フィラーを含有するエポキシ樹脂
をポツテング樹脂として使用するチップキャリアにおい
て、ポツテング樹脂の先端領域に樹脂への謂れ性の低い
凸部によりポツテング樹脂の濡れ角度を45度以上に構
成し、フィラーと樹脂の分離した樹脂富裕層の発生を抑
止したからチップキャリアを外部基板へ取付ける際の半
田付けにおいても微視的亀裂の発生のないチップキャリ
アを提供出来る利点がある。(Effects of the Invention) As explained above, in a chip carrier that uses an epoxy resin containing a filler as a potting resin, the wetting angle of the potting resin can be increased to 45° by the convex portion that is less likely to disturb the resin in the tip region of the potting resin. This has the advantage of being able to provide a chip carrier that does not cause microscopic cracks even during soldering when attaching the chip carrier to an external board because it prevents the formation of a resin rich layer where the filler and resin are separated. .
第1図は本発明の実施例によるチップキャリアの斜視図
、第2図は第1図のポツテング樹脂の先端部分の拡大図
、第3図は従来のポツテング樹脂部分の拡大図である。
1・・・チップキャリア、2・・・半田接合部分、3・
・・半導体素子、4・・・ボンデング線、5・・・ポツ
テング樹脂、5°・・・樹脂、5・フィラー 6・・
・凸部、
角度、
8 ・ ・
・樹脂富裕層。FIG. 1 is a perspective view of a chip carrier according to an embodiment of the present invention, FIG. 2 is an enlarged view of the tip portion of the potting resin shown in FIG. 1, and FIG. 3 is an enlarged view of the conventional potting resin portion. 1...Chip carrier, 2...Solder joint part, 3.
...Semiconductor element, 4. Bonding wire, 5. Potting resin, 5°... Resin, 5. Filler 6.. Convex part, angle, 8. ... Resin wealthy class.
Claims (2)
を載置してボンデング線により接続し、前記半導体素子
とボンデング線をエポキシ樹脂によりポッテングしたチ
ップキャリアにおいて、前記ポッテングするエポキシ樹
脂の周囲に堤防状の凸部を設けたことを特徴とするチッ
プキャリア。(1) In a chip carrier in which a semiconductor element is placed on a chip carrier having mounting electrodes and connected by bonding wires, and the semiconductor element and the bonding wires are potted with epoxy resin, an embankment is formed around the potted epoxy resin. A chip carrier characterized by having a convex portion.
への濡れ角度を45度以上とレたことを特徴とするチッ
プキャリア。(2) A chip carrier characterized in that the epoxy resin according to claim 1 has a wetting angle on a substrate of 45 degrees or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1082081A JPH02260650A (en) | 1989-03-31 | 1989-03-31 | chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1082081A JPH02260650A (en) | 1989-03-31 | 1989-03-31 | chip carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02260650A true JPH02260650A (en) | 1990-10-23 |
Family
ID=13764505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1082081A Pending JPH02260650A (en) | 1989-03-31 | 1989-03-31 | chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02260650A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6762509B2 (en) * | 2001-12-11 | 2004-07-13 | Celerity Research Pte. Ltd. | Flip-chip packaging method that treats an interconnect substrate to control stress created at edges of fill material |
-
1989
- 1989-03-31 JP JP1082081A patent/JPH02260650A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6762509B2 (en) * | 2001-12-11 | 2004-07-13 | Celerity Research Pte. Ltd. | Flip-chip packaging method that treats an interconnect substrate to control stress created at edges of fill material |
| US6940182B2 (en) | 2001-12-11 | 2005-09-06 | Celerity Research Pte. Ltd. | Flip-chip package with underfill dam for stress control |
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