JPH02276309A - Cmos output circuit employing low threshold device - Google Patents

Abstract

PURPOSE: To apply a high voltage to an output node of a CMOS device by coupling an n-channel transistor(TR) between a p-channel TR and an output terminal and making the n-channel TR nonconductive when a terminal level of the output terminal reaches a prescribed level. CONSTITUTION: The circuit 20 comprises a p-channel TR 21 and N-channel TRs 22, 23 which are connected in series between a VCC and a VSS. The TR 22 is a low threshold voltage (low VT) device and its source connects to a drain of the TR 23, and a output terminal 24 is connected to the connecting point. When a high voltage is applied to the output terminal 24, the low threshold voltage device 22 is conductive so long as a voltage applied to the output terminal 24 is smaller than VCC-VT but the low threshold voltage device 22 stops its conduction as soon as the terminal voltage exceeds the voltage VCC-VT so as to reduce the voltage applied to the drain of the TR 21 thereby substantially preventing a high voltage from being applied to the drain of the TR 21.

Description

BACKGROUND OF THE INVENTION (1) Technical Field of the Invention The present invention relates to complementary metal oxide semiconductor (0MO8) devices, and more particularly to CMO8 output drivers.

(2) Prior Art The use of complementary metal oxide semiconductors (0MO8) is well known in the prior art. Advantages derived from using CMO8 technology are also well known in the art, including lower power consumption.

- In boat fishing, a pair of transistors are coupled in series between the supply voltage and ground, and the output is taken at the junction of these two transistors. The pair of transistors consists of an n-type device and a p-type device. In the simplest operation of a pair of transistors, one or the other of said transistors is such that the output available at the junction of both transistors is coupled through said one transistor or said other transistor to a supply voltage or to its ground. so that it is conducting at any given time.

Although CMO8 devices can operate over a wider range of supply voltages than devices using other types of technology, such as transistor-transistor logic (TTL), they can output voltages higher than VCC. Susceptible to diode breakdown or latch-up when applied to a terminal.

During special modes of operation, it may be necessary for high voltages to be applied to the output node. For example, during the manufacture of these 0MO8 devices, high potentials may be applied to place the device into a special purpose or mode, such as a test mode. or in other instances,
For example, electrically programmable read-only storage (p
High voltages may be encountered when programming storage devices such as puoM. In some cases, the application of a high voltage is desirable at the output node, but as there is a possibility of equipment failure, this high voltage is not applied or is severely limited to prevent such failure of the equipment. . In other cases, special node voltages are applied to the inputs (gates of transistors) because a third or pin is not available to overcome this drawback.

The intention of the present invention is to enable the application of such high voltages to the output node of the 0MO8 device.

[Summary of the invention]

The present invention provides a CMO with a low threshold device coupled in series between a p-channel transistor and an output terminal.
This invention discloses a low threshold device with 8 outputs, 4 outputs, and 4 outputs. This low threshold device has a threshold voltage (Vt) of approximately zero volts. Under normal CMOS driver operation, this low threshold device drops to essentially zero volts and the voltage present at the output terminals drops to p
When the channel transistor is conducting, it is essentially equivalent to prior art devices that do not have low threshold devices.

During special mode operation, when a high voltage is applied to the output terminal, the low threshold device will conduct only as long as the voltage applied to the output terminal is less than vcc-VT.

However, from the table it can be seen that as soon as the terminal voltage increases beyond VCC-VT, the low threshold device stops conducting and sets p
Decouples high voltages from the drain of the channel transistor. This depacking essentially prevents high voltages from being applied to the drain of the p-channel transistor.

VD is p at the drain of a p-channel transistor
/n diode turn-on voltage, if the high voltage were to reach a value greater than VCC+VD, the p+/n- junction of the drain to substrate of the p-channel transistor would be forward biased and this This leads to excessive current flowing between the drain of the p-channel, channel φ transistor and the substrate, causing turn-on of the PNP parasitic bipolar transistor and creating a latch-up condition.

〔Example〕

A CMOS driver circuit using low threshold devices is described. In the following description, various specific details are set forth, such as specific threshold levels, etc., in order to provide a thorough understanding of the invention. however,
It will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

In other instances, well-known structures and processes have been described in detail in order not to unnecessarily obscure the present invention.

(1) Prior Art Referring to FIG. 1, a prior art 0MO8 driver circuit 10 is shown. This circuit 10 includes a p-type transistor 11 and an n-type transistor 1 to form an 0MO8 pair.
It consists of 2. Transistor I'' Lister 11 has its source coupled to the power supply voltage VCC and its tray coupled to the tray 7 of transistor 12. The source of transistor 12 is connected to VliS, in this case ground. The gates of each transistor 11 and 12 are coupled to receive an input signal.The output terminal is coupled to the junction of the two drains.

In operation, when the input signal is low, transistor 12 is essentially cut off while transistor 11 is conductive. Conduction of transistor 11 couples output terminal 13 to VCC and places terminal 13 substantially at the VCC potential. On the contrary, when the input is high level (hig
h 1evel ), transistor 11 is in cutoff and transistor 12 is conductive, placing the output terminal at a potential that is Vllg. Circuit 10 operates as a basic CMOS inverter for input signals.

Typically in this configuration, transistors 11 and 12 are driven by input signals to their respective gates. The amplitude of the input voltage may vary over a wide voltage range, typically between VCC and Vlg. The voltage at terminal 13 is derived from the conduction of one of transistors 11 and 12. However, in some cases, such as during special test modes or programming of the storage device, a voltage is applied to terminal 13. The actual value of the applied voltage to and must be limited so that breakdown of the device diode or forward biasing of the diode does not occur. The voltage applied to the terminal 13 is Wee + v,
If the value of , is exceeded, it is possible to destroy the device 11. vD is the p''/n-diode turn-on voltage, typically in the range of 0.6 to 0.7 volts. Applying a high voltage to the drain of transistor 11 Since transistor 11 is a p-type device with its substrate coupled to VCC, if the drain voltage is higher than VC(:+VD) then the p+ The drain is forward biased. This forward bias generates a current between the drain of transistor 11 and its substrate. If this current is too large, subsequent failure of transistor 11 can occur. Alternatively, this current can act as a trigger to induce SCR latch-up in adjacent circuits.

Therefore, the application of high voltage at the output terminal 13 must be limited so that this forward biasing of the drain of the transistor 11 with respect to the substrate does not occur.

(2) The inventive circuit is used to enable the application of high voltages at the inventive output. Referring to FIG. 2, circuit 20a consists of three transistors 21, 22 and 23 coupled in series between VCC and V3s. Transistor 21 is a p-channel device with its source coupled to power supply voltage VCC. The drain of transistor 21 is coupled to the drain of transistor 22, and this junction is designated node A. Transistor 220 source is coupled to the drain of transistor 23, and output terminal 24 is also coupled to this junction. The source of transistor 23 is coupled to VSS, in this case ground. The gates of transistors 21 and 23 are coupled together to warm the input, and the gate of transistor 22 is connected to V
Coupled to a voltage such as CC or switched voltages. Transistors 22 and 23 are n-channel devices, where transistor 22 is a low threshold voltage (low VT) transistor.

Transistors 21 and 23 are comprised of eight CMO pairs and are functionally equivalent to the operation of prior art CMOS inverter 10 of FIG. That is, under normal operation, when the input signal is noy, it causes transistor 23 to conduct and transistor 21 to turn off, thereby applying a low potential to terminal 24. When the input signal is low, transistor 21 is conductive and transistor n is cut off. VCC is transistor 22
is applied to the drain of The transistor 22 is also conductive,
A potential approximately close to potential VCC is applied to terminal 24. The actual voltage varies from vCC to transistor 22 at terminal 24 (V
22) by subtracting the threshold value ■T.

Transistor 22 is an n-channel zero threshold device having a threshold voltage of approximately zero volts. A typical transistor has a threshold voltage on the order of 0.6 to 1.0 volts that an applied gate-to-source voltage must overcome in order to conduct. Low threshold devices typically have turn-on values of θ±0.1 volts, although negative voltages are also possible due to process variations in transistor manufacturing.

Therefore, under normal operation, when transistor 21 is conducting, transistor 22 is also conducting, but with its drain and terminal 22 conducting, such that the voltage present at terminal 24 is approximately equal to the prior art CMO8 circuit of FIG. drops to essentially zero volts across the source. Low threshold devices have essentially no effect under normal operation. Also, when transistor 23 is conducting, transistor 21 is not cut off and transistor 22 is essentially out of circuit.

In special operating modes in which high voltage is to be applied to pad 24: 1. Transistor 22 is switched from high voltage to transistor 2.
1. When the applied voltage to terminal 24 is less than VCC -Vt22, transistor 22 conducts and drops the value of 722 across transistor 220 to drain/gate. The input to the gate of transistor 21 can be such that it activates transistor 21 and does not cause any disturbance. However, when the voltage applied to terminal 24 reaches a value of VCC -Vt22, this voltage application places transistor 22 in a cut-off state. With transistor 22 in the non-conducting state, it operates to isolate transistor 21 from terminal 24.

When the voltage applied to the terminal 24 increases further,
It is decoupled from the drain of transistor 21 by the non-conduction of transistor 22.

High-speed break of n+/p- junction of transistor 22
Down prevents current flow through the substrate of the low threshold device, thereby protecting transistor 22. Since transistor 23 is also an n-type device, high voltages at the drain will not cause its breakdown. Therefore, by placing a low threshold device between p-channel transistor 21 and terminal 24, at least V
If a high voltage with a CC-vTO value is applied to the output terminal 24, it will result in a decoupling of the p-channel red transistor 21 from this output terminal 24.

The manufacture of low threshold devices is well known in the art and is described in U.S. Pat. No. 4,052,229;
, 096,584, and U.S. Patent No. 4,103,1
It is disclosed in No. 89. These US patents are incorporated herein by reference.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional 0MO8 driver circuit. FIG. 2 is a circuit diagram of an 0MO8 driver circuit of the present invention using low threshold transistors. 11-.φΦp-type transistor, 12...n-type transistor, 13...output terminal, 21.p-type transistor, 22,23.n-type transistor, -output terminal.

Claims (2)

[Claims] (1) a p-channel transistor having a source coupled to a first potential; a first p-channel transistor having a substantially zero threshold level and coupled between the p-channel transistor and an output terminal;
a second n-channel transistor coupled between the output terminal and a second electrical potential, the output terminal being activated when the terminal potential of the output terminal reaches a predetermined value. A complementary metal oxide semiconductor (CMOS) circuit tolerant of high voltage inputs, wherein the first n-channel transistor is brought into a non-conducting state to decouple the p-channel transistor from a terminal. (2) a p-channel signal with a source coupled to a supply voltage and a gate coupled to accept an input signal;
a first n-channel transistor having a low threshold level and having a drain coupled to the drain of the p-channel transistor, a gate coupled to a power supply voltage, and a source coupled to an output terminal; a second n-channel transistor having a drain coupled to the output terminal and a source of the first n-channel transistor, a source coupled to the power supply voltage return, and a gate coupled to receive an input; a transistor, such that when the output terminal reaches a terminal potential of V_C_C-V_T, the application of the terminal potential inhibits conduction between the drain of the p-channel transistor and the substrate. Complementary metal oxide semiconductor (CMOS) characterized in that a first n-channel transistor decouples the p-channel transistor
driver circuit.