JPH02278343A - Diagnostic system - Google Patents

Abstract

PURPOSE:To discriminate whether phantom data has been generated in the internal part or the external part of a data pass with less software by transferring a parity check result in a data input terminal to an output terminal with data and comparing it with the parity check result in the output terminal. CONSTITUTION:Since all data 70-7n inputted to the data pass 1 are outputted with the parity check result by input terminal parity checkers 20-2n, a pair of data 70-7n and the parity result are further checked in an output terminal parity checker 3. If the parity check result 9 is a logic '1' when the parity check result 8 is a logic '1', it is shown that there is no fault in the internal part of the data pass by an external fault signal 10. When the parity check result 9 is a logic '0', it is shown that there is the fault in the internal part of the data pass by an internal part fault signal 11. Thus, correspondence that from which input terminal data detecting a parity error has been inputted is attained in the output terminal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to data path diagnosis, and in particular, when a parity error is detected at the data output end, it is possible to determine whether or not the parity error has occurred within the data path. It relates to a diagnostic method for determining.

[Conventional technology]

Conventionally, this type of diagnostic method holds the parity check result at the data input end, and when a parity error is detected at the output end, the parity check result at the input end is referenced to detect the parity error. The method used was to determine whether or not an incident occurred internally.

[Problem to be solved by the invention]

However, in the conventional method described above, the parity check result must be held at the data input terminal at the timing when valid data is input, which makes control complex and requires multiple data input terminals. In some cases, there is a drawback that it is difficult to correlate data for which a parity error has been detected at the output end to which input end the data was input from.

[Means to solve the problem]

The configuration of the diagnostic method of the present invention has a parity checker at each data input end and output end, and the parity check result at the input end is used in the data path to determine whether or not data garbled has occurred internally. The device includes means for transferring the data together with the output terminal, and means for referring to the parity check result at the input terminal that has been transferred when a parity error is detected at the output terminal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a data path 1, input end parity checkers 20 to 2n, output end parity checker 3, AND gates 4 and 5,
It is composed of an inverter 6.

The data 70 to 7n input to the data path 1 are all output together with the parity check results by the input end parity checkers 20 to 2n, so the set of data 70 to 7n
and the parity result is further checked at the output end, and when the parity check result 8 is logic "1", if the parity check result 9 at the input end is also logic "1", the external fault signal is 10 indicates that there is no fault inside the data path, and if the parity check result 9 at the input end is logic "o", the internal fault signal 1
1 indicates a failure within the data path.

〔Effect of the invention〕

As explained above, the present invention transfers the parity check result at the data input end to the output end together with the data and compares it with the parity check result at the output end, thereby preventing data corruption inside the data path with less hardware. This has the effect of being able to determine whether the problem occurred inside or outside.

In particular, when creating a data path using a TTL gate, etc.
Since each TL often includes gates for 4 or 8 bits, 1 bit of parity is required for every 8 bits of data.
In data paths that add , there is a tendency for a few bits worth of paths to be left over, and by implementing the method of the present invention using these leftover paths, further hardware reduction can be expected. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 1... Data path, 20-2n, 3... Verity checker, 4.5... AND gate, 6... Inverter, 70-7n... Input data group, 8... Output end Parity check result at input terminal, 9... Parity check result at input terminal, 10... External failure signal, 11...
Internal fault signal.

Claims (1)

[Claims] Each data input end and output end has a parity checker, and in the data path that determines whether or not data garbled has occurred internally, the parity check result at the input end is transferred together with the data to the output end. and means for referring to the transferred parity check result at the input end when a parity error is detected at the output end.