JPH02278879A - Manufacture of thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a thin film transistor (TPT) used as a switching element of an active matrix liquid crystal display element, for example. (Prior Art) Regarding display devices using liquid crystals, active matrix type liquid crystal display elements with large capacity and high density are being actively developed and put into practical use for use in television displays, graphic displays, and the like. In such display devices, semiconductor switches are used as means for driving and controlling each pixel so that high contrast display without crosstalk can be performed. As the semiconductor switch, a TPT formed on a transparent insulating substrate is usually used because it is capable of transmissive display and can easily be made to have a large area. Furthermore, among TPT, those using amorphous silicon (a-3i) are in-shell because low-temperature processing is possible. Generally, as an active matrix type liquid crystal display element, two substrates, each of which has been subjected to an alignment treatment by rubbing, are placed parallel to each other so that the alignment directions are at 90 degrees to each other, and a nematic film is placed between them. Twisted nematic (T
Type N) is widely used. In the future, the fields of application of such liquid crystal display elements will rapidly expand, and the need for them will increase not only for tabletop and wall-mounted televisions, but also for use in harsh environmental conditions such as in automobiles and aircraft cockpits. is expected. (Problem W1 to be Solved by the Invention) However, this type of a-8LTPT exhibits a deterioration phenomenon in which the on-current decreases with operating time. As TPT deterioration progresses, pixels cannot be driven normally, and display image quality deteriorates. In particular, this deterioration phenomenon is known to be accelerated by atmospheric temperature, which has been a major problem in cases where reliability is required in high-temperature environments, such as in automobiles and aircraft. This invention was made in view of such conventional circumstances, and it provides a TP that has little deterioration and excellent reliability in high-temperature environments.
The purpose of this invention is to provide a method for manufacturing T. [Structure of the Invention] (Means for Solving Notification 3) The present invention relates to a method for manufacturing a TPT consisting of a gate electrode, a gate insulating film, a semiconductor film made of a-3T, a source electrode, and a drain electrode. It is. In the invention according to claim 1, in order to obtain a gate insulating film adjacent to the semiconductor film, a silicon oxide film is formed by plasma CVD at a substrate temperature in the range of 430°C to 800°C from the side far from the semiconductor film. The method includes a step of sequentially forming a silicon nitride film. Note that here, the substrate temperature is 8
The upper limit of 00° C. was set in consideration of deformation of the insulating substrate itself. Further, in the invention according to claim 2, in order to obtain a gate insulating film adjacent to the semiconductor film, the semiconductor film is exposed to a reduced pressure from a side far from the semiconductor film.
The method includes steps of sequentially forming a silicon oxide film using a VD method and a silicon nitride film using a plasma CVD method. (Function) Until now, it has been thought that the stability of a-SiTFT is controlled by the insulating material that is in direct contact with a-3t and the state of its interface. However, in this invention, a-
The amount of charge trapped in the insulating film can be reduced by selecting a film with low defect density for the material on the gate electrode side that does not directly contact St, for example, the part of the double-layer gate insulating film that contacts the gate electrode. , TPT with stable characteristics can be obtained. (Example) Hereinafter, the details of the present invention will be explained with reference to the drawings, taking as an example a case where the present invention is applied to an active matrix type liquid crystal display element. FIG. 1 is a sectional view showing one pixel portion of an active matrix liquid crystal display element using an embodiment of the invention as claimed in claim 1. In the figure, a gate electrode 2 made of molybdenum tantalum (Mo-Ta) is placed on the entire surface of an insulating substrate 1 made of glass (7059 manufactured by Corning), for example.
Next, a silicon oxide film 3a having a thickness of 0.3 μm is formed as a gate insulating film 3 by a plasma CVD method at a substrate temperature of 450° C. and a silicon oxide film 3a with a film thickness of 35 μm is formed so as to cover the gate electrode 2.
A silicon nitride film 3b having a thickness of 0.05 μm is sequentially formed by plasma CVD at 0°C. Here, the silicon oxide film 3a will be explained in detail by taking an example of its manufacturing method. The reaction chamber for film formation has a diameter of 30 cm.
It is equipped with a circular high-frequency electrode of S tH4, N20. A N2 gas supply system and an exhaust system consisting of a turbo molecular pump and a rotary pump are connected. The insulating substrate 1, which is a sample, is clamped to a heated ground electrode, and the substrate surface temperature is controlled to be 450°C. Here S L H20sec, N
Introduced 20200 secm and N2N240se,
These gases are exhausted through a turbomolecular pump and a rotary pump. At this time, the pressure inside the reaction chamber is controlled to 0.2 Torr by adjusting the opening degree of the exhaust valve. In this state, 13.5EI MHz is applied to the high frequency electrode,
When a high frequency of 300W is applied, a glow discharge occurs,
A silicon oxide film 3a is deposited. The deposition rate at this time is 4
．． It is 2 angstroms/S. FIG. 2 is a diagram showing the measurement results of the ESR (electron spin resonance) spectrum of the silicon oxide film 3a formed in this manner. In Figure 2,
The defect density of the film can be estimated from the intensity ratio of the center signal to the left and right reference signals.Also, as a comparative conventional example, the manufacturing conditions for silicon oxide 113a were changed to the substrate temperature of 350°C instead of the substrate temperature of 450°C. The measurement results of the ESR (electron spin resonance) spectrum of the silicon film are also shown. The silicon oxide film of this comparative conventional example has an extremely high signal intensity at the center and a film defect density of 1018. , -3, whereas it can be seen that the silicon oxide film 3a of this example is a good quality film with very low signal intensity and defect density of 1018all-3 or less. Next, a method for manufacturing silicon nitride film 3b will be described in detail. The reaction chamber in which the film is formed is equipped with a circular high-frequency electrode of diameter 30 (Ml+) and a ground electrode opposing it.
4, NH3, and N2 gas supply systems and an exhaust system consisting of a turbo molecular pump and a rotary pump are connected. The insulating substrate 1, which is a sample, is clamped to a heated ground electrode and subjected to f411 so that the substrate surface temperature becomes 350°C. Here is S i H420seci. NH 80 sec and N 2300 sec are introduced, and these gases are exhausted through a turbomolecular pump and a rotary pump. At this time, the pressure inside the reaction chamber is controlled to 0.6 Torr by adjusting the opening degree of the exhaust valve. In this state, 13.56 MHz is applied to the high frequency electrode.
, When a high frequency of 300 W is applied, a glow discharge occurs and the silicon nitride film 3b is deposited. The deposition rate at this time was 1.3 angstroms/S. Next, a film with a thickness of 0.05μ is applied on the gate insulator l1llI3.
A semiconductor film 4 made of a-3i of m and an inorganic protective film 5 of 0.2 μm in thickness are sequentially formed. Next, after processing the inorganic protective film 5 into a predetermined shape, a low resistance semiconductor film 6 with a film thickness of 0.05 μm, for example, is formed, and the semiconductor film 4 and the low resistance semiconductor film 6 are further processed to form a channel. Obtain the regions, source and drain regions. Further, on the gate insulating film 3, an I T
A pixel electrode 7 made of Indium TinOxide is formed. Next, a source electrode 8 is formed on the source region so as to be connected to the pixel electrode 7, and a drain electrode 9 is formed on the drain region. In this way, a predetermined active element substrate 11 having a TPTIO consisting of the gate electrode 2, the gate insulator 1413, the semiconductor film 4 made of a-Si, the source electrode 8, and the drain electrode 9 is obtained. On the other hand, a common electrode 13 made of ITO is formed on the entire surface of an insulating substrate 12 made of glass, thereby forming a counter substrate 14. An alignment film 15 made of, for example, low-temperature cure type polyimide (PI) is formed on the entire surface of the active element substrate 11.
Further, on the entire surface of the counter substrate 14, an alignment film 16 made of, for example, low temperature cure type PI is formed. Then, on the surfaces of the active element substrate 1 and the counter substrate 14, an alignment treatment by rubbing is performed by rubbing each of the alignment films 15 and 16 in a predetermined direction with a cloth or the like. . Furthermore, an active element substrate 11 and a counter substrate 1
4 are arranged so that their surfaces face each other and their orientation axes make approximately 90°, and the liquid crystal 1 is placed in the gap between them.
7 is being held. Here, when the active element substrate 11 and the counter substrate 14 are combined, the rubbing direction of the alignment films 15 and 16 is set so that the direction of good viewing angle faces the front direction. Polarizing plates 18 and 19 are attached to the other main surfaces of the active element substrate 11 and the counter substrate 14, respectively, and illumination is provided from the other main surface of either the active element substrate 11 or the counter substrate 14. It is designed to do this. FIG. 3 is a schematic diagram showing the arrangement of this embodiment. In the figure, one TPTIO exists for each pixel,
It is composed of a gate electrode 2 integrated with the row selection line 20, a drain electrode 9 integrated with the column selection line 21, a source electrode 8 connected to the pixel electrode 7, a channel region surrounded by a dotted line, and the like. Here, the row selection line 20 is an address line for applying a scanning signal to the gate of TPTIO, for example, whereas the column selection line 21 is a data line for applying an image signal to the drain of TFT 1°0, for example. . Overall, one pixel is composed of a plurality of TPTIOs and one pixel electrode 7 connected thereto, and row selection lines 20 and column selection lines 21 are arranged in a matrix around this pixel. It is formed. In this embodiment, in order to obtain the gate insulating film 3 adjacent to the semiconductor 114, the substrate temperature is increased from the far side to the semiconductor film 4.
Since the step of sequentially forming the silicon oxide film 3 as the silicon nitride film 3b by the plasma CVD method in the range of 30° C. to 800° C. is provided, it is possible to suppress the deterioration phenomenon that accompanies the operation time of TPTIO. FIG. 4 shows the TPTIO in this example [(a)] and the comparative example [(b)
)] is a diagram showing changes in transfer characteristics after performing an accelerated deterioration test, and the vertical axis is the lower rain current (A
), the horizontal axis represents the gate voltage (V). Here, compared to TPTIG, in the comparative example, the manufacturing conditions for the silicon oxide film 3a were changed to a substrate temperature of 450°C, and the substrate temperature was 350°C.
They have almost the same configuration except that the temperature is set to ℃. Further, in the accelerated deterioration test, a method was adopted in which the source and drain were short-circuited and grounded, and a voltage of +15V was applied to the gate for 10,000 seconds at an ambient temperature of 70° C., and then changes in characteristics were examined. As can be seen from the figure, in (a) there is a threshold voltage drift) mΔVth-2,5V, and in (b)
4) It can be seen that the threshold voltage drift amount is reduced compared to ΔVth-8, 2v, and a TPT with stable characteristics is obtained in this example. Next, an embodiment of the invention according to claim 2 will be described. This embodiment differs from the embodiment shown in FIG. 1 in the method of forming the gate insulating film 3. That is, in this embodiment, the gate insulating film 3 is made of low pressure carbon so as to cover the gate electrode 2.
A silicon oxide film 3a with a film thickness of 0.3 μm is formed using the VD method, and a film thickness of 0.05 μm is formed using the plasma CVD method at a substrate temperature of 350°C.
m silicon nitride films 3b are sequentially formed. Here, the silicon oxide film 3a will be explained in detail by taking an example of its manufacturing method. The reaction chamber for film formation has a diameter of 30 CI.
Equipped with a circular substrate holder of 1, S tH4,02
, N2 gas supply system and an exhaust system consisting of a mechanical booster pump and a rotary pump are connected. The insulating substrate 1, which is a sample, is clamped to a heated substrate holder, and the substrate surface temperature is controlled to be 400°C. Here S i H30sec and 02100 s
ECG+ is introduced and these gases are exhausted through a mechanical booster pump and a rotary pump. At this time, if the pressure inside the reaction chamber is controlled to OJT orr by adjusting the opening degree of the exhaust valve, the silicon oxide film 3a
is deposited. The deposition rate at this time is 0.5 angstrom/s. FIG. 5 is a diagram showing the measurement results of the ESR (electron spin resonance) spectrum of the silicon oxide film 3a formed in this manner. In FIG. 5, as in the case of FIG. 2, as a comparative conventional example, the ESR (electron spin resonance) spectrum of the silicon oxide film 3a is shown in which the manufacturing conditions of the silicon oxide film 3a are changed to the substrate temperature of 350° C. instead of the substrate temperature of 450° C. The measurement results are also shown. In this comparative conventional silicon oxide film, the signal intensity at the center is extremely large and the defect density of the film is t.
In contrast, in the silicon oxide film 3a of this example, almost no signal due to defects was detected (1
016 cm-3 or less), it can be seen that the film has an extremely low defect density. The method of manufacturing silicon nitride film 3b is the same as that in the embodiment shown in FIG. In this embodiment, the gate insulator II adjacent to the semiconductor film 4
In order to obtain III3, a reduced pressure C is applied to the semiconductor film 4 from the far side.
Since it includes a step of sequentially forming a silicon oxide film 3a using a VD method and a silicon nitride film 3b using a plasma CVD method,
It is possible to suppress the deterioration phenomenon that accompanies the operation time of TPTIO. FIG. 6 shows the TPTIO [(a)
] and the above-mentioned comparative example [(b)] are diagrams showing changes in transfer characteristics after performing an accelerated deterioration test. In the accelerated deterioration test in Figure 6, the source and drain are short-circuited and grounded, and the ambient temperature is 7.
A method was adopted in which changes in characteristics were investigated after applying a voltage of +15 V to the gate for 10,000 seconds at 0°C. The drift amount △Vth-0.8V, ΔVth-3 in (b)
, 2V, the threshold voltage drift H1 is reduced, and it is clear that a TPT with stable characteristics is obtained in this example as in the previous case. Next, another embodiment of the invention set forth in claim 2 will be described. FIG. 7 is a sectional view showing one pixel portion of an active matrix liquid crystal display element using another embodiment of the invention as claimed in claim 2. This embodiment differs from the embodiment shown in FIG. 1 in the method of forming the gate insulating film 3. That is, in this embodiment, as shown in FIG. 7, a silicon oxide film 3 as a gate insulating film 3 having a film thickness of 0.2 μm is formed by low pressure CVD method and plasma CVD at a substrate temperature of 850° C. to cover the gate electrode 2. A silicon oxide film 3c with a thickness of 0.15 μm and a silicon nitride film 3b with a thickness of 0.05 μm are sequentially formed using a plasma CVD method at a substrate temperature of 350° C. Here, the silicon oxide film 3c will be explained in detail by taking a method of manufacturing the same as an example. The reaction chamber for film formation has a diameter of 30 cI.
It is equipped with a circular high-frequency electrode of I+ and a ground electrode opposite to it, and has 5tH4, N20. A N2 gas supply system and an exhaust system consisting of a turbo molecular pump and a rotary pump are connected. The insulating substrate 1, which is a sample, is clamped to a heated ground electrode, and the substrate surface temperature is controlled to be 350°C. Here S i H420sec,
N20200 secm and N240 sec gas are introduced and these gases are exhausted through a turbomolecular pump and a rotary pump. At this time, the pressure inside the reaction chamber is controlled to 0.2 Torr by adjusting the opening degree of the exhaust valve. In this state, 13.58 Mllz is applied to the high frequency electrode,
When a high frequency of 300 W is applied, a glow discharge occurs and a silicon oxide film 3c is deposited. The deposition rate at this time is
It is 4.2 angstroms/S. The method of manufacturing the silicon oxide film 3a and the silicon nitride 113b is the same as in the first embodiment of the invention. In this embodiment, the gate insulating film 3 adjacent to the semiconductor H4 is
In order to obtain this, a silicon oxide film 3as by a low pressure CVD method and a silicon nitride film 3b are sequentially formed by a plasma CVD method on the semiconductor film 4 from the far side. Deterioration phenomena that occur over time can be suppressed. Actually, when an accelerated deterioration test similar to that shown in Fig. 6 was conducted, the drift amount ΔVth-0,
5 V, and it was found that the reproducibility of the reduction in the amount of threshold voltage drift was superior to that of the first embodiment of the invention as claimed in claim 2. This is the silicon oxide film 3a
and silicon nitride film 3b as a buffer layer.
By forming the silicon oxide 11113c by the D method, it is possible to reproducibly form a sufficiently good interface when forming the silicon nitride film 3b by the plasma CVD method on the silicon oxide film 3a by the low pressure CVD method. It is thought that this is because of this. Here, the thickness of the silicon oxide film 3c is 300~
A range of 2000 angstroms is desirable. For example, if the film thickness is less than 300 angstroms, the reproducibility of stabilizing the characteristics is poor because a sufficient effect as a buffer layer cannot be obtained;
When the thickness is greater than 0 angstroms, the stability of TPTIO is dominated by silicon oxide JII3c and becomes unstable. Note that the structure of the TPTIO gate insulating film 3 is not limited to what has been described so far, and it goes without saying that various modifications may be made within the scope of the present invention as long as they satisfy the structural requirements of the present invention. Further, the present invention is applicable not only to active matrix liquid crystal display elements but also to a-St contact sensors and the like. rEffects of the invention] This invention provides the structure of the gate insulating film of the a-3i TFT,
Starting from the side farthest from the semiconductor film, the substrate temperature is 430°C to 800°C.
By forming a silicon oxide film by plasma CVD, a silicon oxide film by low pressure CVD, or a silicon nitride film by plasma CVD in the temperature range of 0.degree. As a result, it becomes possible to manufacture an active matrix type liquid crystal display element with excellent reliability, for example, in a high-temperature environment.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing one pixel portion of an active matrix liquid crystal display element using an embodiment of the invention as claimed in claim 1, and FIG. 2 is an E of a conventional example for comparison with the embodiment shown in FIG.
Figure 3 is a diagram showing the SR spectrum, Figure 3 is a schematic diagram showing the arrangement of the embodiment shown in Figure 1, and Figure 4 is an accelerated deterioration test conducted on the example shown in Figure 1 and the comparative conventional example. FIG. 5 is a diagram showing the ESR spectra of an embodiment of the invention as claimed in claim 2 and a comparative conventional example. FIG. 6 is a diagram showing the ESR spectra of the embodiment shown in FIG. FIG. 7 is a cross-sectional view showing one pixel portion of an active matrix liquid crystal display device using an embodiment of the invention as claimed in claim 2. FIG. 2...Gate electrode 3...Gate insulating film 3a...Silicon oxide film 3b...Silicon nitride film 4...Semiconductor film 8...Source electrode 9...Drain electrode representative Patent attorney rules Ken Ken Yudo Takehana Kikuo @ 1 @ 7 Kaku CG) Figure 2 Doshi 1 Denda Turtle (A) )'t1 Den Tan (A) Isho 4j6 Huge cliff (Ie is also a unit)

Claims (2)

[Claims] (1) In a method for manufacturing a thin film transistor comprising a gate electrode, a gate insulating film, a semiconductor film made of amorphous silicon, a source electrode, and a drain electrode, in order to obtain the gate insulating film adjacent to the semiconductor film, A method for manufacturing a thin film transistor, comprising the steps of sequentially forming a silicon oxide film by a plasma CVD method and a silicon nitride film by a plasma CVD method at a substrate temperature in the range of 430° C. to 800° C. from the side farthest from the semiconductor film. (2) In a method for manufacturing a thin film transistor comprising a gate electrode, a gate insulating film, a semiconductor film made of amorphous silicon, a source electrode, and a drain electrode, in order to obtain the gate insulating film adjacent to the semiconductor film, 1. A method for manufacturing a thin film transistor, comprising a step of sequentially forming a silicon oxide film by low pressure CVD and a silicon nitride film by plasma CVD from the far side of a semiconductor film.