JPH02271275A - Simulating method of logic circuit - Google Patents

Abstract

PURPOSE:To make it possible to perform verification so that dispersion in delays is less when there is a common path parts in signal propagating paths by eliminating the difference in delays at the common path part, and performing the verification. CONSTITUTION:The data of input change, when output change occurs in each logic element of a logic circuit, are preserved. When said logic element is operated, the propagating paths of the signal change to each input of the logic element that is the object of the operation are obtained. Both the minimum delay and the maximum delay which are imparted to each constituent element in the logic circuit are used, and the simulation of the logic operation is performed. At this time, when there is a common path part in the signal propagating paths, the difference in delays at the common path part is eliminated, and verification is performed. Thus the dispersion in delays longer than required value is eliminated, and the verification can be performed. The detection of errors in a normal circuit can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic simulation method for simulating the operation of a logic circuit.

[Conventional technology]

Conventionally, this type of logic circuit simulation method does not store information about input changes that cause output changes of logic elements, and when logic elements are operated, signals reaching each input of the logic element being operated are They were not looking for a propagation path for change.

[Problem to be solved by the invention]

The conventional logic circuit simulation method described above does not store information about the input change that caused the output change of the logic element, and when the logic element is operated, the signals reaching each input of the logic element that is the target of the operation are stored. They were not looking for a propagation path for change.

Therefore, when simulating the logic behavior of a circuit by using both the minimum delay and maximum delay given to the components in the circuit and taking delay variations into account, there will be a Even when there are parts, it is not possible to eliminate differences in delay between common parts, and verification takes into account the variation in delay more than necessary, which has the disadvantage of potentially causing errors. There is also.

FIG. 3 is a circuit diagram schematically showing a general logic circuit, and problems of the conventional technology will be explained using this diagram. In this logic circuit, a data input terminal (DA'l') 1 and a clock input terminal (CLK) 2 are external signal input terminals.Gl is a buffer amplifier, FB and F2 are D flip-flops, and D (data ) and C (clock) input terminals.

Further, OUT indicates the external output terminal 3.

Here, the wiring delay is assumed to be O, and the delay from the input to the output of the buffer G1 and from the C input to the flip-flop Fl and F2 is assumed to be a minimum delay of 5 ns and a maximum delay of Ions, and the set of these flip-flops 7F1 and F2. It is assumed that both the up time and the bold time are 3 ns.

Assume that the logical values of both the data input and the clock change from 0 to 1 due to a certain test button.

Here, waveform 1゛1 shows the change in data input value, and Qns
The waveform T2 shows the change in the clock input value, and the waveform T2 changes from O to IK at Qns. Waveform T
3 indicates a change in the C input of flip-flop F1 (ie, the output of buffer G1), and 0. 5
From ns to just before 10ns is changing from 0 to 1, 1Q
This indicates that the value becomes 1 after ns. Moreover, waveform T4 shows a change in the D input of flip-flop F2, and 1Qn
From 0.1Qns until just before s to just before 2Qns is O
It shows that during the change from 1 to 1, it becomes 1 after 20 nS. The waveform `l゛5 shows the change in the input of the flip 70 knob F2 (that is, the output of the buffer G1). It shows what will happen.

Here, it is assumed that the setup and hold times for the flip flop 1F2 are verified. First, assuming the maximum delay time, the change time of the D input is 1Qns.
Next, assuming the maximum delay time, it is determined that the change time of the C input is IQns and the hold time of 4.9.3 ns is not satisfied.

However, both the change that occurred at the D input and the change that occurred at the C input were caused by the change in the output of buffer G1, and the signal changes at the D and C inputs occurred simultaneously at the output of buffer G1. . Therefore, it is assumed that the path at buffer 01''& changes to the D input or changes with the minimum delay, and C
If the change leading to the input changes with the maximum delay, then variations in the M range will be unnecessarily taken into account.

Now, if we eliminate the 5 ns variation in delay assumed in the path to the output of buffer Gl and the path to both inputs, the change in D input when considering the minimum delay is the same as the change in input C when considering maximum delay. It is found that the change also occurs after SNS, and it is found that the halt time of 3 ns is satisfied.

As described above, in the conventional simulation method, since delay fluctuations are taken into account unnecessarily, there is a problem that errors may be detected even if the circuit is correct.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a method for simulating a logic circuit that can be verified by eliminating delay differences between common circuit parts and reducing delay fluctuations.

[Means to improve the problem]

The configuration of the logic circuit simulation method of the present invention is such that information on input changes that cause output changes of each logic element of the logic circuit is held, and when these logic elements are operated, each input of the logic element that is the object of the operation is When shimmy and ration of logic operations are performed using both the minimum delay and maximum delay given to each component in the logic circuit, the common This method is characterized in that when there is a common path portion, the verification is performed by eliminating the difference in delay between these common path portions.

〔Example〕 Next, the present invention will be explained with reference to figures.

FIG. 1 is a flowchart explaining one embodiment of the present invention;
FIG. 2 is a flowchart showing the contents of the timing verification process in FIG. 1.

First, in step 10, the circuit is initialized and the values of logic elements in the circuit are initialized. Next, in step 11, a test button is applied, and the test button of the given test button number is applied to the external input terminal of the circuit. next,
An event search process is performed in the stem game 12 to search for a change in value at the input of a logic element in the circuit or at an external input section.

Next, in step 13, timing verification is performed, and if the logic element whose input has changed is subject to timing faults such as setup/halt time or spikes, timing verification is performed.

Next, in step 7-14, event execution processing is performed to obtain the output value of the logic element whose input has changed.

Next, a route search process is performed using the stem game 15, and changes in the input given the output value are recorded, and if there are multiple changes in the input at this time, all are recorded.

Next, in step 16, the time is added and the time is advanced by one unit. Next, in step 17, it is determined whether or not the time has reached the period of the slam application, and if it is, the next step 18 is the addition of the bang number, and the test bang number is set to 1 batt lft. , if the cycle is not reached, the process returns to step 12, the event search.

Next, it is determined by the stethoscope 19 whether or not the batten number has exceeded the total number of bangs, and if the number has not been exceeded, the process returns to applying the test batts of the stethoscope 11, and if it has been exceeded, the test is ended.

In the flowchart of the timing verification process in FIG.
It is determined whether the process is subject to timing verification, and if there is a verification item, the timing verification process of step 22 is performed, and if there is no verification item, the process ends.

In the timing verification process in step 22, the signal propagation path that caused the input change of the logic element is considered, and the timing is verified for the worst combination of complex input changes by considering only the change time of the input of the logic element. Execute.

Next, in step 23, it is determined whether or not there is an error. If there is an error, the process proceeds to the route search process for the next stethoscope 24, and if there is no error, the process ends. In the route search process, for combinations of input changes for which errors were found during timing verification,
After that change, the nine signal propagation paths are searched, and then the stethoscope 25 determines whether there is a common part. If there is a common part, the timing of the next stethoscope 26 is re-verified, and if there is no common part. If so, proceed to the error handling of Stesogame “28.”

In the timing angle verification process, for the combination of input changes discovered in the timing verification process in step 22, the variation in the delay up to the later intersection in time among the intersections of the signal propagation paths that caused the change is calculated. Eliminate, recalculate, and re-verify timing.

The Stella 27 determines whether an error has been detected in this timing verification, and if there is an error, the Stella 7゛2
If there is no error, it is determined in step 29 whether there is a combination that causes an error other than the worst among the multiple input changes discovered in the timing verification process of Stesoge '22. and executes the timing verification process of step 22 on the combination,
If it does not exist, exit. In the error processing at step 28, information about the detected error is saved and the process ends.

Next, a case will be described in which rml is verified during setup and hold of the flip-flop in the circuit diagram of FIG. In this case, circuit 01 in FIG. P.I.

The conditions for waveforms 'I'1 to T5' above are the same as in the conventional example.

Under these conditions, it is assumed that the setup/hold time is verified for F2. First, in the conventional example, it is determined that the hold time is not satisfied between the D input and the C input. However, in this embodiment, the flip 70 knob F2
The signal propagation path that caused the change in C and the input of C can be determined as follows by storing information on the input change that caused each output change.

First, the D input of the 7 lip flop F2 is connected to the output of the 7 lip flop F1, and its change is reflected in the flip flop F2.
The C input of this flip-flop F1 is connected to the output of the buffer G1, and the change is caused by the change in the input of the buffer G1, and the C input of the flip-flop F1 is caused by the change in the input of the buffer G1. is connected to the clock and changes as the clock changes.

Next, the C input of the flip-flora 7F2 is connected to the buffer G1
The input of the buffer (jl) is connected to the clock and changes are caused by the changes in the input of the buffer G1.

Therefore, from these information, changes in the D input and C input of the flip 70 tube F2 are caused by the same output change of the buffer G1, and changes in the D input of the clip flop F2 and the C input of the flick 70 tube F2 cause the change in the D input and C input of the flip 70 tube F2.
Re-verification is performed by eliminating the variation in delay taken into account until the output changes.

According to this flow, there is a difference of 5 ns between the maximum value of the change time of the C input of the flip-flop F2 from 0 to 1 and the minimum value of the change time of the D input of the flip-flop F2 from O to 1. exists and satisfies the hold time of 3 ns. At this time, flip flora 1
Since there is no other path combination that causes a change in the D input and C input of F2, the verification with this test button is completed.

Table 1 The following Table 1 shows an example of the data structure of a memory that realizes the simulation of this embodiment, and is an example when verified in FIG. 3. This first table (1° table) shows the changes that occur at each time, and shows the changes that occur for each time, the pointer to the H table in Table 2, and the H output or external input terminal. From special to logic element name, logic value change, change time.

Stores event numbers that distinguish changes. An event number is assigned to each identical output change caused by the same input change. Logical value changes are indicated by arrows that indicate the values before and after the change, and the logical value U indicates that the value is changing from 0 to 1.

The E table in Table 2 shows which event number change caused the change indicated by each event number,
The second and subsequent lines correspond to the event numbers from the top line.

Table 2 H table E table These tables show the relationship between υ and each change, making it possible to obtain the propagation path of the signal change.

Based on the relationship between event numbers, by obtaining the propagation path, the memory capacity is significantly reduced compared to the method of storing all the propagation paths.
This results in a reduction in memory capacity when the same change causes a plurality of output changes, even compared to a method that directly stores information on input changes that cause output changes of each logic element.

Furthermore, it is also possible to know the temporal relationship based on the size of each event number, which has the effect of reducing processing time.

In this article, only the information on the output or external input terminal of each logic element is shown, but the information on the input change of each logic element is expressed as the same as the information on the output or external input terminal of the logic element connected to it. There is.

Generally, information on the relationship between a change in the output of a logic element and a change in its input, and information on the connection between that input and the output of the logic element in the preceding stage or an external input terminal, are represented in separate tables and used in combination. It turns out. Furthermore, by representing the information on changes to the event number represented by the E table as a pointer from the E table to the H chief, it becomes more efficient.

〔Effect of the invention〕

As described above, the present invention stores information about input changes that cause output changes of a logic element, and determines the propagation path of the signal change to each input of the logic element.

By using both the minimum delay and maximum delay given to the components in the circuit to eliminate delay differences in common parts of multiple signal propagation paths, verify by eliminating unnecessary delay variations. It has the effect of being able to.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a flowchart illustrating an embodiment of the present invention;
FIG. 2 is a flowchart showing details of the timing verification process in FIG. 1, and FIG. 3 is a block diagram schematically showing an example of a general logic circuit. 10-19.21-29...processing step, 1...
Data input terminal, 2... Clock input terminal, 3...
Output terminal, Fl, F”z...Flip-flop, Gl
...Buffer (amplifier),'1'1~T5...Waveform. Agent Susumu Uchihara, patent attorney, P'2m 12th

Claims (1)

[Claims] Information about the input changes that caused the output changes of each logic element of the logic circuit is stored, and when these logic elements are operated, the propagation path of the signal change that reaches each input of the logic element that is the object of the operation is determined, and the information is stored in the logic circuit. When simulating logical operations using both the minimum delay and maximum delay given to each component in the signal propagation path, if there is a common path part among the signal propagation paths, the delay of this common path part A logic circuit simulation method characterized by performing verification by eliminating differences between