JPH02281343A - Cpu operation monitor system - Google Patents

Abstract

PURPOSE:To prevent erroneous output of a signal by comparing address information on an address bus and data information on a data bus with a reference and outputting a restart signal at the time of coincidence between them. CONSTITUTION:An address and data as the reference value are set to an address/data setting means 1. Each time an address and data are outputted to an address bus 101 or a data bus 102 from a CPU 3, they are compared with the reference value by a comparing circuit 2. When this comparison results in coincidence, the CPU 3 is judged to be normally operated and a watchdog timer WDT 7 is reset. If the WDT 7 is not reset within a set time, the operation of the CPU 3 is judged to be abnormal, and an alarm signal is outputted to a signal line 104, and the CPU 3 is reset. Thus, the control is returned to the start of a program and erroneous output of the restart signal of the WDT 7 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to monitoring of program running status in a CPUIC, and particularly to its watchdog timer (hereinafter referred to as WDT) system.

(Prior Art) Conventionally, the WDT monitoring method for monitoring the running state of a program includes rounding means for outputting a timer restart signal to an address that is always executed within a certain period of time on the program;
The device is configured to include a WDT that outputs an alarm to the outside when a certain period of time has elapsed for transmitting a restart signal.

Therefore, when the program is running normally, WDT
is always restarted within a certain period of time, and no alarm signal is output. Furthermore, since restart is not performed in the event of an abnormality, an alarm signal is output from the WDT to the outside. In the WDT monitoring method, the running of the program is monitored using this.

(Problems to be Solved by the Invention) The conventional WDT monitoring method described above monitors the abnormality when the WDT restart signal is erroneously output even if the system is abnormal. The disadvantage is that it cannot be done.

The purpose of the present invention is to constantly monitor address information on the address bus and data information on the data bus of the PU, store reference monitoring address information and monitoring data information in advance, and store the reference monitoring address information and data information on the address bus. The address information on the data bus and the data information on the data bus are compared with the reference,
By outputting a restart signal when the comparison results match and outputting an alarm signal after a certain period of time, the above drawbacks are eliminated and the WDT restart signal is configured to avoid being output erroneously. The present invention provides a method for monitoring CPU operation.

(Means for Solving the Problems) A CPU operation monitoring method according to the present invention is configured to include monitoring means, storage means, comparison means, determination means, and timer means with restart.

The monitoring means is for monitoring first address information on the address bus of the CPU and first data information on the data bus.

The storage means is for storing predetermined second address information for monitoring and second data information for monitoring.

The comparison means is for comparing the first and second address information as well as the first and second data information.

The determination means is a round type that outputs a restart signal when the first and second address information and the first and second data information both match as a result of the comparison.

The restart timer means is for outputting an alarm when a certain period of time has elapsed since the sending of the restart signal O.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a CPU operation monitoring method according to the present invention.

In FIG. 1, 1 is an address/data setting means, 2 is a comparison circuit, 3 is a CPU, and 4 is a RAM.

5 is a ROM, 6 is a determination circuit, and 7 is a WDT.

Also, 101 is an address bus, 102 is a 7'-tapas, 1
03 and 104 are signal lines, respectively.

First, an address and data to be compared and matched are set in the address/data setting means 1 using a switch.

Each time an address and data are output from the CPU 3, the comparison circuit 2 compares these addresses and data with a set address and set data, respectively. If the actual address and data being executed match the set address and set data during comparison, the CPU 3 determines that it is operating normally and resets the WDT 7. Within the set time of the WDT 7. If the reset is not applied, it is determined that the operation of the CPU 3 is abnormal, and the Hairer 4 signal is output on the signal line 104, and at the same time, the CPU 3 is reset, and the program is returned to the beginning and executed.

In this embodiment, address bus 101. ! -Data bus 1
02 are independent, but it is clear that the present invention can be applied even if these paths are common.

(Effects of the Invention) As explained above, the present invention can monitor the running of the program in the CPU by monitoring the address information on the address bus and the data information on the data bus. This has the effect that the program does not need an instruction to send a signal. Also, since the setting address and execution address are compared with the setting data and execution data, and the comparison results are used to control whether to restart the WDT or generate an alarm signal, it is possible that the WDT may be erroneous. It does not become a restart signal (it has the effect of being able to reliably check the operation of the CPU).

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a CPU operation monitoring method according to the present invention. 1... Address/data setting means 2... Comparing means 3... Comparing means 4... RAM 5... ROM 6... Judgment circuit 7... WDT 101.102... Bus 103 .104...Signal line patent applicant NEC Corporation

Claims (1)

[Claims] monitoring means for monitoring first address information on the address of the CPU and first data information on the data bus;
a storage means for storing predetermined second address information for monitoring and second data information for monitoring; a comparison means for comparing data information; and outputting a restart signal when the first and second address information and the first and second data information match as a result of the comparison; 1. A method for monitoring CPU operation, comprising: determination means; and timer means with restart for outputting an alarm when a predetermined period of time has elapsed since the transmission of the restart signal.