JPH02295215A - Maximum cycle signal generation circuit - Google Patents

Abstract

PURPOSE:To improve the anti-interference performance and the secrecy without increasing the scale of a device by using additionally a preset signal generating part, a K-notation counter, and a switch circuit which switches the number of stages of a shift register. CONSTITUTION:The switch circuits 5 and 6 switch the number (n) of stages and the number (m) of intermediate stages for feedback of an n-stage shift register 1. A K-notation counter circuit 7 secures the synchronization with the pulse modulating cycle of a radar, etc. Then a preset signal generating part 3 is added to set the optional initial value. Thus the signal irregularity is increased from the first since the initial value can be optionally set at the part 3. Furthermore the numbers (n) and (m) of stages of the register 1 can be varied and at the same time the code length and cycle are forcibly changed by the circuit 7. Thus it is possible to improve the anti-interference performance and the secrecy without increasing the scale of a device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for generating a maximum cycle signal that can improve anti-jamming properties and secrecy in communications, radar, etc.

[Conventional technology]

Conventional. Various irregular signals. It is used to improve the jamming performance of communications, radar, etc.). A typical example is the maximum period sequence signal.

FIG. 5 is a diagram showing a conventional n-th maximum period sequence signal generation circuit. In the figure, (1) is an i-stage shift register. (2
) is an exclusive OR circuit. (3) is the reset signal generation section.
(4) is a clock pulse generator.

In this circuit. The n-th stage of the n-stage shift register (1) and .
What is the output of the mth stage in the middle? Exclusive OR is performed using exclusive OR circuit (2). The output. It is fed back to the input of the first stage of the n-stage shift register (1). If the clock pulse ft of period T generated by the clock pulse generator (4) is added to the n-stage shift register (11), it is possible to generate the n-th maximum period sequence signal which is a combination of .0 and 1. In this case, the .n-stage shift register It is necessary that the initial state of the registers in all stages in (1) is not a, and that the number of intermediate stages m for feedback corresponds to the coefficients of the primitive polynomial over the finite field G F (21.Shift register For example, the value of m corresponding to the number of stages n in "Coding Theory" (Miyagawa.
Iwadare. Co-authored by Imai. Shokodo, 1973) and ``Spread Spectrum Communication System'' (published on May 20, 1988, Science and Technology Publishing Co., Ltd.). Page 423 Tables 6 and 6 K are known.

[Problem to be solved by the invention]

The initial value settings for the conventional maximum period sequence signal generation circuit as described above are as follows. A reset signal generator (3) presets the flip-flop with a reset signal. Initial value (1,
o, o, ...0) were used. For this reason, when the number of stages n of the shift register increases, there is a problem in that the initial period of 0 continues and the signal becomes less irregular, as shown in FIG. 6(b). Also. When applied to radar etc. If the period of pulse modulation of the radar and the period of the maximum period train signal are asynchronous, spurious will occur, so it is necessary to synchronize them with each other. However, the period of the nth maximum period sequence signal is (
2'-1) T. Radar distance performance. Pulse width determined by Doppler detection performance, etc. There was a problem in that it was difficult to match the pulse repetition period and synchronization rate. Furthermore. To improve confidentiality. When changing the period of the maximum cycle signal or the sign of the signal (combination of O and 1) over time. In order to change the position of the stage number 1 of the shift register and the number m of intermediate stages for feedback, it is necessary to provide a plurality of maximum period sequence signal generation circuits, which causes a problem that the device becomes large.

This invention was made to solve the problems mentioned above. The object of the present invention is to obtain a circuit for generating a maximum period sequence signal which has a high degree of irregularity from the beginning and whose period and sign are variable.

[Failure to solve the problem]

The maximum period sequence signal generation circuit according to the present invention is as follows. A switch circuit for switching the number of stages n of the shift register and the number m of intermediate stages for feedback. It is equipped with a K-ary counter circuit for synchronizing with the pulse modulation period of radar etc. and a preset circuit for setting an arbitrary initial value.

[Effect]

The maximum periodic train signal generation circuit in this invention is. Since the initial value can be set arbitrarily using the preset circuit, the signal is highly irregular from the beginning. Furthermore. The values of the number of stages n and the number of intermediate stages m of the shift register can be changed by forcibly changing the code length and cycle using the KK-based counter. To generate a maximum period sequence signal that can improve anti-jamming performance and secrecy without increasing the size of the device.

〔Example〕

FIG. 1 is a diagram showing an embodiment of this invention. (!) is an n-stage shift register. (2) is an exclusive OR circuit. 《3
>> is the preset signal generation section. (4) is a clock pulse generator. (5) is a switch circuit for switching the number of stages of the shift register. (6) is a switch circuit for switching the tap position for feedback. (7) is a K-ary counter. ( 8) is a control section.

The control unit (8) is composed of a CPU (8) as shown in Figure '2.
1), Memo IJ (82), 1st dedicated computing unit (83)
, a second dedicated arithmetic unit (84) and ■/0 (input/output) controller (85), which are mutually connected by a path (86).
connected to one.

The operation flow of this control section (8) is as shown in the flowchart of FIG. Maximum period sequence signal format suitable for communications and radar specifications. In other words. Performs calculations to determine signal periods and code combinations, and schedules (how to change them over time) the periods and code combinations.

Follow the flowchart in Figure 3. The operation of the maximum period sequence signal generation circuit according to the present invention will be explained. first. I/O controller (85) for specifications of communication equipment and radar equipment
t is read and stored in the memory (82) (Step I). Using the specifications stored in this memory (82), the number of stages n/ of the shift register (11) and the tap position m are determined by the first dedicated arithmetic unit (83) (step ro).The values n' and m is I/O controller (85)
T-Through. The signal is sent to a switch circuit (5) for changing the number of stages of the shift register (1) and a switch circuit (6) for changing the tap position of the feedback reservoir. Operate each switch circuit to create a shift register (
The number of stages is 11. Tap position km. This memory (8
2) Specifications stored in . In other words, using the radar pulse repetition period (data period in communication) τ, ゛, (2”−
1) Number of stages n of shift register (1) that satisfies 'T≧τ
'All settings. The tap position m is determined from the coefficients of the n/th order primitive polynomial corresponding to n' using a dedicated arithmetic unit (83).

These values n' and m}f are passed through the I/O controller (85). The signal is sent to a switch circuit (5) for switching the number of stages of the shift register (1) and a switch circuit (6) for switching the tap position for feedback. Operate each switch circuit to increase the number of stages of shift register (1) to n'. Switch to tap position krn (step). next. The initial value of the shift register (1) is set by a second dedicated arithmetic unit (84) (for example, a binary random number generator). control/0 controller ce5> and sends the entire signal to the preset signal generator {3). The reset command presets the shift register (1) as an initial value (step 2). After completing the initial settings as described above. The K-ary counter (
7) Reset (step ho). Furthermore, the clock pulse generator (4) is activated (to step).

The maximum period sequence signal generation circuit that has started operating according to the above procedure generates a clock pulse every K clock pulses as shown in Fig. 4 (.). An overflow pulse occurs in the K-ary counter (7) shown in FIG. 4(b), and the K-ary counter (7) and the preset signal generator (3) are reset and preset as shown in FIG. 4 <c>. to return to the initial state. The period (2
"-1) Extract the period of KT from T as shown in FIG. 4(d).

. in this way. The n/th order maximum period sequence signal obtained by presetting the initial value obtained using binary random numbers etc. is. High degree of irregularity from the beginning. Moreover. Decide on the base number Ki of the counters so that they can be synchronized with each other according to the specifications of communications, radar, etc. Every time a preset signal is generated in the preset signal generator (3). In other words. Since the n'th maximum period sequence signal appears reproducibly with a period of KT (<(2''-1)T), the generation of spurious signals that occur due to a period shift can be suppressed. Also, in terms of time, m Alternatively, by changing n' and m at the same time, the code combination and code length of the generated signal can be changed.The other party has less time to analyze the signal, improving confidentiality and anti-jamming properties.

In addition. In the above explanation, we talked about the case where the number of taps for feedback is one. The same applies to multiple cases. Also. I have described the case where a dedicated computing device is used for control. The same can be applied to the case where calculations are performed using a plurality of CPUs.

〔Effect of the invention〕

As above. According to this invention. Conventional maximum periodic sequence {
A preset signal is generated in the circuit that generates the word L KA counter. By adding all the switch circuits that switch stages a'i of the shift register. This has the effect of providing a maximum period sequence signal generation circuit with good initial characteristics that is compatible with the specifications of communications, radar, etc., without increasing the size of the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the maximum period sequence signal generation circuit according to the present invention. FIG. 2 is a block diagram showing one embodiment of the control section of the signal generation circuit of the present invention. Figure 3 is a flowchart explaining the operation of this control section. FIG. 4 is a diagram showing an example of a signal waveform generated by the signal generation circuit of the present invention.
Figure 5 is a block diagram showing a conventional maximum period sequence signal generation circuit. FIG. 6 is a diagram showing an example of a signal waveform generated by this signal generating circuit. In the figure. (1) is. Stage shift register. (2) is an exclusive OR circuit. (3) is a preset signal generation section. (4) is a clock pulse generator, +51, (61 is a switch circuit, (7) is a K-ary counter, and (8) is a control unit. In addition, the same or equivalent parts in the figure are given the same symbols. It is shown.

Claims (1)

[Claims] n-stage shift register and n of the n-stage shift register
Input the output of the first stage and the output of the intermediate stage number m (<n),
an exclusive OR circuit that feeds back the output of the exclusive OR to the input end of the first stage of the n-stage shift register; and an exclusive OR circuit that generates a clock pulse with a period T and sends the clock pulse to the n-stage shift register. a switch circuit for switching the number of stages n of the shift register in order to make the code length and cycle variable; and a switch circuit for switching the tap position m for the feedback; , a K-adic counter for reproducibly generating a period of a maximum period train signal determined by the clock pulse of the period T and the number of stages of the shift register with a period of KT, and inputting the output of the K-adic counter; a preset signal generation unit for setting an initial value of the shift register; a means for determining the number of stages and tap position of the shift register using predetermined specification information; and the number of stages and tap position determined by this means. means for generating a switching control command to the switch circuit so as to
means for setting an initial value of the shift register, outputting the initial value to the preset signal generating section, and generating a preset command for setting the initial value to the shift register; after completion of the presetting, the K-ary counter 1. A maximum period train signal generation circuit comprising: a control section having means for generating a reset command and generating a start command to the clock pulse generation section.