JPH02297974A - Thin-film e2prom - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a thin film E'FROM.

[Prior Art] Recently, as an E2PROM, a memory transistor and a selection transistor that selects this memory transistor (a selection transistor connected to each memory transistor, or a gate, source, etc. of a memory transistor,
A thin 111E2PROM has been developed in which a line selection transistor (line selection transistor) connected to each wiring connected to a drain electrode is formed of a thin film transistor.

This kind of thin-film E2PROM is known to use a normal thin-film transistor as the selection transistor, but recently, in order to increase the on-state current of the selection transistor, the selection transistor is replaced with a gate insulated from the transistor's original gate insulation. It is being considered to form a thin film transistor that includes, in addition to the membrane, another gate electrode that applies voltage to the semiconductor layer.

Figure 4 shows a thin film E2 FROM in which the selection transistor is a thin film transistor with two gate electrodes, the original gate electrode of the transistor and another gate electrode. This shows what is connected.

This thin film E2 FROM has a selection transistor TI, which is a thin film transistor with two gate electrodes, and a memory transistor T, which is a thin film transistor with one gate electrode, on an insulating substrate 1 made of glass or the like.
2, the selection transistor TI includes a lower gate electrode Gla formed on the substrate 1, and a lower gate insulator ff2 made of silicon nitride formed on the gate electrode Gla over almost the entire surface of the substrate 1. and an n-type semiconductor layer 3 made of 1-a-81 (type amorphous silicon) formed on this lower gate insulating film 2 to face the lower gate electrode Gla, and this n-type semiconductor layer 3. A source electrode Sl and a drain electrode D1 are formed on the n-type semiconductor layer 4 made of n"-a-81 (amorphous silicon doped with n-type impurities).
an upper gate insulating film 5 made of silicon nitride (StN) formed thereon over almost the entire surface of the substrate 1; and an upper gate electrode Glb. The lower gate insulating film 2 and the upper gate insulating film 5 of the selection transistor T1 each have a composition ratio Si/N of silicon atoms S1 and nitrogen atoms N in order to prevent the transistor from having hysteresis. It is made of silicon nitride, which has almost the same stoichiometric ratio (S i /N-0, 75) and does not have a charge storage function.

This selection transistor TI has an original lower gate electrode Gla and another upper gate electrode Glb.
By applying a voltage to the n-type semiconductor layer 3 from the upper gate electrode Glb, the on-current (I
DON) is made thicker.

Further, the memory transistor T2 is formed on an interlayer insulating film 6 made of silicon nitride or the like, which is formed over almost the entire surface of the substrate 1 on the selection transistor TI. a gate electrode G2 formed thereon, a gate insulating film 7 made of silicon nitride formed over the entire surface of the substrate on this gate electrode G2, and a gate insulating film 7 formed on this gate insulating film 7 to face the gate electrode G2. an n-type semiconductor layer 8 made of 1-a-Sl, and an n''
It consists of a source electrode S2 and a drain electrode D2 formed through an n-type semiconductor layer 9 made of -a-Si.

The gate insulating film 7 is composed of silicon atoms S1 and nitrogen atoms N, in order to provide a memory effect to the transistor.
The composition ratio Sl/N is expressed as the stoichiometric ratio (Sl/N-0,
75) Thicker (Si/N-0,85~1.15)
It is made of silicon nitride which has a charge storage function. Since the gate insulating film 7 of the memory transistor T2 has a charge storage function, the memory transistor T2 has a large hysteresis in the VG (gate voltage)-1DC drain current) characteristic, and thus has a memory effect. This memory transistor T2
performs writing/erasing/continuation operation by controlling the voltage applied to the gate electrode G2.

Note that the drain electrode D2 of the memory transistor T2
are connected to the source electrode S1 of the selection transistor T1 by connection wiring (not shown), and each gate electrode Gla of the selection transistor Tl.

Glb, drain electrode D1 and memory transistor T
The gate electrode G2 and source electrode S2 of No. 2 are each connected to wiring not shown. Further, 10 is a protective insulating film made of silicon nitride or the like.

[Problem to be solved by the invention]

However, in the conventional thin film E2PROM, the substrate 1
First, the lower gate electrode Gla of the selection transistor T1 is shown above.
A lower gate insulating film 2, an n-type semiconductor layer 3, an n-type semiconductor layer 4, and source and drain electrodes St are formed thereon.
, Di, the upper gate insulating film 5, and the upper gate electrode Gl
After forming a selection transistor T1 by stacking the selection transistor T1, an interlayer insulating film 6 is formed on this selection transistor Tl, and a memory transistor T2 is formed on this interlayer insulating film 6.
gate electrode G2, n-type semiconductor layer 7, n-type semiconductor layer 8, source and drain electrodes S2. Since this thin film E2PROM is manufactured using a manufacturing process in which the memory transistor T2 is formed by laminating the memory transistor T2, this thin film E2PROM requires a large number of steps to manufacture, and the overall thickness of the thin film E2PROM is also quite thick. I had a problem.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to form a memory transistor made of a thin film transistor and a selection transistor made of a thin film transistor provided with two gate electrodes on a substrate. The object of the present invention is to provide a thin film E2 FROM, which can be manufactured efficiently with a small number of steps and whose overall thickness can be reduced.

[Means to solve the problem]

In order to achieve the above object, the thin film E2 FROM of the present invention includes, on a substrate, a lower gate electrode for a selection transistor, a lower gate insulating film for a selection transistor covering almost the entire surface of the substrate, and a semiconductor layer for a selection transistor. Source for selection transistor.

A drain electrode and an upper gate insulating film for a selection transistor covering almost the entire surface of the substrate are laminated, and on the upper gate insulating film, an upper gate electrode for the selection transistor facing the semiconductor layer for the selection transistor, and a memory transistor. a gate electrode for the memory transistor, and on the gate electrode for the memory transistor, a gate insulating film for the memory transistor having a charge storage function, a semiconductor layer for the memory transistor, a source for the memory transistor,
A drain electrode is laminated.

The thin film E2PROM of the present invention further includes, on a substrate, a lower gate electrode for a selection transistor, a lower gate insulating film for the selection transistor covering almost the entire surface of the substrate, a semiconductor layer for the selection transistor, a source for the selection transistor,
A drain electrode and an upper gate insulating film for a selection transistor covering almost the entire surface of the substrate are laminated, and on the upper gate insulating film, an upper gate electrode for the selection transistor facing the semiconductor layer for the selection transistor, and a memory transistor. a first gate electrode for the memory transistor, and a first gate insulating film for the memory transistor, a semiconductor layer for the memory transistor, and source and drain electrodes for the memory transistor on the first gate electrode. ,
A second gate insulating film for a memory transistor and a second gate electrode for a memory transistor are laminated,
and one of the first gate insulating film and the second gate insulating film for the memory transistor is an insulating film having a charge storage function, and the other gate insulating film is an insulating film having no charge storage function. At the same time, among the first gate electrode and the second gate electrode for the memory transistor,
A gate electrode facing the memory transistor semiconductor layer through a gate insulating film having a charge storage function is used as a writing and erasing electrode, and a gate electrode facing the memory transistor semiconductor layer through a gate insulating film not having a charge storage function is used as a writing and erasing electrode. The opposing gate electrodes are used as readout electrodes.

[Effect]

That is, in the thin film E2PROM of the present invention, the upper gate electrode of the selection transistor and the gate electrode of the memory transistor are formed on the upper gate insulating film of the selection transistor. By forming the upper gate electrode of the selection transistor and the gate electrode of the memory transistor on the upper gate insulating film of the selection transistor, the selection transistor's The upper gate electrode and the gate electrode of the memory transistor can be formed simultaneously in one step, and the step of forming the interlayer BH is also unnecessary. Therefore, although the thin film E2 FROM of the present invention has a memory transistor made of a thin film transistor and a selection transistor made of a thin film transistor provided with two gate electrodes formed on a substrate, it is different from the conventional thin film E'FROM.
It can be manufactured efficiently with fewer steps than M, and is thinner due to the elimination of the interlayer insulating film.
The thickness of the entire FROM can also be reduced.

Further, in the thin film E' FROM of the present invention, the gate electrode of the memory transistor formed on the upper gate insulating film of the selection transistor is the first gate electrode of this memory transistor, and the first gate electrode A first gate insulating film for a memory transistor, a semiconductor layer for a memory transistor, and a source for a memory transistor.

A drain electrode, a second gate insulating film for the memory transistor, and a second gate electrode for the memory transistor are laminated to form the memory transistor into a transistor having first and second gate electrodes, and Writing and Erasing is performed using the gate electrode of the first and second gate electrodes that faces the memory transistor semiconductor layer via a gate insulating film having a charge storage function, and reading is performed using the gate electrode that also has a charge storage function. This is done by using a gate electrode that faces the semiconductor layer for the memory transistor through a gate insulating film that does not have a high temperature.If the memory transistor is configured in this way, the memory transistor will remain intact even after repeated reading. Since the threshold voltage of 15 does not change, stable reading can be performed semi-permanently. Also in this thin film E2PROM, since the upper gate electrode of the selection transistor and the first gate electrode of the memory transistor are formed on the upper gate insulating film of the selection transistor, the upper gate electrode of the selection transistor and the first gate electrode of the memory transistor are formed. and the first gate electrode can be formed simultaneously in one step, and the interlayer insulating film provided on the selection transistor in the conventional thin film E2PROM can be made unnecessary. Therefore, although this thin film E2 FROM has a selection transistor equipped with two gate electrodes and a memory transistor also equipped with two gate electrodes, one for writing and erasing and one for reading, it is different from the conventional one. The thin film E2 can be manufactured more efficiently with fewer steps compared to the case where another readout gate electrode is provided in the FROM memory transistor, and the thin film E2
The overall thickness of the 2PROM can also be reduced.

〔Example〕

Hereinafter, the first embodiment of the present invention will be explained using a thin film E2 FRO in which a selection transistor is connected to each memory transistor.
M will be explained with reference to FIGS. 1 and 2.

As shown in FIG. 1, the thin film E2PROM of this embodiment has a selection transistor TIO, which is a thin film transistor with two gate electrodes, and a thin film transistor with one gate electrode, on an insulating substrate 11 made of glass or the like. A memory transistor 720 is formed.

The selection transistor TIO includes a selection transistor lower gate electrode GIOa formed on the substrate 11, and a selection transistor made of silicon nitride (SIN) formed on the lower gate electrode GIOa over almost the entire surface of the substrate 11. A lower gate insulating film 12 and the lower gate electrode G10a on this lower gate insulating film 12.
An i-type semiconductor layer 13 for selection transistors made of 1-a-3l formed opposite to , and an n-type semiconductor layer 14 made of 1-a-3i formed on top of this l-type semiconductor layer 13 (; Select transistor source and drain electrodes S
IO, DIO, the i-type semiconductor layer 13 and the source,
An upper gate insulating film 15 for a select transistor made of silicon nitride formed over almost the entire surface of the substrate 11 is laminated on the drain electrodes SIO and DIO, and the i-type semiconductor layer 13 is formed on the upper gate insulating film 15. Upper gate electrode G10 for selection transistor formed to face each other
It consists of b. The lower gate insulating film 12 and the upper gate insulating film 15 of this selection transistor TIO have a composition ratio of silicon atoms S1 and nitrogen atoms N, respectively.
It is made of silicon nitride, which has no charge storage function and has a ratio of /N almost equal to the stoichiometric ratio (Si/N-0,75).

The memory transistor T20 is made of a memory transistor gate electrode G20 formed on the upper gate insulating film 15 of the selection transistor TIO, and silicon nitride formed on the gate electrode G20 over almost the entire surface of the substrate 11. A gate insulating film 16 for a memory transistor, an i-type semiconductor layer 17 for a memory transistor made of 1-a-81 formed on this gate insulating film 16 facing the gate electrode G20, and this l-type semiconductor layer. a memory transistor source formed on 17 via an n-type semiconductor layer 18 made of n''-a-St;
Drain electrode 820. It consists of D20. The gate insulating film 16 of the memory transistor T20 has a composition ratio S1/N of silicon atoms S1 and nitrogen atoms N in a stoichiometric ratio (S l /N-) in order to provide a memory effect to the memory transistor T20. 0.75) and is made of silicon nitride which is thicker (31/N-0.85 to 1.15) and has a charge storage function.

Note that the drain electrode 1 of the memory transistor T20
) 20 is connected to the source electrode SIO of the selection transistor TIO by a connection wiring (not shown), and is connected to each gate electrode GIOa of the selection transistor TIO.

G10b, the drain electrode DIO, and the gate electrode G20 and source electrode 820 of the memory transistor T20 are respectively connected to wiring not shown. Further, 19 is a protective insulating film made of silicon nitride or the like.

That is, in this thin film E2PROM, the upper gate electrode G1Ob of the selection transistor T10 and the gate electrode G20 of the memory transistor T20 are formed on the upper gate insulating film 15 of the selection transistor TIO, and the selection transistor TIO is selected. The interlayer insulating film provided on the transistor is eliminated, and in this way, the upper gate electrode GLO of the selection transistor T20 is placed on the upper gate insulating film 15 of the selection transistor TIO.
b and the gate electrode G20 of the memory transistor T20, the upper gate electrode G1Ob of the selection transistor TIO and the memory transistor ? Twenty gate electrodes G20 can be formed simultaneously in one process.

FIG. 2 shows the manufacturing process of the thin film E" FROM. This thin $E2 FROM can be manufactured by the following steps.

First, a metal film such as chromium (Cr) is deposited on the substrate 11 by vacuum evaporation or sputtering, and this metal film is buttered, as shown in FIG. 2(a).
A lower gate electrode G 10a of the selection transistor TIO and a gate wiring connected to this lower gate electrode G 10a are formed.

Next, as shown in FIG. 2(b), silicon nitride with an S1/N value of about 81/N-0.75 is deposited on the entire surface of the substrate 11 by plasma CVD. forming a lower gate insulator 11112 for the selection transistor;
Subsequently, t-a-81 and n''-a-31 are successively deposited thereon by the plasma CVD method to form the n-type semiconductor layer 13 and the n-type semiconductor layer 14, and further. On top, the source of the selection transistor TIO.

Metal film a such as chromium that becomes the drain electrodes SIO and DIO
A film is formed by vacuum evaporation or sputtering.

Next, as shown in FIG. 2(c), the metal film a and the n-type semiconductor layer 14 are patterned by photolithography, and the source and drain electrodes 810°010 and While forming a drain wiring connected to the drain electrode DIO,
Unnecessary portions of the n-type semiconductor layer 14 are removed, and the i-type semiconductor layer 13 is further patterned into the element shape of the selection transistor TIO by photolithography.

Next, as shown in FIG. 2(d), silicon nitride with a St/N value of approximately the same as Sl/N-, 0.75 is deposited over the entire surface of the substrate 11 by plasma CVD. The upper gate insulating film 15 for the selection transistor is formed, and then a metal film such as chromium, which will become the upper gate electrode GIO of the selection transistor TIO and the gate electrode G20 of the memory transistor T20, is deposited thereon by vacuum evaporation or sputtering. Attach a film.

Next, as shown in Figure 42(e), the metal film is patterned by photolithography, and the upper gate electrode G1 for the selection transistor is made of this metal film.
0b, a memory transistor gate electrode G20, and a gate wiring connected to each gate electrode G10b, 020, respectively. At this point, the two gate electrodes G
Select transistor TI with lOa, G 10b
O is completed.

Next, as shown in FIG.
Plasma CV
A gate insulating film 16 for a memory transistor is formed by depositing by method D, and then 1-a-8i and n
"-a-8l" are successively deposited by a plasma CVD method to form an n-type semiconductor layer 17 and an n-type semiconductor layer 18, and further thereon, a memory transistor T is formed.
A film of metal IC such as chromium, which will become the source and drain electrodes S20.020, is deposited by vacuum evaporation or sputtering.

Next, as shown in FIG. 2(g), the metal film C and the n-type semiconductor layer 18 are patterned by photolithography to form source and drain electrodes S20°D20 for the memory transistor made of the metal film C. and forming a source wiring connected to the source electrode S20, removing an unnecessary portion of the n-type semiconductor layer 18, and further removing the unnecessary portion of the n-type semiconductor layer 18;
The semiconductor layer 17 is patterned into the element shape of the memory transistor T20 by photolithography to complete the memory transistor T20.

Thereafter, a protective insulating film 19 made of silicon nitride or the like is formed to cover the selection transistor TIO and the memory transistor T20, thereby completing the thin film E, 2PROM shown in FIG.

In this way, according to the thin 111E2 FROM, the upper gate electrode G10b of the selection transistor TIO and the gate electrode G20 of the memory transistor T20 can be simultaneously formed in one process during its manufacture.
Further, there is no need for the step of forming an interlayer insulating film provided on the selection transistor in the conventional thin film E2PROM.

Therefore, although the thin @E'FROM has a memory transistor T20 made of a thin film transistor and a selection transistor T10 made of a thin film transistor provided with two gate electrodes G LOa and G fob formed on the substrate 11, it is different from the conventional one. Compared to thin film E2 FR, it can be manufactured efficiently with fewer steps, and the thin film E2 FR can be manufactured by eliminating the interlayer insulating film.
The overall thickness of the OM can also be reduced.

Note that in the above embodiment, the memory transistor 720 is
Although it is assumed that the memory transistor T20 has one gate electrode G20, the memory transistor T20 may have two gate electrodes 020, one for writing and erasing and one for reading.

FIG. M3 shows a second embodiment of the present invention, and the thin film E2PROM of this embodiment has a selection transistor TIO and a memory transistor T20 each having two gate electrodes.

The thin film E2 FROM of this embodiment includes, on a substrate 11, a lower gate electrode G 10a for a selection transistor, a lower gate insulating film 12 for a selection transistor covering almost the entire surface of the substrate 11, and an i-type semiconductor layer 13 for a selection transistor.
and an n-type semiconductor layer 14 and source and drain electrodes sio for the selection transistor.

A DID and an upper gate insulating film 15 for a selection transistor covering almost the entire surface of the substrate 11 are laminated, and an upper gate for a selection transistor facing the i-type semiconductor layer 13 for a selection transistor is formed on the upper gate insulating film 15. An electrode G fob and a first gate electrode G 20a for the memory transistor are formed, and a first gate insulating film (having a load storage function for the memory transistor) is formed on the first gate electrode G 20a. S1/N-0,85
~1.15 silicon nitride film) 16, i-type semiconductor layer 17 for memory transistor, and n-type semiconductor layer 17 for memory transistor.
type semiconductor layer 18 and source and drain electrodes S20. D
20 and a second gate insulating film for the memory transistor (
A silicon nitride film 20 having no load storage function and a second gate electrode G 20b for a memory transistor are stacked.

Of the first gate electrode 020a and the second gate electrode G20b of the memory transistor T20,
A first gate electrode G 2 facing the i-type semiconductor layer 17 via a first gate insulating film 16 having a charge storage function.
0a is a second gate electrode G which is used as a writing and erasing electrode and which faces the i-type semiconductor layer 17 via a second gate insulating film 20 which does not have a charge storage function.
20b is a reading electrode.

That is, in the thin film E2PROM of this embodiment, by providing the memory transistor T20 with a first gate electrode G 20a and a second gate electrode G 20b,
Writing and erasing are performed using the first and second gate electrodes G2.
Reading is performed using the first gate electrode 020a of G20b, which faces the n-type semiconductor layer 17 via the first gate insulating film 16 having a charge storage function.
A second gate electrode G 2 facing the type 1 semiconductor layer 17 via a second gate insulating film 20 that does not have a charge storage function.
If the memory transistor T20 is configured in this way, the threshold voltage of the memory transistor T20 will not change even if reading is repeated, so reading can be performed semi-permanently and stably. (See Japanese Patent Application No. 1-15165).

And also in the thin @E2 FROM of this example,
The upper gate electrode GLGb of the selection transistor TIO and the first gate electrode G20 of the memory transistor T20 are disposed on the upper gate insulating film 15 of the selection transistor TIO.
Since the upper gate electrode G 10b of the selection transistor TIO and the first gate electrode G 20a of the memory transistor T20 can be simultaneously formed in one process, the selection transistor The interlayer insulating film provided thereon can be made unnecessary. Therefore, this thin film E2
FROM has a selection transistor TIO with two gate electrodes ctoa.

Although the memory transistor T20 is also equipped with two gate electrodes G20a and G20b for writing and erasing and for reading, it is different from the conventional thin film E2 FROM memory transistor. Compared to the case where one readout gate electrode is provided, it can be manufactured efficiently with fewer steps, and the thickness of the entire thin film E2 FROM can also be reduced.

In this second embodiment, the first gate electrode G 20a of the memory transistor T20 is used for writing and erasing, and the second gate electrode G 20b is used for reading. 1 gate electrode G 20
a may be used for reading, and the second gate electrode G 20b may be used for writing and erasing. In that case, the first gate insulating film 16 is an insulating film that does not have a charge storage function,
The second gate insulating film 20 may be an insulating film having a charge storage function.

Further, in the first and second embodiments described above, the gate insulating film having a charge storage function of the memory transistor T20 is
This gate insulating film is made of silicon nitride with an i/N of 0.85 to 1.15, and a high dielectric film (tantalum oxide, etc.) with a dielectric constant of 10 or more is formed on the gate electrode side. i
On the type semiconductor layer side, the value of Si/H is the stoichiometric ratio (l/
A thin film of silicon nitride (N = C1, 75) comparable to
It may be a two-layer film having a film thickness of 50 to 2,000 layers, and this two-layer structure gate insulating film also has a sufficient charge storage function as a memory element.

Further, in the above embodiment, a thin film E2PROM in which a selection transistor T20 is connected to a memory transistor TIO has been described, but the present invention provides a line for selecting each wiring to each wiring connected to the gate, source, and drain electrodes of a memory transistor. Of course, the present invention can also be applied to a thin film E''FROM connected with a selection transistor.

〔Effect of the invention〕

In the thin @E2PROM of the present invention, the upper gate electrode of the selection transistor and the gate electrode of the memory transistor are formed on the upper gate insulating film of the selection transistor.
Conventional thin 111E2PROM+: Since the interlayer insulating film provided on the selection transistor in the conventional thin 111E2PROM+ is not required, the upper gate electrode of the selection transistor and the gate electrode of the memory transistor are simultaneously formed in one process. This also eliminates the need for the step of forming the interlayer insulating film. Therefore, the thin 111IE' PR of the present invention
Although OM has a memory transistor made of a thin film transistor and a selection transistor made of a thin film transistor with two gate electrodes formed on a substrate, it can be manufactured efficiently with fewer steps than conventional thin film E2PROM. In addition, the thickness of the entire thin film E2PROM can be reduced by the amount of the interlayer insulating film.

Further, in the thin film E2PROM of the present invention, the gate electrode of the memory transistor formed on the upper gate insulating film of the selection transistor is the first gate electrode of this memory transistor, and A first gate insulating film for a memory transistor, a semiconductor layer for a memory transistor, and a source for a memory transistor.

A drain electrode, a second gate insulating film for the memory transistor, and a second gate electrode for the memory transistor are laminated to form the memory transistor into a transistor having first and second gate electrodes, and Writing and Erasing is performed using the gate electrode of the first and second gate electrodes that faces the memory transistor semiconductor layer via a gate insulating film having a charge storage function, and reading is performed using the gate electrode that also has a charge storage function. Since this is carried out using a gate electrode that faces the semiconductor layer for the memory transistor through a gate insulating film that does not have a high temperature, the threshold voltage of the memory transistor does not change even if reading is repeated, and therefore it is semi-permanent. Therefore, stable reading can be performed. Also in this thin film E2PROM, since the upper gate iai of the selection transistor and the first gate electrode of the memory transistor are formed on the upper gate insulating film of the selection transistor, the upper gate electrode of the selection transistor and the first gate electrode of the memory transistor are formed on the upper gate insulating film of the selection transistor. and the first gate electrode can be formed simultaneously in one step, and the interlayer insulating film provided on the selection transistor in the conventional thin film E2 FROM can be made unnecessary. Therefore, this thin film E2PROM has a selection transistor equipped with two gate electrodes,
Furthermore, although the memory transistor is also equipped with two gate electrodes, one for writing and erasing and one for reading, compared to the case where the memory transistor of a conventional thin film E2PROM is provided with another gate electrode for reading, It is possible to efficiently manufacture the thin film E2PROM with a small number of steps, and the thickness of the entire thin film E2PROM can be reduced.

[Brief explanation of drawings]

1 and 2 are a cross-sectional view of a thin-film E2PROM and its manufacturing process diagram showing a first embodiment of the present invention, and FIG. 3 is a cross-sectional view of a thin-film E2PROM showing a second embodiment of the present invention. FIG. 4 is a sectional view of a conventional thin film E2PROM. 11...Substrate, Gloa...Lower gate electrode, 1
2... Lower gate insulating film, 13... i-type semiconductor layer,
14...n-type semiconductor layer, S10... source electrode, D
lo...Drain electrode, 15...Top gate insulating film, G10b...Top gate electrode, T2O...Memory transistor, GIO...Gate electrode (G loa
. . . first gate electrode), 16 . . . gate insulating film (
first gate insulating film), 17... i-type semiconductor layer, 18
... n-type semiconductor layer, S20 ... source electrode, D20
...Drain electrode, 20...Second gate insulating film,
G fob...second gate electrode, 19...protective insulating film.

Claims (2)

[Claims] (1) Thin film E^2P in which a memory transistor made of a thin film transistor and a selection transistor made of a thin film transistor with two gate electrodes are formed on a substrate.
In the ROM, on the substrate, a lower gate electrode for a selection transistor;
A lower gate insulating film for a selection transistor covering almost the entire surface of the substrate, a semiconductor layer for the selection transistor, source and drain electrodes for the selection transistor, and an upper gate insulating film for the selection transistor covering almost the entire surface of the substrate are laminated; An upper gate electrode for a selection transistor facing the semiconductor layer for the selection transistor and a gate electrode for the memory transistor are formed on the upper gate insulating film, and a charge storage function is formed on the gate electrode for the memory transistor. A thin film E^2PROM characterized in that a gate insulating film for a memory transistor, a semiconductor layer for a memory transistor, and source and drain electrodes for a memory transistor are laminated. (2) Thin film E^2P in which a memory transistor made of a thin film transistor and a selection transistor made of a thin film transistor with two gate electrodes are formed on a substrate.
In the ROM, on the substrate, a lower gate electrode for a selection transistor;
A lower gate insulating film for a selection transistor covering almost the entire surface of the substrate, a semiconductor layer for the selection transistor, source and drain electrodes for the selection transistor, and an upper gate insulating film for the selection transistor covering almost the entire surface of the substrate are laminated; An upper gate electrode for a selection transistor facing the semiconductor layer for the selection transistor and a first gate electrode for the memory transistor are formed on the upper gate insulating film, and on the first gate electrode,
A first gate insulating film for a memory transistor, a semiconductor layer for a memory transistor, a source and drain electrode for a memory transistor, a second gate insulating film for a memory transistor, and a second gate electrode for a memory transistor. and one of the first gate insulating film and the second gate insulating film for the memory transistor is an insulating film having a charge storage function, and the other gate insulating film has a charge storage function. In addition to creating an insulating film that does not swell,
Of the first gate electrode and second gate electrode for the memory transistor, the gate electrode facing the semiconductor layer for the memory transistor via a gate insulating film having a charge storage function is used as a writing and erasing electrode; A thin film E^2PROM characterized in that a gate electrode facing the memory transistor semiconductor layer via a gate insulating film having no charge storage function is used as a readout electrode.