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JPH0231447A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0231447A
JPH0231447A JP18220688A JP18220688A JPH0231447A JP H0231447 A JPH0231447 A JP H0231447A JP 18220688 A JP18220688 A JP 18220688A JP 18220688 A JP18220688 A JP 18220688A JP H0231447 A JPH0231447 A JP H0231447A
Authority
JP
Japan
Prior art keywords
oxide film
bonding pad
layer
semiconductor device
diffusion layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18220688A
Other languages
Japanese (ja)
Inventor
Takeshi Sato
剛 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18220688A priority Critical patent/JPH0231447A/en
Publication of JPH0231447A publication Critical patent/JPH0231447A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a semiconductor device of high reliability by a method wherein a diffusion layer, whose shape is similar to that of a bonding pad, is provided under the bonding pad and a wiring section which is led out from the bonding pad, and the bonding pad, the diffusion layer, and the wiring section are connected with each other. CONSTITUTION:An oxide film is formed on the surface of an N-type epitaxial layer 2 through thermal oxidation after the epitaxial layer 2 has been grown on a P-type silicon substrate 1, a P-type impurity ions such as of boron are implanted using the oxide film as a mask to form a P-type impurity layer 3, and the whole oxide film is removed. Next, a thermal oxide film 4 is grown, and the part of the oxide film 4 which forms a contact with the N-type impurity layer 3 is removed through a photolithography method. Then, metal such as Al or the like is deposited through an evaporation method, and an electrode wiring 5 and a contact are formed through a photolithography method.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関し、特に耐湿性を
改善する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that improves moisture resistance.

〔従来の技術〕[Conventional technology]

従来より半導体装置においては、水分の侵入があると、
金属電極や配線を腐食し、断線を生ずるので、耐湿性が
問題となり、種々の改善工夫がなされている。Traditionally, when moisture enters semiconductor devices,
Since it corrodes metal electrodes and wiring, causing wire breakage, moisture resistance becomes a problem, and various improvements have been made.

第２図（ａ）〜（ｃ）は従来の半導体装置の製造方法を
説明するための工程順に示した半導体チップの断面図で
゛ある。FIGS. 2(a) to 2(c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

まず、第２図（ａ）に示すように、Ｐ型シリコン基板１
の上にＮ型エピタキシャル層２、熱酸化膜４、電極配線
５を順次形成する。First, as shown in FIG. 2(a), a P-type silicon substrate 1
An N-type epitaxial layer 2, a thermal oxide film 4, and an electrode wiring 5 are sequentially formed thereon.

次に第２図（ｂ）に示すように、プラズマ窒化膜、ＣＶ
Ｄ酸化膜８を順次堆積する。Next, as shown in FIG. 2(b), plasma nitride film, CV
A D oxide film 8 is sequentially deposited.

次に、第３図（ｃ）に示すように、電極配線５の上部に
接続用の窓をあける。Next, as shown in FIG. 3(c), a connection window is opened above the electrode wiring 5.

このように、プラズマ窒化膜とＣＶＤ酸化膜で覆うこと
により内部に水分が侵入するのを防いでいた。In this way, by covering with the plasma nitride film and the CVD oxide film, moisture intrusion into the interior was prevented.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置内部への水の侵入を防ぎ、断
線を防止する方法は、接続用開口部からの水の侵入まで
は防ぐことができず、ボンディングパッドと配線を例え
ば、アルミニウム等の金属で配線した場合、これらを腐
食させてしまい、配線部を断線させてしまうという信頼
性上問題があった。The above-mentioned conventional method of preventing water from entering inside a semiconductor device and preventing wire breakage cannot prevent water from entering through the connection opening, and bonding pads and wiring cannot be connected to metals such as aluminum. If the wires are wired using the wires, they will corrode and the wires will become disconnected, which poses a problem in terms of reliability.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、半導体基板に回路素
子を形成する際に将来ボンディングパッド部と配線の一
部が形成される場所に拡散層を形成する工程と、前記半
導体基板表面を絶縁膜で覆う工程と、前記拡散層の上部
の前記絶縁膜を選択除去して開口部を形成する工程と、
電極配線を形成し前記拡散層と電極配線の一部とを接続
する工程とを含んで構成される。The method for manufacturing a semiconductor device of the present invention includes a step of forming a diffusion layer at a location where a bonding pad portion and a portion of wiring will be formed in the future when forming a circuit element on a semiconductor substrate, and covering the surface of the semiconductor substrate with an insulating layer. a step of selectively removing the insulating film above the diffusion layer to form an opening;
The method includes the steps of forming an electrode wiring and connecting the diffusion layer and a part of the electrode wiring.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図（ａ）〜（ｃ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.

まず、第１図（ａ）に示すように、Ｐ型シリコン基板１
にＮ型エピタキシャル層２を成長させた後、熱酸化によ
り、酸化膜を表面に形成し、酸化膜をマスクにホウ素の
ようなＰ型不純物を加速エネルギー３０ｋｅＶ、ドーズ
量５Ｘ１０”ｃｍ〜２でイオン注入して、Ｐ型不純物層
３を形成し、酸化膜を全面除去する。First, as shown in FIG. 1(a), a P-type silicon substrate 1
After growing an N-type epitaxial layer 2, an oxide film is formed on the surface by thermal oxidation, and using the oxide film as a mask, ions of a P-type impurity such as boron are ionized at an acceleration energy of 30 keV and a dose of 5 x 10" cm~2. A P-type impurity layer 3 is formed by implantation, and the oxide film is completely removed.

次に、第１図（ｂ）に示すように、熱酸化により熱酸化
膜４を約５００ｎｍの厚さに成長させ、Ｎ型不純物層３
とコンタクト形成する箇所の酸化膜４をホトリソグラフ
ィ法を用いて除去する。Next, as shown in FIG. 1(b), a thermal oxide film 4 is grown to a thickness of about 500 nm by thermal oxidation, and an N-type impurity layer 3 is grown.
The oxide film 4 at the location where the contact is to be formed is removed using a photolithography method.

次に、第１図（ｃ）に示すように、アルミニウム等の金
属を蒸着法により、約２μｍの厚さに堆積し、ホトリソ
グラフィ法を用いて電極配線５とコンタクトを形成する
。Next, as shown in FIG. 1(c), a metal such as aluminum is deposited to a thickness of about 2 μm by vapor deposition, and contacts with the electrode wiring 5 are formed using photolithography.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、ボンディングパッド部
とこれから引出される配線部の下に同形状の拡散層を形
成し、この拡散層とボンディングパッドと配線をつなげ
ることにより、水の侵入で配線金属が腐食し断線しても
、拡散層でつながるので導通不良を防止することができ
、信頼性上問題がない半導体装置を製造することができ
るという効果がある。As explained above, the present invention forms a diffusion layer of the same shape under the bonding pad part and the wiring part led out from this, and connects this diffusion layer, the bonding pad, and the wiring, thereby preventing the wiring from entering by water. Even if the metal corrodes and the wire breaks, the diffusion layer connects the wire, preventing conduction failure and producing a semiconductor device with no problems in terms of reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）〜（ｃ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第２図（ａ
）〜（Ｃ）は従来の半導体装置の製造方法の一例を説明
するための工程順に示した半導体チップの断面図である
。 １・・・Ｐ型シリコン基板、２・・・Ｎ型エピタキシャ
ル層、３・・・Ｐ型不純物層、４・・・熱酸化膜、５・
・・電極配線、７・・・プラズマ窒化膜、８・・・ＣＶ
Ｄ酸化膜。 ヅ 不　ｊ因1(a) to 1(c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (C) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an example of a conventional method for manufacturing a semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... N-type epitaxial layer, 3... P-type impurity layer, 4... thermal oxide film, 5...
... Electrode wiring, 7... Plasma nitride film, 8... CV
D oxide film. zufu j cause

Claims (1)

【特許請求の範囲】[Claims] 半導体基板に回路素子を形成する際に将来ボンディング
パッド部と配線の一部が形成される場所に拡散層を形成
する工程と、前記半導体基板表面を絶縁膜で覆う工程と
、前記拡散層の上部の前記絶縁膜を選択除去して開口部
を形成する工程と、電極配線を形成し前記拡散層と電極
配線の一部とを接続する工程とを含むことを特徴とする
半導体装置の製造方法。When forming a circuit element on a semiconductor substrate, a step of forming a diffusion layer in a place where a bonding pad portion and a part of wiring will be formed in the future, a step of covering the surface of the semiconductor substrate with an insulating film, and a step of forming an upper part of the diffusion layer. A method for manufacturing a semiconductor device, comprising the steps of selectively removing the insulating film to form an opening, and forming an electrode wiring and connecting the diffusion layer and a part of the electrode wiring.
JP18220688A 1988-07-20 1988-07-20 Manufacture of semiconductor device Pending JPH0231447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18220688A JPH0231447A (en) 1988-07-20 1988-07-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18220688A JPH0231447A (en) 1988-07-20 1988-07-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0231447A true JPH0231447A (en) 1990-02-01

Family

ID=16114210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18220688A Pending JPH0231447A (en) 1988-07-20 1988-07-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0231447A (en)

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