JPH0233218A - frequency synthesizer - Google Patents

Abstract

PURPOSE:To attain high speed phase locking and to improve noise immunity by forming a sufficient in-phase state at the intermittent operating mode and providing a 1-bit data latch and a gate circuit to a data input section so as to synthesize a strobe signal. CONSTITUTION:A control circuit 9 receiving an output of a phase comparator 3 and an intermittent control signal in the intermittent operation controls gate circuits 10, 11 controlling the input of a reference frequency divider 2 and a variable frequency divider 5 by a time for a phase error so as to make two inputs to the phase comparator 3 in phase. Moreover, the control circuit 9 forms a loop control signal shorter than the leading of the intermittent control signal by a prescribed time. A loop switch 8 is controlled directly by the loop control signal. The phase adjustment is applied at the start of the intermittent control by the operation so as to make the operation enough to be in a short locking time and the conventional mode of the frequency synthesizer is reached.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applied to a frequency synthesizer used in high-frequency multi-channel radio equipment, etc., and more specifically relates to a PLL type frequency synthesizer characterized by high-speed phase pull-in. It is.

Conventional Technology Frequency synthesizers are important components of multi-channel radio equipment, and achieving high-speed frequency pull-in characteristics and lowering power consumption are important issues for mobile radio equipment. A digital phase initialization circuit shown in Material C385-21 of the Institute of Electronics, Information and Communication Engineers Communication Systems Study Group is a method devised for high-speed frequency pull-in characteristics and low power consumption. A conventional digital phase initialization circuit will be described below with reference to FIG.

In FIG. 4, 1 is a reference oscillator whose output is frequency-divided by a reference frequency divider 2 and input to a 1-phase comparator 3 as a reference signal. 4 is a voltage controlled oscillator (hereinafter referred to as VCO)
The output is frequency-divided by a variable frequency divider 5 and inputted to a phase comparator 3. The output of the phase comparator 3 is connected to the reference frequency divider 2,
It is a phase difference component of the output of the variable frequency divider 5, and is inputted to the control terminal of the VCO 4 through a charge pump 6° low-pass filter 7 to control one phase difference. Through this operation, a stable output synchronized with the reference signal can be obtained from the VCO 4. By changing the frequency division ratio of the variable frequency divider 5, the output frequency of the VCO 4 can be changed.

Used in multi-channel radio equipment.

Furthermore, in order to reduce the power consumption of radio equipment, it is possible to turn off the power when it is not needed, which is generally referred to as intermittent operation. When the frequency synthesizer explained above is operated intermittently, it depends on the consistency of the system.

Furthermore, due to the effects of intermittent operation, it is necessary to stabilize the frequency in a short period of time. The following methods are being considered to achieve these goals. That is, the low-pass filter 7 holds the control voltage output at the required frequency when the power is turned off during one intermittent operation. At this time, the charge held may vary depending on the state of the charge pump 6, so a loop switch 8 is inserted between the charge pump 6 and the low-pass filter 7, and the loop switch 8 is opened when the power is turned off. Furthermore, when the power is turned on, the frequencies are the same but the phases are different, so a phase difference signal may be generated at the output of the phase comparator 3, which causes frequency fluctuations and requires time to stabilize the frequency. As a countermeasure to this problem, a method has been considered in which the reference frequency divider 2 is initialized with the output of the variable frequency divider 5, and the variable frequency divider 5 and the reference frequency divider 2 are brought into the same phase state to form a loop. Note that 9 is a control circuit that performs these controls.

Problems to be Solved by the Invention However, this method has a problem in that it takes time to enter one phase side because a sufficient in-phase state cannot be obtained. Furthermore, in low-voltage operation applications, there is a problem in that data changes due to noise that enters the data input section.

The present invention is intended to solve the above-mentioned problems of the prior art, and aims to achieve high-speed phase pull-in and improve noise resistance.

Means for Solving the Problems The present invention provides a multi-channel radio device that includes a first oscillator that outputs a reference frequency, a first reference frequency divider that divides the output of the first oscillator, and a target frequency. a second oscillator that outputs an output, a second frequency divider that variably divides the output of the second oscillator, and a phase comparator that compares the phases of the outputs of the first and second frequency dividers.

A charge pump that converts the output of the phase comparator and uses it as a drive signal for an integrator, and an integrator that integrates the output of the charge pump and controls the second oscillator, and further includes the first oscillator. a first gate circuit between the second oscillator and the first frequency divider, a second gate circuit between the second oscillator and the second frequency divider or within the second frequency divider, and a second gate circuit between the second oscillator and the second frequency divider; a third gate circuit between the frequency divider and the integrator, a shift register having three or more pits which receives the output of the first or second frequency divider and the frequency synthesizer control signal as input, and the output of the phase comparator. The above object is achieved by a control circuit consisting of two gate circuits whose inputs are the output of the shift register and the output of the shift register. Further, the signal from the strobe input terminal and the output signal of the 1-bit data latch are controlled by a gate circuit, and are input to the load terminal of the N-bit data latch, thereby inputting the output of the bit shift register to the N-bit data latch. With such an operating structure, strobe signals with a one-time difference can be synthesized, and a frequency synthesizer that is resistant to noise can be constructed.

Function The present invention uses the above-mentioned configuration to create a sufficient in-phase state in the intermittent operation mode, to perform frequency pull-in at high speed, and to synthesize strobe signals by providing a 1-bit data latch and a gate circuit in the data input section. This makes it a frequency synthesizer that is resistant to noise when inputting data.

Embodiment FIG. 1 is a block diagram of a frequency synthesizer in an embodiment of the present invention. In FIG. 1, 1 is a reference oscillator, 2
is a reference frequency divider whose input is the output of reference oscillator 1, and 4 is v
CO15 is a variable frequency divider whose input is the output of VCO4, 3
is a phase comparator that receives the outputs of the reference frequency divider 2 and variable frequency divider 5 as input, 6 is a charge pump that receives the output of phase comparator 3 as input, and 7 is a low-pass that receives the output of charge pump 6 as input. filter; 8 is a loop switch that switches between the charge pump 6 and the low-pass filter 7; 10.
11 is between the reference oscillator 1 and the reference frequency divider 2 and the VCO
A gate circuit 9 is placed between the loop switch 8 and the variable frequency divider 5, and the gate circuit 9 receives the intermittent control signal, the output of the reference frequency divider 2 or the variable frequency divider 5, and the output of the phase comparator 3 as input. This is a control circuit that controls the gate circuit 10°11.

In the above configuration, the normal frequency synthesizer operation, which will be described below, is similar to the conventional technique. In intermittent operation, a gate circuit 10 controls the inputs of the reference frequency divider 2 and the variable frequency divider 5 by the control circuit 9 which receives the output of the -1 phase comparator 3 and the 1 intermittent control signal.
11 by the time corresponding to the phase error, and 2 of 1 phase comparator 3.
The two inputs are in phase. Further, the control circuit 9 generates a loop control signal that is shorter by a certain period of time than the rising edge of the intermittent control signal. This loop control signal causes the loop switch 8 to
direct control. Due to these actions.

At the beginning of intermittent control, one phase adjustment is performed to achieve a state that requires a short pull-in time, and then the normal frequency synthesizer mode is set.

FIG. 2 is a configuration diagram of the control circuit 9 in one embodiment of the present invention. In FIG. 2, 12 is a 3-bit shift register whose clock input is the output of the reference frequency divider 2 or the variable frequency divider 5 and whose reset input is the intermittent control signal 1;
．． 14 is the output of the shift register 12 and the phase comparator 106
This is a gate circuit that has an output and an input.

The operation of the above configuration will be explained below. 3
A bit shift register 12 generates a loop control signal that is shorter by three reference periods than the rising edge of the intermittent control. This loop control signal directly controls the switch circuit 8. Further, the control signals for the gate circuits 10 and 11 are created so that the loop control signal and the output of the phase comparator 3 are gated by the gate circuits 13 and 14, and the phase is adjusted by three reference periods of one intermittent control rise. Through these operations, one phase adjustment is performed at the beginning of one intermittent control, and after a short pull-in time is achieved, the normal frequency synthesizer mode is established.

FIG. 3 is a configuration diagram of a main part frequency synthesizer setting data input section in an embodiment of the present invention.

In FIG. 3, 15 is an N-bit shift register;
6 is an N-bit data latch, 17 is a 1-pit data latch, 18 is a gate circuit, and 19, 20.degree. 21 are clock, data, and strobe input terminals, respectively.

The operation of the above configuration will be explained below. The signal from the data input terminal 20 is input to the N-bit shift register 15 by the signal from the clock input terminal 19, and the data pushed out from the N-bit shift register 15 is input to the 1-bit data latch 17. Signal from strobe input terminal 21 and 1-bit data latch 17
The output signal of the N-bit shift register 15 is controlled by the gate circuit 18 and inputted to the load terminal of the N-bit data latch 16, thereby inputting the output signal of the N-bit shift register 15 to the N-bit data latch 16. With such an operating structure, strobe signals with time differences are synthesized, and a frequency synthesizer that is resistant to noise can be constructed.

As described above, according to the present embodiment, the gate circuit 10. 11- by providing a shift register 12 and gate circuits 13 and 14 as the control circuit 9.
High-speed phase pull-in can be achieved during intermittent work. Further, by providing a 1-bit data latch 17 and a gate circuit 18 in the data input section and synthesizing strobe signals, a frequency synthesizer that is resistant to noise during data input can be obtained.

Effects of the Invention As described above, the present invention can create a sufficient in-phase state during one intermittent operation and perform frequency pull-in at high speed, and the data input section can improve noise resistance, which has great effects.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a frequency synthesizer according to an embodiment of the present invention, Fig. 2 is a block diagram of a control circuit which is the main part of the frequency synthesizer, and Fig. 3 is a block diagram of the data input section which is the main part of the same. , FIG. 4 is a block diagram of a conventional intermittent operation type frequency synthesizer. 1... Reference oscillator, 2... Frequency divider, 3... Phase comparator. 4... Voltage controlled token, 5... Frequency divider (variable frequency divider). 60. Charge pump, 7... Loop filter (low-pass filter, integrator), 8... Loop switch. 9,...control circuit, 10.11.13.14...
gate circuit. 12...Shift register, 15...N-bit shift register, 16. ,, N focus data latch, 17...
・1 pit data latch, 18...gate circuit. Name of agent Patent attorney Shigetaka Awano Haka1 Takuchi Yu Aya

Claims (3)

[Claims] (1) a first oscillator that outputs a reference frequency;
a first frequency divider that divides the output of the oscillator; a second oscillator that outputs a target frequency; a second frequency divider that variably divides the output of the second oscillator; , a phase comparator that compares the phases of the output of the second frequency divider, a charge pump that converts the output of the phase comparator and uses it as a driving signal for the integrator, and a charge pump that integrates the output of the charge pump and uses the second an integrator for controlling an oscillator, a first gate circuit between the first oscillator and the first frequency divider, and a first gate circuit between the second oscillator and the second frequency divider. or a second gate circuit within the second frequency divider, a third gate circuit between the phase comparator and the integrator, and a frequency synthesizer control signal between the output of the first or second frequency divider and the frequency synthesizer control signal. A control circuit comprising a shift register of 3 bits or more that receives as input, and fourth and fifth gate circuits that receive as input the output of the phase comparator and the output of the shift register. synthesizer. (2) The frequency synthesizer according to claim 1, further comprising a charge pump whose output signal is controlled by a signal from a control circuit, and which performs the function of the third gate circuit. (3) A frequency division number setting circuit consisting of a shift register and a data latch is a logical product of 1 bit in the shift register or a 1 bit data latch output placed either before or after the shift register and a data strobe signal. 2. The frequency synthesizer according to claim 1, wherein the data latch is controlled by a frequency synthesizer.