JPH0235779A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to the use of LDD (Lightly Doped
In a field effect transistor with a drain structure, a gap is provided between the low concentration diffusion layer region and the substrate surface to suppress the injection of hot carriers into the sidewall film, or a magnetic material is added to a part of the MO3 field effect transistor. The invention relates to controlling injection of hot gear by providing a.

BACKGROUND OF THE INVENTION Conventionally, there has been a structure example in which a high concentration diffusion layer region is provided below a low concentration diffusion layer region to suppress the hot carrier effect, but there is no example of suppressing the hot carrier effect using a magnetic material.

Problems to be Solved by the Invention In a conventional LDD structure field effect transistor, there are many electron traps from the low concentration diffusion layer region to the sidewall film, and as a result, the resistance of the low concentration diffusion layer region becomes high.
Current drive ability tends to decrease.

In a semiconductor device with a fine structure, the components in the low concentration diffusion layer region are more likely to influence the device characteristics.

The present invention has been made in view of the various drawbacks of conventional semiconductor devices as described above, and an object of the present invention is to provide a highly reliable semiconductor device that is less susceptible to deterioration due to pot carriers and the like.

Means for Solving the Problems The present invention is a semiconductor device characterized in that a gap is provided between a low concentration diffusion layer region and a surface of a semiconductor substrate.

By providing an insulating layer between the low concentration diffusion layer region and the surface of the semiconductor substrate, hot carrier injection into the sidewall film can be prevented.

Embodiment FIG. 1(a) shows that a polysilicon gate 3 provided on a p-type thick conductive type semiconductor substrate through a gate oxide film 2 is etched shallowly into a semiconductor substrate 1 using a mask, and then etched by ion implantation. An n-type diffusion layer 4 is formed therein.

In FIG. 1(b), an insulating layer 5 is provided on the etched portion of the semiconductor substrate 1, and a sidewall film is further formed.

In FIG. 1C, an n + -type scattering layer 7 is formed by ion implantation using the sidewall film 6 as a mask, and a gap is finally formed between the n - diffusion layer 4 and the surface of the semiconductor substrate 1 .

In FIG. 2, silicon trenches are dug on both sides of the polysilicon gate 3, and n~ is diffused in the same process as above. 4
A gap is formed between the surface of the semiconductor substrate 1 and the surface of the semiconductor substrate 1.

No. 314 is a type in which a trench is dug at the end of the drain, a magnetic material 10 is buried therein, and an insulating layer 11 is provided at the bottom of the groove. By penetrating into the gate oxide film 2 (FIG. 2(b)), traps caused by injection of hot carriers into the gate oxide film 2 are suppressed.

FIG. 3(C) is a plan view of this.

Furthermore, in FIG. 3C, it is also possible to use the magnetic material 10 as a memory element using a floating gate structure by embedding the magnetic material 10 near the center of the polysilicon gate 3 in the gate length direction or over the entire area from a to C (
However, in this case, the direction of the magnetic field must be reversed.)

Effects of the Invention The present invention has the above-described structure, and utilizes the etching of the semiconductor substrate and the insulating layer to create a gap between the low concentration diffusion layer and the surface of the semiconductor substrate, thereby preventing hot water from reaching the sidewall film. By suppressing carrier injection, this prevents the acceleration of hot carrier deterioration in fine semi-conductor devices.

Furthermore, by embedding the magnetic material inside the substrate, the pot carrier is tightly packed inside the substrate, thereby preventing acceleration of hot carrier deterioration. Conversely, by intentionally injecting electrons into the oxide film, it is used as a memory element.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the manufacturing process of a semiconductor device according to one embodiment of the present invention, FIG. 2 is a sectional view of the manufacturing process of another embodiment, and FIG. 3 is a sectional view of the structure of another embodiment, and a diagram explaining the concept of operation. and a top view. 1...p-type conductivity type semiconductor substrate, 2...
Gate oxide film, 3...Polysilicon gate, 4
......n-type diffusion layer, 5...Insulating layer, 6
・・・・・・Sidewall membrane, 7・・・・・・Name of n+ type scattering layer agent Patent attorney Shigetaka Awano Figure 1

Claims (5)

[Claims] (1) LDD (Lightly Doped Drai)
n) A semiconductor device characterized in that, in a structured field effect transistor, a gap is provided between a low concentration diffusion layer region and a surface of a semiconductor substrate. (2) A semiconductor device characterized in that a magnetic material is provided in a portion of a MOS field effect transistor, and the direction of current is controlled by the magnetic material. (3) A substrate groove is provided so that lines of magnetic force pass under the gate electrode, and electrons are trapped in the floating gate to form a memory element.
The semiconductor device described in . (4) A method for manufacturing a semiconductor device, which comprises shallowly etching a semiconductor substrate using a gate electrode as a mask, and then forming a low concentration diffusion layer region. (5) After providing an insulating layer in the etched area and flattening the substrate surface, a sidewall film is formed, and a high concentration diffusion layer region is formed using the sidewall film as a mask. 4. A method for manufacturing a semiconductor device according to item 4.