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JPH023930A - Manufacture of multilayer electrode in semiconductor device - Google Patents

Manufacture of multilayer electrode in semiconductor device

Info

Publication number
JPH023930A
JPH023930A JP63153284A JP15328488A JPH023930A JP H023930 A JPH023930 A JP H023930A JP 63153284 A JP63153284 A JP 63153284A JP 15328488 A JP15328488 A JP 15328488A JP H023930 A JPH023930 A JP H023930A
Authority
JP
Japan
Prior art keywords
layer
deposition rate
deposition
vacuum
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63153284A
Other languages
Japanese (ja)
Other versions
JPH0691096B2 (en
Inventor
Naoharu Tsujimoto
辻本 直治
Akio Iwabuchi
昭夫 岩渕
Yoshifumi Kadowaki
門脇 良文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP63153284A priority Critical patent/JPH0691096B2/en
Publication of JPH023930A publication Critical patent/JPH023930A/en
Publication of JPH0691096B2 publication Critical patent/JPH0691096B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the permeation of metal constituting a second metal electrode into the lower part material by forming a first layer at a deposition rate smaller than a second layer, forming the first layer thicker than the second layer, and blocking the pass of the metal constituting the second metal electrode layer. CONSTITUTION:Cr layers 5a, 5b on an Al layer 4 side are subjected to vapor deposition at a comparatively small deposition rate, and a Cr layer 5c adjacent to a Cu layer 6 is subjected to vapor deposition at a comparatively large deposition rate. That is, the vacuum deposition is performed as follows: when the Cr layers 5a, 5b are formed, a beam current value is made small, and when the Cr layer 5c is formed, the beam current value is made large. Since the Cr layer 5b with a thickness formed at a reduced deposition rate is arranged in this manner, Cu diffusion from the Cu layer 6 to the Al layer 4 can be decreased, thereby increasing the adhesion between the Al layer 4 and an SiO2 layer 2, and preventing the exfoliation of this part.

Description

【発明の詳細な説明】 [産業上の利用分野コ 本発明は半導体装置における多層電極の製造方法に関し
、更に詳細には異なる材料から成る少なくとも2つの金
属電極層が積層されて取る半導体装置における多層電極
の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a multilayer electrode in a semiconductor device, and more particularly, to a method for manufacturing a multilayer electrode in a semiconductor device in which at least two metal electrode layers made of different materials are laminated. The present invention relates to a method for manufacturing an electrode.

〔従来の技術及び発明が解決しようとする課題〕フリッ
プチップのバンプ電極C突起状′I電極)は異なる材料
から成る金属電極層が積場された多層を極構造となって
いる。従来のバングを極は、シリコンから成る牛導体碩
域の±に複機された5iQ2膜(シリコン酸化層)の土
に順次に真空蒸着さj7’CA+ (7,++、< ニ
ウム3層、Cr(り−ム)N1.Cu(銅)層と、その
上Km気メツキにて肉厚に形成されたCu層と、更にそ
の上に形成された牛田層とから成る。A1層は、バンブ
電極から離すした所で半導体領域とオーピック接触して
いる配線!極層1゛ある。AI場がバンプik極の直下
で牛導体頌域とオービック接触している場合もある。C
u層は半田の何71全良好とするための半田付は金楕層
である。
[Prior Art and Problems to be Solved by the Invention] The bump electrode (C protrusion (I electrode)) of a flip chip has a multilayer polar structure in which metal electrode layers made of different materials are stacked one on top of the other. The poles of the conventional bang are sequentially vacuum-deposited on the soil of the 5iQ2 film (silicon oxide layer) compounded on the ± of the silicon conductor area. (Rem)N1.Consists of a Cu (copper) layer, a thick Cu layer formed on the Cu layer by Km plating, and a Ushida layer further formed on it.The A1 layer is a bump electrode. There is a wiring pole layer 1 which is in orbital contact with the semiconductor region at a distance from the bump. There is also a case where the AI field is in orbital contact with the conductor area directly under the bump ik pole.C.
The U layer is a gold elliptical layer to ensure good soldering.

また、 Cr層はA1層とCu層の接続を良好とするバ
ッファ金−層である。
Further, the Cr layer is a buffer gold layer that improves the connection between the A1 layer and the Cu layer.

バンプ[f&には特に引張強度が大きいことが要求され
るが、従来この種の多層1!極では、所定の引張強度が
得られないものが発生する頻度が比較的高かった。特に
、配線電極層(AI鳩)と5iU2膜との界面で剥離す
るものが多くみらt−した。この原因は、牛田付は金楕
層(Cu7m)を構成する金属(Cu )力しくソファ
金!Ar@rCr層)を通過して配線電極re(A、1
層)にかなり大量に拡散し、配線′!!i極島(A1層
)とS lo2膜の接着強度が低下することにある。牛
田付は金属にCu’PAu(金)などの重金属を使用し
た場合、それらの金属が牛導体飴域まで拡散すると、特
性劣化の原因にもなる。
Bumps [f& are required to have particularly high tensile strength, but conventionally this type of multilayer 1! In the case of poles, there was a relatively high frequency of cases in which the specified tensile strength could not be obtained. In particular, many peelings were observed at the interface between the wiring electrode layer (AI layer) and the 5iU2 film. The cause of this is that the metal (Cu) that makes up the gold elliptical layer (Cu7m) is so strong that the sofa gold! The wiring electrode re (A, 1
layer) in a fairly large amount, and the wiring'! ! This is because the adhesive strength between the i-polar island (A1 layer) and the S lo2 film decreases. If heavy metals such as Cu'PAu (gold) are used as the metal for Ushida Tsuke, if those metals diffuse into the Ushida conductor area, it may cause property deterioration.

ところで、特開昭54−92176号公報に。By the way, in Japanese Patent Application Laid-Open No. 54-92176.

ゴ゛a(タンタル)1−の上KAI層が形成さ才(た多
層電極構造において、AIJ−のAIが’I’a ff
曽を通過して更に”’F層に拡散するのを抑制するため
に、 Al /−のTa層側に酸化アルεニウムを多量
に含んたA1層を形成することが開示されている。Ta
層のA1層側全酸化タンタルを多量に含むTa層に形成
した構造と組合せる場合もある。これらの酸化物全多量
に含む金属層の形成は、真空蒸着の途中で真空槽内に水
分や酸素全速り込み(結果として真空槽中の圧力が高ま
る)、酸化性の比較的高い雰囲気で蒸着を行う。この蒸
着の前後には酸化物をほとんど含まない蒸着全行ワので
、真空槽中の圧力全所定の冒真空状態に保って蒸着全行
つ之後、上記酸化性雰囲気蒸着のために真空槽中の圧力
を高め、その後また真空槽中の圧力を所定の高真空状態
にもと丁といり工程を終ることになる。
In a multilayer electrode structure in which a KAI layer is formed on top of tantalum (tantalum) 1-, AI of AIJ- is 'I'a ff
It has been disclosed that an A1 layer containing a large amount of aluminum oxide is formed on the Ta layer side of the Al/- in order to suppress the diffusion of the aluminum oxide into the F layer.
It may be combined with a structure formed in a Ta layer containing a large amount of total tantalum oxide on the A1 layer side of the layer. The formation of a metal layer containing a large amount of these oxides is caused by moisture and oxygen quickly entering the vacuum chamber during vacuum deposition (as a result, the pressure in the vacuum chamber increases), and deposition in a relatively highly oxidizing atmosphere. I do. Before and after this evaporation, all the evaporation steps contain almost no oxide, so after all the evaporation steps are carried out while keeping the pressure in the vacuum chamber at a predetermined non-vacuum state, the pressure in the vacuum chamber is The pressure is increased, and then the pressure in the vacuum chamber is brought back to a predetermined high vacuum state to complete the process.

上記公開公報に開示されている発明を7リソプチツプの
バンプ電極の形成に適用する場合、真空蒸着で形成下る
Cu層のCr層と隣接する層を酸化銅を多量に含むCu
層として形成し、必要に応じてCr層のCu層とVa接
する層も酸化クロムを多量に含むCr層として形成下れ
ばよい。しかし、異種金属から成るCu層とCr層をこ
のよ5に形成した場合、Cu層とCr層の接着強度が低
下し、結果としてバンブ111極に要求される引張強度
を満亀させることができない。しかも、真空蒸着の途中
で真空槽内の圧力を変化させることも、制御が難しいし
時間も増えることになり、″に産向きとは言えない。
When the invention disclosed in the above-mentioned publication is applied to the formation of bump electrodes of 7 lithographic chips, the layer adjacent to the Cr layer of the Cu layer formed by vacuum evaporation is made of Cu containing a large amount of copper oxide.
If necessary, a layer of the Cr layer in contact with the Cu layer and Va may also be formed as a Cr layer containing a large amount of chromium oxide. However, when the Cu layer and Cr layer made of different metals are formed in this way, the adhesive strength between the Cu layer and the Cr layer decreases, and as a result, the tensile strength required for the bump 111 pole cannot be achieved. . Moreover, changing the pressure inside the vacuum chamber during vacuum deposition is difficult to control and takes more time, which is not ideal for "vacuum deposition."

そこで本発明の目的は、海開接着強度の大きい多層II
極を量産性良く製造できる方法を提供することにある。
Therefore, the object of the present invention is to provide multilayer II with high sea-opening adhesive strength.
The object of the present invention is to provide a method for manufacturing poles with good mass productivity.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するための本発明は、少なくとも第1の
金属電極層とこれと異なる材料から成る第2の金属電極
層が順次隣接して形成された半導体装置における多/f
1m極の製造方法において、前記第1の金属電極層の一
部である第1の層を第1の蒸着速度で第1の厚さに真空
蒸着法によって形成し、前記第1の金属電極層の他の一
部である第2の層を前記第1の層上に前記第1の蒸着速
度よりも大きい第2の蒸着速度で前記第1の厚さより薄
い第2の厚さに真空蒸着法によって形成し、しかる後、
前記第2の層上に前記第2の金属電極層を形成すること
を特徴とする半導体装置における多層′電極の製造方法
に係わるものである。
To achieve the above object, the present invention provides a semiconductor device in which at least a first metal electrode layer and a second metal electrode layer made of a material different from the first metal electrode layer are successively formed adjacent to each other.
In the method for manufacturing a 1 m pole, a first layer that is a part of the first metal electrode layer is formed by a vacuum evaporation method to a first thickness at a first evaporation rate, and the first layer is a part of the first metal electrode layer. A second layer, which is another part of the layer, is deposited on the first layer to a second thickness thinner than the first thickness at a second deposition rate that is greater than the first deposition rate. formed by and then,
The present invention relates to a method for manufacturing a multilayer electrode in a semiconductor device, characterized in that the second metal electrode layer is formed on the second layer.

なお、上記発明と実施例との対応関係を説明すると、第
1の金属電極層はCr層5であり、第1の層は第1及び
第2のCr層5a、5bであジ、第2の層は第3のCr
層5cである。第2の金IWiI!極層はCu層6であ
る。
In addition, to explain the correspondence relationship between the above invention and the embodiments, the first metal electrode layer is the Cr layer 5, and the first layer is the first and second Cr layers 5a and 5b. The layer is the third Cr
This is layer 5c. Second gold IWiI! The pole layer is the Cu layer 6.

〔作 用〕[For production]

上記発明における第2の層は、第1の層よりも大きい蒸
着速度で形成されるので、第1の層と比較して、第2の
金1iJ電極層と大きな接着強度を持って積層される。
The second layer in the above invention is formed at a higher deposition rate than the first layer, so it is laminated with the second gold 1iJ electrode layer with greater adhesive strength than the first layer. .

第1のJ−は、第2の膚よりも小さい蒸着速度で形成さ
れ、かつ第2の膚よりも厚く形成されるので、第2の層
と比較して第2の金稿電@1層を構成する金属が通過し
ようとするのを阻止する働きが大きい。このため、第1
の金属電極層の下部邪材中に第2の金属1!極層を構成
する金属が侵入していくことに起因する不良発生が抑制
される。
The first J- layer is formed at a lower deposition rate than the second layer and is thicker than the second layer, so the second layer is less dense than the second layer. It has a great effect on preventing the metals that make up the structure from passing through. For this reason, the first
The second metal 1 in the lower evil material of the metal electrode layer! The occurrence of defects caused by penetration of the metal constituting the pole layer is suppressed.

〔実施例〕〔Example〕

本発明の一5iIIc施例に係わるバンプ電極と、その
製造方法について以下に説明する。
The bump electrode according to the 15iIIIc embodiment of the present invention and its manufacturing method will be described below.

第2図のバンプ電極1は、シリコンかうffる半導体領
域2の上に被覆された熱酸化によるS i02膜3の上
に形成さiておジ、AlNd、Cr層5.Cu層6,7
、半田層8から成る多層構造となっている。
The bump electrode 1 in FIG. 2 is formed on a thermally oxidized Si02 film 3 which is coated on a semiconductor region 2 made of silicon, an AlNd, and a Cr layer 5. Cu layer 6, 7
, and has a multilayer structure consisting of solder layers 8.

バンプ電極1を大造するに当っては、まず、SiO2膜
6の上に配置t極層としてA1層4を形成する。41層
4は、バンブを極1の最下層となる部分と半導体傾城2
にオーミック接触している部分(図示ゼす)とこtらを
接続する部分とから放る。
In fabricating the bump electrode 1, first, the A1 layer 4 is formed on the SiO2 film 6 as a t-pole layer. 41 Layer 4 connects the bump to the bottom layer of pole 1 and semiconductor tilted wall 2.
It is emitted from the part that is in ohmic contact with the (not shown) and the part that connects them.

A1層4は、全面的に真空蒸着を行った後、フォトエツ
チングにより所望のパターンに形成する。AI/?#4
の厚さは約1μmである。41層4の真空蒸着は周知の
電子衝撃法(電子ビーム蒸着法)にょジ行5゜fill
ち、所定の圧力(1QTorr程度)に保たれた真空槽
(ペルジャー)に被蒸着体としての半導体基板と薄膜材
料としてのAj板を対向させて配置する。つづいて、A
I板に電子ビームを照射して加熱し、 AI材を蒸発さ
せる。蒸発したA1分子ないしAI原子は半導体基板へ
と飛散し、その表面に凝縮してA1層を形成する。
The A1 layer 4 is vacuum-deposited over the entire surface and then formed into a desired pattern by photo-etching. AI/? #4
The thickness is approximately 1 μm. 41 Layer 4 was vacuum deposited using the well-known electron impact method (electron beam evaporation method).
First, a semiconductor substrate as a deposition target and an Aj plate as a thin film material are placed facing each other in a vacuum chamber (Pelger) maintained at a predetermined pressure (approximately 1 Q Torr). Next, A
The I plate is irradiated with an electron beam and heated to evaporate the AI material. The evaporated A1 molecules or AI atoms scatter to the semiconductor substrate and condense on its surface to form an A1 layer.

次に、 A1層4の上面にスパッタリングにより石英ガ
ラスからなる保護膜9を形成する。なお、保護膜9を全
面に形成し、しかる後、バンブを極1を形成丁べき箇所
に対応させてフォトエツチングにより開口10を形成す
る。
Next, a protective film 9 made of quartz glass is formed on the upper surface of the A1 layer 4 by sputtering. Note that the protective film 9 is formed on the entire surface, and then the openings 10 are formed by photo-etching with the bumps corresponding to the locations where the poles 1 are to be formed.

次に、Cr層とUu層を顯次真窒蒸着にて全面的に形成
し、7オトエツチングにより開口10の部分を残存させ
て01層5.Cu層6を形成する。Cr)*5.Cu層
乙の真空M看もA1層4と同様圧電子衝撃法による。 
Cr層5、Cu層6は開口10を通じて41層4と電気
的に接続されている。Cu層5の厚さは約3μmである
。Cr/ii5の厚さについては後述する。
Next, a Cr layer and a Uu layer are formed on the entire surface by next nitride deposition, and the opening 10 portion is left by etching 7, and the 01 layer and 5.0 layer are etched. A Cu layer 6 is formed. Cr) *5. The vacuum M of the Cu layer B was also measured by the piezoelectric impact method as with the A1 layer 4.
The Cr layer 5 and the Cu layer 6 are electrically connected to the 41 layer 4 through the opening 10. The thickness of the Cu layer 5 is approximately 3 μm. The thickness of Cr/ii5 will be described later.

次に、バンプ電極1の高さを確保てるために。Next, to ensure the height of the bump electrode 1.

Uu 1m 6の上面に!気メツキにて約30μmの厚
さのCuHz7選択的に形成する。つづいて、半田デイ
ツプあるいは手出ボールの載置及び溶融によりCuI曽
7の上面に半球状の半田層8を設ける。
On the top of Uu 1m 6! A CuHz7 layer with a thickness of about 30 μm is selectively formed by plating. Subsequently, a hemispherical solder layer 8 is provided on the upper surface of the CuI plate 7 by placing and melting a solder dip or a solder ball.

以上の説明は従来のバンプ11極の製法と伺ら変らない
。本実施例の従来例と異なる点はバッファ金属層である
01層5を第1図に示すよ5に蒸着速度と厚さを変えて
第1、第2及び第3の01層5a。
The above explanation is the same as the conventional manufacturing method for 11 bump poles. The difference between this embodiment and the conventional example is that the 01 layer 5, which is a buffer metal layer, is changed in deposition rate and thickness to the first, second and third 01 layers 5a as shown in FIG.

5b、5cKわけて形成したことにある。R口ち。The reason is that 5b and 5cK were formed separately. R mouth.

AI層4側の第1及び第2の01層5a、5bは比較的
蒸着速度を小さくして真全蒸着し、Cu層6に隣接する
第3のCr層5cは比較的蒸着速度を大きくして真空蒸
着する。この例では、第1.第2及び第3のCr/1I
5a、5b、5cをツレツレ毎分蒸着した。蒸着速度の
制御は薄膜材料としてのCr材に衝突させる電子ビーム
のビーム電流値を変えることで行う。即ち、第1及び第
2の01層5a。
The first and second 01 layers 5a and 5b on the side of the AI layer 4 are completely deposited at a relatively low deposition rate, and the third Cr layer 5c adjacent to the Cu layer 6 is deposited at a relatively high deposition rate. vacuum evaporate. In this example, the first. second and third Cr/1I
5a, 5b, and 5c were deposited every minute. The vapor deposition rate is controlled by changing the beam current value of the electron beam that is made to collide with the Cr material as the thin film material. That is, the first and second 01 layers 5a.

5bを形成するときはビーム電流値を小さくシ。When forming 5b, reduce the beam current value.

第3のCr層5Cを形成するときはビーム電流値を大き
くして真空蒸着する。第2のCr層5bの厚さは、第1
及び第3の01層5a、5cの厚さより太き(する。こ
の例では、第1.第2.第3の01層5a、5b、5c
の潔さはそれぞtz500A。
When forming the third Cr layer 5C, the beam current value is increased and vacuum evaporation is performed. The thickness of the second Cr layer 5b is the same as that of the first Cr layer 5b.
and the thickness of the third 01 layers 5a, 5c (in this example, the first, second and third 01 layers 5a, 5b, 5c
The cleanliness of each is tz500A.

3500A、500Aである。They are 3500A and 500A.

本実施例のバンプ電極は以下の効果を有する。The bump electrode of this example has the following effects.

fi+  蒸着速度を小さくして形成した肉厚の第2O
Cr層5bを投げたことにより、 Cu層6からのA1
層4へのCuの拡散全減少させることができ。
fi+ Thick second O formed by reducing the deposition rate
By throwing the Cr layer 5b, A1 from the Cu layer 6
The total diffusion of Cu into layer 4 can be reduced.

41層4と5102膜2の接着gi度が向止し、ここで
の剥llFを防止することができる。このメカニズムは
次のとおジである。真空蒸着の際に真空槽内の圧力を蒸
着を行’110Torr程度に下げたとき。
The degree of adhesion between the 41 layer 4 and the 5102 film 2 is controlled, and peeling at this point can be prevented. This mechanism is as follows. When the pressure inside the vacuum chamber is lowered to about 110 Torr during vacuum deposition.

残留ガス中にはHz0(水分)が比較的多量に含まれて
いる。Crは活性の強い金属であるから、Crの一部は
このHz Oと反応してクロム酸化物とHz(水素)ガ
スを発生させる。事実、真空槽内の残留ガスを分析する
と、 Crの蒸着を進めるに従ってHz0が減少し、H
zが増加することがN認される。
The residual gas contains a relatively large amount of Hz0 (moisture). Since Cr is a highly active metal, a portion of Cr reacts with this Hz O to generate chromium oxide and Hz (hydrogen) gas. In fact, analysis of the residual gas in the vacuum chamber shows that as Cr deposition progresses, Hz0 decreases and H
It is recognized that z increases.

このように、蒸着速度を小さくして真空蒸着をした第1
及び第2の01層5 a、 5 bは、酸化の度合が大
きく、蒸着速度を大きくして真空蒸着した第6のCr層
5cは酸化の度合が小さくなっている。
In this way, the first step was performed using vacuum evaporation at a lower evaporation speed.
The second 01 layers 5a and 5b have a high degree of oxidation, and the sixth Cr layer 5c, which is vacuum-deposited at a high deposition rate, has a low degree of oxidation.

酸化の度合とCUの拡散館止の関係は明確ではないが1
次のように考えらする。Cr層を構成する微小なCr粒
子の粒界には酸化忙よって生成されるクロム酸化物が存
在し、このクロム酸化物の存在が粒界を通って進行しよ
りとするCUの拡散を阻止するよりに作用する。従って
、酸化の度合の大きい第2のCr層5bは、酸化の度合
の小さい第6のCr層5CよジもCuの拡散全阻止する
能力が大きい。
Although the relationship between the degree of oxidation and the inhibition of CU diffusion is not clear, 1
Let's think about it as follows. Chromium oxide, which is produced by oxidation, is present at the grain boundaries of the minute Cr particles that make up the Cr layer, and the presence of this chromium oxide prevents the diffusion of CU, which would otherwise proceed through the grain boundaries. It works even better. Therefore, the second Cr layer 5b, which is highly oxidized, has a greater ability to completely inhibit Cu diffusion than the sixth Cr layer 5C, which is less oxidized.

もちろん、第1のOr層5aも、第3のCr層5cよ!
1lcuの拡散を阻止する能力が大きいが、酸化の度合
と厚さの面からCuの拡散を減少させているのは、主と
して第2のC,層5bである。なお、この実施例の場合
に:A1A1層のCuの含有量が従来より著しく減少し
たことはオージェ分析により確認した。
Of course, the first Or layer 5a is also the third Cr layer 5c!
It is mainly the second C layer 5b that has a large ability to inhibit the diffusion of 1 lcu, but reduces the diffusion of Cu in terms of the degree of oxidation and thickness. In this example, it was confirmed by Auger analysis that the Cu content of the A1A1 layer was significantly reduced compared to the conventional one.

(2(Cυ層6との@接部分を含む第3のCr J曽5
Cは蒸着速度を大きくして酸化の度合が小さくなるよう
に真空蒸着している。従って、CU層6との接着強度が
大きい。なお、Cr層5全全厚みに渡って蒸着速度を小
さくして形成した場合、 Cuの拡散を阻止する作用は
大きくできるが、01層5とCuJ曽6との接着強度が
小さくなってしまり。
(2(3rd Cr J so 5 including @ contact part with Cυ layer
C is vacuum deposited to increase the deposition rate and reduce the degree of oxidation. Therefore, the adhesive strength with the CU layer 6 is high. Note that when the Cr layer 5 is formed at a lower deposition rate over the entire thickness, the effect of inhibiting Cu diffusion can be increased, but the adhesive strength between the 01 layer 5 and the CuJ layer 6 is reduced.

(31第1の01層5aの真空蒸着の速度を第2のCr
/15bに比べて大きくしている。このため、第1の0
1層5aと41層4との妄Ng1度が大きい。
(31 The rate of vacuum deposition of the first 01 layer 5a is
It is larger than /15b. Therefore, the first 0
The difference Ng1 degree between the 1st layer 5a and the 41st layer 4 is large.

ただし、Cr層とA1層の接着性は比較的良好であるの
で、第1の01層5aの蒸着速度は第3のCr層5cに
比べて小さくしている。
However, since the adhesion between the Cr layer and the A1 layer is relatively good, the deposition rate of the first 01 layer 5a is set lower than that of the third Cr layer 5c.

(41蒸着速度を略一定として、真空槽内の圧力を変え
てH20含有量を制御てれは上記と同様の効果を有する
cr層5a、5b、5cを得ることができる。即ち、第
1及び第2の01層5a、5bの形成の際は真空槽内の
圧力を大きくシ、第3のCr層5cの形成の際は真空槽
内の圧力を小さくして真空蒸着する。しかし、真空槽内
の圧力を速やかにかつ大きく変化させるのは量産の場で
は困難である。その点、蒸着速度でcr層5の膜質を制
御する実施例の方法は実用性が高い。なお、真空槽内の
圧力を&極層に変えない場合でも、第1の層の蒸着から
第2及び第6の層の蒸着にかけて真壁槽内の圧力は徐々
に増加する。しかし、これは無視できる程度のものであ
る。
(41 By keeping the deposition rate approximately constant and controlling the H20 content by changing the pressure in the vacuum chamber, it is possible to obtain the CR layers 5a, 5b, and 5c having the same effects as above. When forming the second 01 layers 5a and 5b, the pressure in the vacuum chamber is increased, and when forming the third Cr layer 5c, the pressure inside the vacuum chamber is decreased and vacuum evaporation is performed. In mass production, it is difficult to change the internal pressure rapidly and greatly.In this respect, the method of the embodiment in which the film quality of the CR layer 5 is controlled by the vapor deposition rate is highly practical. Even if the pressure is not changed to the extreme layer, the pressure in the Makabe tank increases gradually from the deposition of the first layer to the deposition of the second and sixth layers. However, this is negligible. .

〔変形例〕[Modified example]

本発明は上述の実M例に1sIil定されるものでなく
、例えは次の変形が可能なものである。
The present invention is not limited to the above-mentioned actual example, but can be modified as follows.

ill  A1層とCr層との接着性は比較的良好であ
るので、 41層4との接着層として作用する第1のC
r層5aOM着速度は、第2のOr層5bと同等の蒸着
速度で形成してもよい。丁なわち、 01層5は、蒸着
速度を変えて真空蒸着し念2膚構造としてもよい。また
、4層以上としてもよい。この場合、01層6との接着
部分を含む領域を大きな蒸着速度で真空蒸着し、この軸
線の下部に位置する2層以上の領域を小さな蒸着速度で
真空蒸着する。
ill The adhesion between the A1 layer and the Cr layer is relatively good, so the first C layer acts as an adhesive layer with the 41 layer 4.
The r layer 5aOM may be formed at the same deposition rate as the second Or layer 5b. In other words, the 01 layer 5 may be vacuum-deposited at different deposition rates to form a two-dimensional structure. Moreover, it is good also as four or more layers. In this case, the region including the adhesive portion with the 01 layer 6 is vacuum-deposited at a high deposition rate, and the region of two or more layers located below this axis is vacuum-deposited at a low deposition rate.

(2)  蒸7#I速度を連続的に変化させて01層5
を形成してもよい。例えば、最初は中位の蒸着速度でス
タートシ1次第に蒸ft速度を遅くシ、シばらく小さい
蒸着速度で一定させた後1次第に蒸着速度を筒めて大き
い蒸着速度で01層5の形成を終了する。
(2) 01 layer 5 by continuously changing the steaming speed 7#I
may be formed. For example, start with a medium evaporation rate, gradually reduce the evaporation rate to 1, then keep it constant at a low evaporation rate, then gradually reduce the evaporation rate to a high evaporation rate to form the 01 layer 5. finish.

13ノ  真空槽中の圧力は、@?!!一定として01
層5の真壁蒸着を行うのが便利である。しかし、蒸着速
度を変えて01層5の酸化度合を制御する方法を主体と
して、真空槽中の圧力を少し変えて真空槽中のHtOの
含有量を制御する方法全補助的に組合せてもよい。
13. What is the pressure in the vacuum chamber? ! ! 01 as constant
It is convenient to carry out a true wall deposition of layer 5. However, the method of controlling the degree of oxidation of the 01 layer 5 by changing the deposition rate is the main method, and the method of controlling the content of HtO in the vacuum chamber by slightly changing the pressure in the vacuum chamber may be combined as an auxiliary method. .

+41  生出付は金属層としてAυ(金)、Ag(銀
)、I’yiにッケル)等ヲ使用し、バッファ電極ある
いはバッファを極兼オーiツク!極としてTi (チタ
ン)等を使用したときも、71層を01層5のように形
成丁れば本発明は有効である。
+41 For production, use Aυ (gold), Ag (silver), I'yi (nickel), etc. as the metal layer, and use the buffer electrode or buffer as the pole! Even when Ti (titanium) or the like is used as the electrode, the present invention is effective if the 71 layer is formed like the 01 layer 5.

(51第1の金属電極場が半導体細線に隣接した構造で
あっても、第1の金属!極層と半導体@城との剥離が問
題となるとき、あるいは第2の金属′11!@INの金
属妙:半導体細線に侵入することによる特性劣化が問題
になるとき1本発明は有効である。
(51 Even if the first metal electrode field is adjacent to the semiconductor thin wire, when peeling between the first metal! pole layer and the semiconductor @ castle is a problem, or the second metal '11! @ IN 1. The present invention is effective when deterioration of characteristics due to metal penetration into semiconductor thin wires becomes a problem.

また、第1の金F4電極層が絶縁物に隣接した構造であ
っても、PJ様の剥離−IP詩性劣化が問題になるとき
は本発明は有効である。
Further, even in a structure where the first gold F4 electrode layer is adjacent to an insulator, the present invention is effective when PJ-like peeling and deterioration of IP quality are a problem.

(61%に大きな機械的強度が要求されるバンブを極の
とき本発明は特に有効であるが1例えはワイヤホンティ
ングのためのパッドを構成する多層を極にも適用できる
(The present invention is particularly effective when used as poles for bumps that require a high mechanical strength of 61%, but it can also be applied to poles for multi-layered pads constituting wire honting pads, for example.

〔発明の効果〕〔Effect of the invention〕

上述のように、本発明によf(ば、引張強度が高いこと
によって扁信頼性で、かつ電気的特性を劣化させる原因
とならない牛導体装置の多層!極を実用性の高い製−a
′)5法によって提供することができる。
As described above, the present invention provides a highly practical multi-layer conductor device that has high tensile strength, is highly reliable, and does not cause deterioration of electrical characteristics.
') It can be provided by 5 methods.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に係わるバンブ電極の一部全
拡大して示す断面図。 第2図は一実施例のバンブ電極を示す断面図である。 、!1=AI層、 5−Cr h、 5 a =−第1
のCr1iii、5b・・・第2のCr層、5c・・・
第3のCr層、6・・・Cu層。 代  理  人   高  野  則  次第1図 第2図
FIG. 1 is a partially enlarged sectional view of a bump electrode according to an embodiment of the present invention. FIG. 2 is a sectional view showing a bump electrode of one embodiment. ,! 1=AI layer, 5-Cr h, 5 a=-1st
Cr1iii, 5b... second Cr layer, 5c...
Third Cr layer, 6...Cu layer. Agent Nori Takano Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 〔1〕少なくとも第1の金属電極層とこれと異なる材料
から成る第2の金属電極層が順次隣接して形成された半
導体装置における多層電極の製造方法において、 前記第1の金属電極層の一部である第1の層を第1の蒸
着速度で第1の厚さに真空蒸着法によつて形成し、 前記第1の金属電極層の他の一部である第2の層を前記
第1の層上に前記第1の蒸着速度よりも大きい第2の蒸
着速度で前記第1の厚さより薄い第2の厚さに真空蒸着
法によつて形成し、 しかる後、前記第2の層上に前記第2の金属電極層を形
成することを特徴とする半導体装置における多層電極の
製造方法。
[Scope of Claims] [1] A method for manufacturing a multilayer electrode in a semiconductor device in which at least a first metal electrode layer and a second metal electrode layer made of a material different from the first metal electrode layer are successively formed adjacent to each other, comprising: a first layer that is a part of the first metal electrode layer is formed by a vacuum evaporation method to a first thickness at a first evaporation rate; forming a second layer on the first layer to a second thickness thinner than the first thickness at a second deposition rate higher than the first deposition rate; . A method for manufacturing a multilayer electrode in a semiconductor device, comprising forming the second metal electrode layer on the second layer.
JP63153284A 1988-06-21 1988-06-21 Method for manufacturing multilayer electrode in semiconductor device Expired - Fee Related JPH0691096B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63153284A JPH0691096B2 (en) 1988-06-21 1988-06-21 Method for manufacturing multilayer electrode in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63153284A JPH0691096B2 (en) 1988-06-21 1988-06-21 Method for manufacturing multilayer electrode in semiconductor device

Publications (2)

Publication Number Publication Date
JPH023930A true JPH023930A (en) 1990-01-09
JPH0691096B2 JPH0691096B2 (en) 1994-11-14

Family

ID=15559109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63153284A Expired - Fee Related JPH0691096B2 (en) 1988-06-21 1988-06-21 Method for manufacturing multilayer electrode in semiconductor device

Country Status (1)

Country Link
JP (1) JPH0691096B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5188329A (en) * 1991-10-23 1993-02-23 Tachi-S Co. Ltd. Structure for covering slide railing seat adjuster
KR100956210B1 (en) * 2007-06-19 2010-05-04 에어 프로덕츠 앤드 케미칼스, 인코오포레이티드 Plasma Enhanced Cyclic Deposition of Metal Silicon Nitride Thin Films
JP2017130823A (en) * 2016-01-21 2017-07-27 京セラ株式会社 Piezoelectric oscillator and manufacturing method of the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5915181A (en) * 1982-02-12 1984-01-26 ゲ−ツエ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフッング Double door loaded in closing direction by spring

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5915181A (en) * 1982-02-12 1984-01-26 ゲ−ツエ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフッング Double door loaded in closing direction by spring

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5188329A (en) * 1991-10-23 1993-02-23 Tachi-S Co. Ltd. Structure for covering slide railing seat adjuster
KR100956210B1 (en) * 2007-06-19 2010-05-04 에어 프로덕츠 앤드 케미칼스, 인코오포레이티드 Plasma Enhanced Cyclic Deposition of Metal Silicon Nitride Thin Films
JP2017130823A (en) * 2016-01-21 2017-07-27 京セラ株式会社 Piezoelectric oscillator and manufacturing method of the same

Also Published As

Publication number Publication date
JPH0691096B2 (en) 1994-11-14

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